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30fd2a5dcc
Move GR HAL operation g->ops.gr.init_fs_state to hal.gr.init unit as g->ops.gr.init.fs_state. Copy the corresponding hal function for init fs_state to the hal.gr.init files. JIRA NVGPU-2951 Change-Id: Icaf47e8872cc74a5a7430026633c52b47cfc879b Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/2073381 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
98 lines
2.8 KiB
C
98 lines
2.8 KiB
C
/*
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* Copyright (c) 2019, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#include <nvgpu/gk20a.h>
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#include <nvgpu/gr/gr.h>
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#include <nvgpu/gr/config.h>
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u32 nvgpu_gr_get_idle_timeout(struct gk20a *g)
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{
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return nvgpu_is_timeouts_enabled(g) ?
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g->gr_idle_timeout_default : UINT_MAX;
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}
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int nvgpu_gr_init_fs_state(struct gk20a *g)
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{
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u32 tpc_index, gpc_index;
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u32 sm_id = 0;
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u32 fuse_tpc_mask;
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u32 gpc_cnt, tpc_cnt, max_tpc_cnt;
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int err = 0;
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struct nvgpu_gr_config *gr_config = g->gr.config;
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nvgpu_log_fn(g, " ");
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err = g->ops.gr.init.fs_state(g);
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if (err != 0) {
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return err;
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}
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if (g->ops.gr.init_sm_id_table != NULL) {
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err = g->ops.gr.init_sm_id_table(g);
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if (err != 0) {
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return err;
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}
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/* Is table empty ? */
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if (g->gr.no_of_sm == 0U) {
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return -EINVAL;
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}
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}
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for (sm_id = 0; sm_id < g->gr.no_of_sm; sm_id++) {
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tpc_index = g->gr.sm_to_cluster[sm_id].tpc_index;
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gpc_index = g->gr.sm_to_cluster[sm_id].gpc_index;
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g->ops.gr.program_sm_id_numbering(g, gpc_index, tpc_index, sm_id);
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}
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g->ops.gr.init.pd_tpc_per_gpc(g);
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/* gr__setup_pd_mapping */
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g->ops.gr.setup_rop_mapping(g, &g->gr);
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g->ops.gr.init.pd_skip_table_gpc(g);
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fuse_tpc_mask = g->ops.gr.config.get_gpc_tpc_mask(g, gr_config, 0);
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gpc_cnt = nvgpu_gr_config_get_gpc_count(gr_config);
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tpc_cnt = nvgpu_gr_config_get_tpc_count(gr_config);
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max_tpc_cnt = nvgpu_gr_config_get_max_tpc_count(gr_config);
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if ((g->tpc_fs_mask_user != 0U) &&
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(fuse_tpc_mask == BIT32(max_tpc_cnt) - 1U)) {
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u32 val = g->tpc_fs_mask_user;
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val &= BIT32(max_tpc_cnt) - U32(1);
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tpc_cnt = (u32)hweight32(val);
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}
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g->ops.gr.init.cwd_gpcs_tpcs_num(g, gpc_cnt, tpc_cnt);
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g->ops.gr.load_tpc_mask(g);
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err = g->ops.gr.load_smid_config(g);
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if (err != 0) {
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nvgpu_err(g, "load_smid_config failed err=%d", err);
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}
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return err;
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}
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