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c7d43f5292
The CONFIG_NVGPU_NEXT config is no longer required now that ga10b and ga100 sources have been collapsed. However, the ga100, ga10b sources are not safety certified, so mark them as NON_FUSA by replacing CONFIG_NVGPU_NEXT with CONFIG_NVGPU_NON_FUSA. Move CONFIG_NVGPU_MIG to Makefile.linux.config and enable MIG support by default on standard build. Jira NVGPU-4771 Change-Id: Idc5861fe71d9d510766cf242c6858e2faf97d7d0 Signed-off-by: Antony Clince Alex <aalex@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2547092 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
66 lines
1.9 KiB
C
66 lines
1.9 KiB
C
/*
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* Copyright (c) 2017-2021, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifdef CONFIG_NVGPU_IOCTL_NON_FUSA
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#include <nvgpu/ptimer.h>
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#include <nvgpu/timers.h>
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#include <nvgpu/gk20a.h>
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#include <nvgpu/nvgpu_init.h>
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#include <nvgpu/power_features/cg.h>
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int nvgpu_ptimer_init(struct gk20a *g)
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{
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#if defined(CONFIG_NVGPU_NON_FUSA)
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nvgpu_cg_slcg_timer_load_enable(g);
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#endif
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return 0;
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}
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int nvgpu_get_timestamps_zipper(struct gk20a *g,
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u32 source_id, u32 count,
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struct nvgpu_cpu_time_correlation_sample *samples)
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{
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int err = 0;
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unsigned int i = 0;
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if (gk20a_busy(g) != 0) {
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nvgpu_err(g, "GPU not powered on\n");
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err = -EINVAL;
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goto end;
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}
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for (i = 0; i < count; i++) {
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err = g->ops.ptimer.read_ptimer(g, &samples[i].gpu_timestamp);
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if (err != 0) {
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return err;
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}
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samples[i].cpu_timestamp = nvgpu_hr_timestamp();
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}
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end:
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gk20a_idle(g);
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return err;
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}
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#endif
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