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df6d5ab07b
Add bar2 support for gp10b and set-up bar2 binding. Bug 1587825 Change-Id: I46660b3a28a5667ec782dd45b4528ae5f79e17c8 Signed-off-by: Seshendra Gadagottu <sgadagottu@nvidia.com> Reviewed-on: http://git-master/r/659236 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
85 lines
2.2 KiB
C
85 lines
2.2 KiB
C
/*
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* GP10B MMU
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*
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* Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#include <linux/pm_runtime.h>
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#include <linux/dma-mapping.h>
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#include "gk20a/gk20a.h"
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#include "mm_gp10b.h"
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#include "hw_ram_gp10b.h"
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#include "hw_bus_gp10b.h"
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u32 gp10b_mm_get_physical_addr_bits(struct gk20a *g)
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{
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return 36;
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}
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static int gb10b_init_bar2_vm(struct gk20a *g)
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{
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int err;
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struct mm_gk20a *mm = &g->mm;
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struct vm_gk20a *vm = &mm->bar2.vm;
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struct inst_desc *inst_block = &mm->bar2.inst_block;
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u32 big_page_size = gk20a_get_platform(g->dev)->default_big_page_size;
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/* BAR2 aperture size is 32MB */
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mm->bar2.aperture_size = 32 << 20;
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gk20a_dbg_info("bar2 vm size = 0x%x", mm->bar2.aperture_size);
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gk20a_init_vm(mm, vm, big_page_size, SZ_4K,
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mm->bar2.aperture_size, false, "bar2");
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/* allocate instance mem for bar2 */
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err = gk20a_alloc_inst_block(g, inst_block);
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if (err)
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goto clean_up_va;
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gk20a_init_inst_block(inst_block, vm, big_page_size);
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return 0;
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clean_up_va:
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gk20a_deinit_vm(vm);
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return err;
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}
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static int gb10b_init_bar2_mm_hw_setup(struct gk20a *g)
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{
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struct mm_gk20a *mm = &g->mm;
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struct inst_desc *inst_block = &mm->bar2.inst_block;
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phys_addr_t inst_pa = inst_block->cpu_pa;
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gk20a_dbg_fn("");
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g->ops.fb.set_mmu_page_size(g);
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inst_pa = (u32)(inst_pa >> bus_bar2_block_ptr_shift_v());
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gk20a_dbg_info("bar2 inst block ptr: 0x%08x", (u32)inst_pa);
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gk20a_writel(g, bus_bar2_block_r(),
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bus_bar2_block_target_vid_mem_f() |
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bus_bar2_block_mode_virtual_f() |
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bus_bar2_block_ptr_f(inst_pa));
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gk20a_dbg_fn("done");
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return 0;
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}
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void gp10b_init_mm(struct gpu_ops *gops)
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{
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gm20b_init_mm(gops);
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gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits;
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gops->mm.init_bar2_vm = gb10b_init_bar2_vm;
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gops->mm.init_bar2_mm_hw_setup = gb10b_init_bar2_mm_hw_setup;
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}
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