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Two new fifo hals are added. read_pbdma_data and reset_pbdma_header. In turing the instruction that caused the interrupt will be stored in NV_PPBDMA_PB_DATA0 register or NV_PPBDMA_HDR_SHADOW register, which is decided based on NV_PPBDMA_PB_COUNT value and PB_HEADER type JIRA NVGPU-1240 Change-Id: I54a92e317a6054335439d2d61bced28aff3eecb7 Signed-off-by: Vinod G <vinodg@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1990699 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
100 KiB
100 KiB