mirror of
git://nv-tegra.nvidia.com/linux-nvgpu.git
synced 2025-12-22 17:36:20 +03:00
fec60b6e6e
Add a way to force idle and reset the GPU in case where GPU rail gating is not supported (i.e. platform->can_railgate = false) In this case, we follow below sequence : - once GPU is idle, get runtime reference which enables the clocks - call prepare_poweroff() to save the state explicitly - perform explicit reset assert/deassert - call finalize_poweron() to restore the state - drop the runtime reference taken earlier Bug 1525284 Change-Id: Id5f3ec152093acd585631dfbf785d8e0561f9048 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: http://git-master/r/435620 GVS: Gerrit_Virtual_Submit Reviewed-by: Arto Merilainen <amerilainen@nvidia.com> Tested-by: Arto Merilainen <amerilainen@nvidia.com>
624 lines
17 KiB
C
624 lines
17 KiB
C
/*
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* drivers/video/tegra/host/gk20a/gk20a.h
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*
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* GK20A Graphics
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*
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* Copyright (c) 2011-2014, NVIDIA CORPORATION. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*/
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#ifndef _NVHOST_GK20A_H_
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#define _NVHOST_GK20A_H_
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struct gk20a;
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struct fifo_gk20a;
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struct channel_gk20a;
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struct gr_gk20a;
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struct sim_gk20a;
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struct gk20a_ctxsw_ucode_segments;
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struct acr_gm20b;
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#include <linux/sched.h>
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#include <linux/spinlock.h>
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#include <linux/nvhost_gpu_ioctl.h>
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#include <linux/tegra-soc.h>
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#include "../../../arch/arm/mach-tegra/iomap.h"
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#include "as_gk20a.h"
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#include "clk_gk20a.h"
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#include "fifo_gk20a.h"
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#include "tsg_gk20a.h"
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#include "gr_gk20a.h"
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#include "sim_gk20a.h"
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#include "pmu_gk20a.h"
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#include "priv_ring_gk20a.h"
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#include "therm_gk20a.h"
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#include "platform_gk20a.h"
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#include "gm20b/acr_gm20b.h"
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extern struct platform_device tegra_gk20a_device;
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bool is_gk20a_module(struct platform_device *dev);
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struct cooling_device_gk20a {
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struct thermal_cooling_device *gk20a_cooling_dev;
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unsigned int gk20a_freq_state;
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unsigned int gk20a_freq_table_size;
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struct gk20a *g;
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};
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enum gk20a_cbc_op {
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gk20a_cbc_op_clear,
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gk20a_cbc_op_clean,
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gk20a_cbc_op_invalidate,
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};
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struct gpu_ops {
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struct {
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int (*determine_L2_size_bytes)(struct gk20a *gk20a);
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void (*set_max_ways_evict_last)(struct gk20a *g, u32 max_ways);
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int (*init_comptags)(struct gk20a *g, struct gr_gk20a *gr);
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int (*cbc_ctrl)(struct gk20a *g, enum gk20a_cbc_op op,
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u32 min, u32 max);
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void (*set_zbc_color_entry)(struct gk20a *g,
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struct zbc_entry *color_val,
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u32 index);
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void (*set_zbc_depth_entry)(struct gk20a *g,
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struct zbc_entry *depth_val,
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u32 index);
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void (*init_cbc)(struct gk20a *g, struct gr_gk20a *gr);
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void (*sync_debugfs)(struct gk20a *g);
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void (*init_fs_state)(struct gk20a *g);
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void (*elpg_flush)(struct gk20a *g);
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void (*isr)(struct gk20a *g);
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u32 (*cbc_fix_config)(struct gk20a *g, int base);
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void (*flush)(struct gk20a *g);
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} ltc;
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struct {
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int (*init_fs_state)(struct gk20a *g);
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void (*access_smpc_reg)(struct gk20a *g, u32 quad, u32 offset);
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void (*bundle_cb_defaults)(struct gk20a *g);
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void (*cb_size_default)(struct gk20a *g);
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int (*calc_global_ctx_buffer_size)(struct gk20a *g);
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void (*commit_global_attrib_cb)(struct gk20a *g,
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struct channel_ctx_gk20a *ch_ctx,
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u64 addr, bool patch);
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void (*commit_global_bundle_cb)(struct gk20a *g,
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struct channel_ctx_gk20a *ch_ctx,
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u64 addr, u64 size, bool patch);
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int (*commit_global_cb_manager)(struct gk20a *g,
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struct channel_gk20a *ch,
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bool patch);
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void (*commit_global_pagepool)(struct gk20a *g,
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struct channel_ctx_gk20a *ch_ctx,
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u64 addr, u32 size, bool patch);
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void (*init_gpc_mmu)(struct gk20a *g);
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int (*handle_sw_method)(struct gk20a *g, u32 addr,
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u32 class_num, u32 offset, u32 data);
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void (*set_alpha_circular_buffer_size)(struct gk20a *g,
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u32 data);
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void (*set_circular_buffer_size)(struct gk20a *g, u32 data);
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void (*enable_hww_exceptions)(struct gk20a *g);
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bool (*is_valid_class)(struct gk20a *g, u32 class_num);
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void (*get_sm_dsm_perf_regs)(struct gk20a *g,
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u32 *num_sm_dsm_perf_regs,
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u32 **sm_dsm_perf_regs,
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u32 *perf_register_stride);
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void (*get_sm_dsm_perf_ctrl_regs)(struct gk20a *g,
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u32 *num_sm_dsm_perf_regs,
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u32 **sm_dsm_perf_regs,
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u32 *perf_register_stride);
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void (*set_hww_esr_report_mask)(struct gk20a *g);
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int (*setup_alpha_beta_tables)(struct gk20a *g,
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struct gr_gk20a *gr);
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int (*falcon_load_ucode)(struct gk20a *g,
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u64 addr_base,
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struct gk20a_ctxsw_ucode_segments *segments,
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u32 reg_offset);
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int (*load_ctxsw_ucode)(struct gk20a *g);
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} gr;
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const char *name;
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struct {
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void (*init_fs_state)(struct gk20a *g);
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void (*reset)(struct gk20a *g);
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void (*init_uncompressed_kind_map)(struct gk20a *g);
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void (*init_kind_attr)(struct gk20a *g);
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} fb;
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struct {
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void (*slcg_gr_load_gating_prod)(struct gk20a *g, bool prod);
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void (*slcg_perf_load_gating_prod)(struct gk20a *g, bool prod);
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void (*blcg_gr_load_gating_prod)(struct gk20a *g, bool prod);
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void (*pg_gr_load_gating_prod)(struct gk20a *g, bool prod);
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void (*slcg_therm_load_gating_prod)(struct gk20a *g, bool prod);
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} clock_gating;
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struct {
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void (*bind_channel)(struct channel_gk20a *ch_gk20a);
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void (*trigger_mmu_fault)(struct gk20a *g,
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unsigned long engine_ids);
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} fifo;
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struct pmu_v {
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/*used for change of enum zbc update cmd id from ver 0 to ver1*/
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u32 cmd_id_zbc_table_update;
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u32 (*get_pmu_cmdline_args_size)(struct pmu_gk20a *pmu);
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void (*set_pmu_cmdline_args_cpu_freq)(struct pmu_gk20a *pmu,
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u32 freq);
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void (*set_pmu_cmdline_args_trace_size)(struct pmu_gk20a *pmu,
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u32 size);
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void (*set_pmu_cmdline_args_trace_dma_base)(
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struct pmu_gk20a *pmu);
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void (*set_pmu_cmdline_args_trace_dma_idx)(
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struct pmu_gk20a *pmu, u32 idx);
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void * (*get_pmu_cmdline_args_ptr)(struct pmu_gk20a *pmu);
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u32 (*get_pmu_allocation_struct_size)(struct pmu_gk20a *pmu);
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void (*set_pmu_allocation_ptr)(struct pmu_gk20a *pmu,
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void **pmu_alloc_ptr, void *assign_ptr);
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void (*pmu_allocation_set_dmem_size)(struct pmu_gk20a *pmu,
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void *pmu_alloc_ptr, u16 size);
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u16 (*pmu_allocation_get_dmem_size)(struct pmu_gk20a *pmu,
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void *pmu_alloc_ptr);
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u32 (*pmu_allocation_get_dmem_offset)(struct pmu_gk20a *pmu,
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void *pmu_alloc_ptr);
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u32 * (*pmu_allocation_get_dmem_offset_addr)(
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struct pmu_gk20a *pmu, void *pmu_alloc_ptr);
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void (*pmu_allocation_set_dmem_offset)(struct pmu_gk20a *pmu,
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void *pmu_alloc_ptr, u32 offset);
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void (*get_pmu_init_msg_pmu_queue_params)(
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struct pmu_queue *queue, u32 id,
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void *pmu_init_msg);
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void *(*get_pmu_msg_pmu_init_msg_ptr)(
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struct pmu_init_msg *init);
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u16 (*get_pmu_init_msg_pmu_sw_mg_off)(
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union pmu_init_msg_pmu *init_msg);
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u16 (*get_pmu_init_msg_pmu_sw_mg_size)(
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union pmu_init_msg_pmu *init_msg);
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u32 (*get_pmu_perfmon_cmd_start_size)(void);
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int (*get_perfmon_cmd_start_offsetofvar)(
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enum pmu_perfmon_cmd_start_fields field);
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void (*perfmon_start_set_cmd_type)(struct pmu_perfmon_cmd *pc,
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u8 value);
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void (*perfmon_start_set_group_id)(struct pmu_perfmon_cmd *pc,
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u8 value);
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void (*perfmon_start_set_state_id)(struct pmu_perfmon_cmd *pc,
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u8 value);
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void (*perfmon_start_set_flags)(struct pmu_perfmon_cmd *pc,
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u8 value);
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u8 (*perfmon_start_get_flags)(struct pmu_perfmon_cmd *pc);
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u32 (*get_pmu_perfmon_cmd_init_size)(void);
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int (*get_perfmon_cmd_init_offsetofvar)(
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enum pmu_perfmon_cmd_start_fields field);
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void (*perfmon_cmd_init_set_sample_buffer)(
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struct pmu_perfmon_cmd *pc, u16 value);
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void (*perfmon_cmd_init_set_dec_cnt)(
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struct pmu_perfmon_cmd *pc, u8 value);
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void (*perfmon_cmd_init_set_base_cnt_id)(
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struct pmu_perfmon_cmd *pc, u8 value);
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void (*perfmon_cmd_init_set_samp_period_us)(
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struct pmu_perfmon_cmd *pc, u32 value);
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void (*perfmon_cmd_init_set_num_cnt)(struct pmu_perfmon_cmd *pc,
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u8 value);
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void (*perfmon_cmd_init_set_mov_avg)(struct pmu_perfmon_cmd *pc,
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u8 value);
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void *(*get_pmu_seq_in_a_ptr)(
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struct pmu_sequence *seq);
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void *(*get_pmu_seq_out_a_ptr)(
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struct pmu_sequence *seq);
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void (*set_pmu_cmdline_args_secure_mode)(struct pmu_gk20a *pmu,
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u32 val);
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} pmu_ver;
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struct {
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int (*get_netlist_name)(int index, char *name);
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bool (*is_fw_defined)(void);
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} gr_ctx;
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struct {
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int (*set_sparse)(struct vm_gk20a *vm, u64 vaddr,
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u32 num_pages, u32 pgsz_idx);
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} mm;
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struct {
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int (*prepare_ucode)(struct gk20a *g);
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int (*pmu_setup_hw_and_bootstrap)(struct gk20a *g);
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} pmu;
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};
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struct gk20a {
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struct platform_device *dev;
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struct platform_device *host1x_dev;
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struct resource *reg_mem;
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void __iomem *regs;
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void __iomem *regs_saved;
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struct resource *bar1_mem;
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void __iomem *bar1;
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void __iomem *bar1_saved;
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bool power_on;
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struct rw_semaphore busy_lock;
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struct clk_gk20a clk;
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struct fifo_gk20a fifo;
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struct gr_gk20a gr;
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struct sim_gk20a sim;
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struct mm_gk20a mm;
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struct pmu_gk20a pmu;
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struct acr_gm20b acr;
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struct cooling_device_gk20a gk20a_cdev;
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/* Save pmu fw here so that it lives cross suspend/resume.
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pmu suspend destroys all pmu sw/hw states. Loading pmu
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fw in resume crashes when the resume is from sys_exit. */
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const struct firmware *pmu_fw;
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u32 gr_idle_timeout_default;
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u32 timeouts_enabled;
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bool slcg_enabled;
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bool blcg_enabled;
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bool elcg_enabled;
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bool elpg_enabled;
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bool aelpg_enabled;
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bool forced_idle;
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bool forced_reset;
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#ifdef CONFIG_DEBUG_FS
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spinlock_t debugfs_lock;
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struct dentry *debugfs_ltc_enabled;
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struct dentry *debugfs_timeouts_enabled;
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struct dentry *debugfs_gr_idle_timeout_default;
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#endif
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struct gk20a_ctxsw_ucode_info ctxsw_ucode_info;
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/* held while manipulating # of debug/profiler sessions present */
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/* also prevents debug sessions from attaching until released */
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struct mutex dbg_sessions_lock;
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int dbg_sessions; /* number attached */
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int dbg_powergating_disabled_refcount; /*refcount for pg disable */
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void (*remove_support)(struct platform_device *);
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u64 pg_ingating_time_us;
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u64 pg_ungating_time_us;
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u32 pg_gating_cnt;
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spinlock_t mc_enable_lock;
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struct nvhost_gpu_characteristics gpu_characteristics;
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struct {
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struct cdev cdev;
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struct device *node;
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} channel;
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struct gk20a_as as;
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struct {
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struct cdev cdev;
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struct device *node;
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} ctrl;
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struct {
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struct cdev cdev;
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struct device *node;
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} dbg;
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struct {
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struct cdev cdev;
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struct device *node;
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} prof;
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struct {
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struct cdev cdev;
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struct device *node;
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} tsg;
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struct mutex client_lock;
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int client_refcount; /* open channels and ctrl nodes */
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dev_t cdev_region;
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struct class *class;
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struct gpu_ops ops;
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int irq_stall;
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int irq_nonstall;
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u32 max_ltc_count;
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u32 ltc_count;
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struct generic_pm_domain pd;
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struct devfreq *devfreq;
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struct gk20a_scale_profile *scale_profile;
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struct device_dma_parameters dma_parms;
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};
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static inline unsigned long gk20a_get_gr_idle_timeout(struct gk20a *g)
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{
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return g->timeouts_enabled ?
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g->gr_idle_timeout_default : MAX_SCHEDULE_TIMEOUT;
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}
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static inline struct gk20a *get_gk20a(struct platform_device *dev)
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{
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return gk20a_get_platform(dev)->g;
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}
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enum BAR0_DEBUG_OPERATION {
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BARO_ZERO_NOP = 0,
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OP_END = 'DONE',
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BAR0_READ32 = '0R32',
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BAR0_WRITE32 = '0W32',
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};
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struct share_buffer_head {
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enum BAR0_DEBUG_OPERATION operation;
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/* size of the operation item */
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u32 size;
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u32 completed;
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u32 failed;
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u64 context;
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u64 completion_callback;
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};
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struct gk20a_cyclestate_buffer_elem {
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struct share_buffer_head head;
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/* in */
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u64 p_data;
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u64 p_done;
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u32 offset_bar0;
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u16 first_bit;
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u16 last_bit;
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/* out */
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/* keep 64 bits to be consistent */
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u64 data;
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};
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/* debug accessories */
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#ifdef CONFIG_DEBUG_FS
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/* debug info, default is compiled-in but effectively disabled (0 mask) */
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#define GK20A_DEBUG
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/*e.g: echo 1 > /d/tegra_host/dbg_mask */
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#define GK20A_DEFAULT_DBG_MASK 0
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#else
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/* manually enable and turn it on the mask */
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/*#define NVHOST_DEBUG*/
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#define GK20A_DEFAULT_DBG_MASK (dbg_info)
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#endif
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enum gk20a_dbg_categories {
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gpu_dbg_info = BIT(0), /* lightly verbose info */
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gpu_dbg_fn = BIT(2), /* fn name tracing */
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gpu_dbg_reg = BIT(3), /* register accesses, very verbose */
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gpu_dbg_pte = BIT(4), /* gmmu ptes */
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gpu_dbg_intr = BIT(5), /* interrupts */
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gpu_dbg_pmu = BIT(6), /* gk20a pmu */
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gpu_dbg_clk = BIT(7), /* gk20a clk */
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gpu_dbg_map = BIT(8), /* mem mappings */
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gpu_dbg_gpu_dbg = BIT(9), /* gpu debugger/profiler */
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gpu_dbg_mem = BIT(31), /* memory accesses, very verbose */
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};
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#if defined(GK20A_DEBUG)
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extern u32 gk20a_dbg_mask;
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extern u32 gk20a_dbg_ftrace;
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#define gk20a_dbg(dbg_mask, format, arg...) \
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do { \
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if (unlikely((dbg_mask) & gk20a_dbg_mask)) { \
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if (gk20a_dbg_ftrace) \
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trace_printk(format "\n", ##arg); \
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else \
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pr_info("gk20a %s: " format "\n", \
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__func__, ##arg); \
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} \
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} while (0)
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#else /* GK20A_DEBUG */
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#define gk20a_dbg(dbg_mask, format, arg...) \
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do { \
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if (0) \
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pr_info("gk20a %s: " format "\n", __func__, ##arg);\
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} while (0)
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|
#endif
|
|
|
|
#define gk20a_err(d, fmt, arg...) \
|
|
dev_err(d, "%s: " fmt "\n", __func__, ##arg)
|
|
|
|
#define gk20a_warn(d, fmt, arg...) \
|
|
dev_warn(d, "%s: " fmt "\n", __func__, ##arg)
|
|
|
|
#define gk20a_dbg_fn(fmt, arg...) \
|
|
gk20a_dbg(gpu_dbg_fn, fmt, ##arg)
|
|
|
|
#define gk20a_dbg_info(fmt, arg...) \
|
|
gk20a_dbg(gpu_dbg_info, fmt, ##arg)
|
|
|
|
/* mem access with dbg_mem logging */
|
|
static inline u8 gk20a_mem_rd08(void *ptr, int b)
|
|
{
|
|
u8 _b = ((const u8 *)ptr)[b];
|
|
#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
|
|
gk20a_dbg(gpu_dbg_mem, " %p = 0x%x", ptr+sizeof(u8)*b, _b);
|
|
#endif
|
|
return _b;
|
|
}
|
|
static inline u16 gk20a_mem_rd16(void *ptr, int s)
|
|
{
|
|
u16 _s = ((const u16 *)ptr)[s];
|
|
#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
|
|
gk20a_dbg(gpu_dbg_mem, " %p = 0x%x", ptr+sizeof(u16)*s, _s);
|
|
#endif
|
|
return _s;
|
|
}
|
|
static inline u32 gk20a_mem_rd32(void *ptr, int w)
|
|
{
|
|
u32 _w = ((const u32 *)ptr)[w];
|
|
#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
|
|
gk20a_dbg(gpu_dbg_mem, " %p = 0x%x", ptr + sizeof(u32)*w, _w);
|
|
#endif
|
|
return _w;
|
|
}
|
|
static inline void gk20a_mem_wr08(void *ptr, int b, u8 data)
|
|
{
|
|
#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
|
|
gk20a_dbg(gpu_dbg_mem, " %p = 0x%x", ptr+sizeof(u8)*b, data);
|
|
#endif
|
|
((u8 *)ptr)[b] = data;
|
|
}
|
|
static inline void gk20a_mem_wr16(void *ptr, int s, u16 data)
|
|
{
|
|
#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
|
|
gk20a_dbg(gpu_dbg_mem, " %p = 0x%x", ptr+sizeof(u16)*s, data);
|
|
#endif
|
|
((u16 *)ptr)[s] = data;
|
|
}
|
|
static inline void gk20a_mem_wr32(void *ptr, int w, u32 data)
|
|
{
|
|
#ifdef CONFIG_TEGRA_SIMULATION_PLATFORM
|
|
gk20a_dbg(gpu_dbg_mem, " %p = 0x%x", ptr+sizeof(u32)*w, data);
|
|
#endif
|
|
((u32 *)ptr)[w] = data;
|
|
}
|
|
|
|
/* register accessors */
|
|
int gk20a_lockout_registers(struct gk20a *g);
|
|
int gk20a_restore_registers(struct gk20a *g);
|
|
|
|
static inline void gk20a_writel(struct gk20a *g, u32 r, u32 v)
|
|
{
|
|
gk20a_dbg(gpu_dbg_reg, " r=0x%x v=0x%x", r, v);
|
|
wmb();
|
|
writel_relaxed(v, g->regs + r);
|
|
}
|
|
static inline u32 gk20a_readl(struct gk20a *g, u32 r)
|
|
{
|
|
u32 v = readl(g->regs + r);
|
|
gk20a_dbg(gpu_dbg_reg, " r=0x%x v=0x%x", r, v);
|
|
return v;
|
|
}
|
|
|
|
static inline void gk20a_bar1_writel(struct gk20a *g, u32 b, u32 v)
|
|
{
|
|
gk20a_dbg(gpu_dbg_reg, " b=0x%x v=0x%x", b, v);
|
|
wmb();
|
|
writel_relaxed(v, g->bar1 + b);
|
|
}
|
|
|
|
static inline u32 gk20a_bar1_readl(struct gk20a *g, u32 b)
|
|
{
|
|
u32 v = readl(g->bar1 + b);
|
|
gk20a_dbg(gpu_dbg_reg, " b=0x%x v=0x%x", b, v);
|
|
return v;
|
|
}
|
|
|
|
/* convenience */
|
|
static inline struct device *dev_from_gk20a(struct gk20a *g)
|
|
{
|
|
return &g->dev->dev;
|
|
}
|
|
static inline struct gk20a *gk20a_from_as(struct gk20a_as *as)
|
|
{
|
|
return container_of(as, struct gk20a, as);
|
|
}
|
|
static inline struct gk20a *gk20a_from_pmu(struct pmu_gk20a *pmu)
|
|
{
|
|
return container_of(pmu, struct gk20a, pmu);
|
|
}
|
|
|
|
static inline u32 u64_hi32(u64 n)
|
|
{
|
|
return (u32)((n >> 32) & ~(u32)0);
|
|
}
|
|
|
|
static inline u32 u64_lo32(u64 n)
|
|
{
|
|
return (u32)(n & ~(u32)0);
|
|
}
|
|
|
|
static inline u32 set_field(u32 val, u32 mask, u32 field)
|
|
{
|
|
return ((val & ~mask) | field);
|
|
}
|
|
|
|
/* invalidate channel lookup tlb */
|
|
static inline void gk20a_gr_flush_channel_tlb(struct gr_gk20a *gr)
|
|
{
|
|
spin_lock(&gr->ch_tlb_lock);
|
|
memset(gr->chid_tlb, 0,
|
|
sizeof(struct gr_channel_map_tlb_entry) *
|
|
GR_CHANNEL_MAP_TLB_SIZE);
|
|
spin_unlock(&gr->ch_tlb_lock);
|
|
}
|
|
|
|
/* classes that the device supports */
|
|
/* TBD: get these from an open-sourced SDK? */
|
|
enum {
|
|
KEPLER_C = 0xA297,
|
|
FERMI_TWOD_A = 0x902D,
|
|
KEPLER_COMPUTE_A = 0xA0C0,
|
|
KEPLER_INLINE_TO_MEMORY_A = 0xA040,
|
|
KEPLER_DMA_COPY_A = 0xA0B5, /*not sure about this one*/
|
|
};
|
|
|
|
#if defined(CONFIG_GK20A_PMU)
|
|
static inline int support_gk20a_pmu(void)
|
|
{
|
|
return 1;
|
|
}
|
|
#else
|
|
static inline int support_gk20a_pmu(void){return 0;}
|
|
#endif
|
|
|
|
void gk20a_create_sysfs(struct platform_device *dev);
|
|
|
|
#ifdef CONFIG_DEBUG_FS
|
|
int clk_gk20a_debugfs_init(struct platform_device *dev);
|
|
#endif
|
|
|
|
#define GK20A_BAR0_IORESOURCE_MEM 0
|
|
#define GK20A_BAR1_IORESOURCE_MEM 1
|
|
#define GK20A_SIM_IORESOURCE_MEM 2
|
|
|
|
void gk20a_busy_noresume(struct platform_device *pdev);
|
|
int gk20a_busy(struct platform_device *pdev);
|
|
void gk20a_idle(struct platform_device *pdev);
|
|
void gk20a_disable(struct gk20a *g, u32 units);
|
|
void gk20a_enable(struct gk20a *g, u32 units);
|
|
void gk20a_reset(struct gk20a *g, u32 units);
|
|
int gk20a_get_client(struct gk20a *g);
|
|
void gk20a_put_client(struct gk20a *g);
|
|
|
|
const struct firmware *
|
|
gk20a_request_firmware(struct gk20a *g, const char *fw_name);
|
|
|
|
#define NVHOST_GPU_ARCHITECTURE_SHIFT 4
|
|
|
|
/* constructs unique and compact GPUID from nvhost_gpu_characteristics
|
|
* arch/impl fields */
|
|
#define GK20A_GPUID(arch, impl) ((u32) ((arch) | (impl)))
|
|
|
|
#define GK20A_GPUID_GK20A \
|
|
GK20A_GPUID(NVHOST_GPU_ARCH_GK100, NVHOST_GPU_IMPL_GK20A)
|
|
|
|
#define GK20A_GPUID_GM20B \
|
|
GK20A_GPUID(NVHOST_GPU_ARCH_GM200, NVHOST_GPU_IMPL_GM20B)
|
|
|
|
int gk20a_init_gpu_characteristics(struct gk20a *g);
|
|
|
|
#endif /* _NVHOST_GK20A_H_ */
|