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git://nv-tegra.nvidia.com/tegra/kernel-src/nv-kernel-display-driver.git
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jetson_35.
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l4t/l4t-r3
| Author | SHA1 | Date | |
|---|---|---|---|
|
5f54f1d5a5 |
@@ -1,7 +1,7 @@
|
||||
# NVIDIA Linux Open GPU Kernel Module Source
|
||||
|
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This is the source release of the NVIDIA Linux open GPU kernel modules,
|
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version 35.1.0.
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version 35.2.1.
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|
||||
|
||||
## How to Build
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||||
@@ -17,7 +17,7 @@ as root:
|
||||
|
||||
Note that the kernel modules built here must be used with gsp.bin
|
||||
firmware and user-space NVIDIA GPU driver components from a corresponding
|
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35.1.0 driver release. This can be achieved by installing
|
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35.2.1 driver release. This can be achieved by installing
|
||||
the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
|
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option. E.g.,
|
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|
||||
|
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@@ -72,7 +72,11 @@ EXTRA_CFLAGS += -I$(src)/common/inc
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||||
EXTRA_CFLAGS += -I$(src)
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||||
EXTRA_CFLAGS += -Wall -MD $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args
|
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EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
|
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EXTRA_CFLAGS += -DNV_VERSION_STRING=\"35.1.0\"
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EXTRA_CFLAGS += -DNV_VERSION_STRING=\"35.2.1\"
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|
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ifneq ($(SYSSRCHOST1X),)
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EXTRA_CFLAGS += -I$(SYSSRCHOST1X)
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endif
|
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|
||||
EXTRA_CFLAGS += -Wno-unused-function
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||||
|
||||
|
||||
@@ -860,9 +860,9 @@ struct drm_gem_object;
|
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|
||||
NV_STATUS NV_API_CALL nv_dma_import_sgt (nv_dma_device_t *, struct sg_table *, struct drm_gem_object *);
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void NV_API_CALL nv_dma_release_sgt(struct sg_table *, struct drm_gem_object *);
|
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NV_STATUS NV_API_CALL nv_dma_import_dma_buf (nv_dma_device_t *, struct dma_buf *, NvU32 *, void **, struct sg_table **, nv_dma_buf_t **);
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NV_STATUS NV_API_CALL nv_dma_import_from_fd (nv_dma_device_t *, NvS32, NvU32 *, void **, struct sg_table **, nv_dma_buf_t **);
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void NV_API_CALL nv_dma_release_dma_buf (void *, nv_dma_buf_t *);
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NV_STATUS NV_API_CALL nv_dma_import_dma_buf (nv_dma_device_t *, struct dma_buf *, NvU32 *, struct sg_table **, nv_dma_buf_t **);
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NV_STATUS NV_API_CALL nv_dma_import_from_fd (nv_dma_device_t *, NvS32, NvU32 *, struct sg_table **, nv_dma_buf_t **);
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void NV_API_CALL nv_dma_release_dma_buf (nv_dma_buf_t *);
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void NV_API_CALL nv_schedule_uvm_isr (nv_state_t *);
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@@ -151,6 +151,7 @@ test_headers() {
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FILES="$FILES linux/platform/tegra/dce/dce-client-ipc.h"
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FILES="$FILES linux/nvhost.h"
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FILES="$FILES linux/nvhost_t194.h"
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FILES="$FILES linux/host1x-next.h"
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FILES="$FILES asm/book3s/64/hash-64k.h"
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FILES="$FILES asm/set_memory.h"
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FILES="$FILES asm/prom.h"
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@@ -179,6 +179,153 @@ NvBool nvkms_syncpt_op(
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return NV_TRUE;
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}
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|
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#elif defined(NV_LINUX_HOST1X_NEXT_H_PRESENT) && defined(NV_LINUX_NVHOST_H_PRESENT)
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#include <linux/dma-fence.h>
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#include <linux/file.h>
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#include <linux/host1x-next.h>
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#include <linux/sync_file.h>
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|
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/*
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* If the host1x.h header is present, then we are using the upstream
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* host1x driver and so make sure CONFIG_TEGRA_HOST1X is defined to pick
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* up the correct prototypes/definitions in nvhost.h.
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*/
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#define CONFIG_TEGRA_HOST1X
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|
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#include <linux/nvhost.h>
|
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|
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#undef NVKMS_SYNCPT_STUBS_NEEDED
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|
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NvBool nvkms_syncpt_op(
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enum NvKmsSyncPtOp op,
|
||||
NvKmsSyncPtOpParams *params)
|
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{
|
||||
struct host1x_syncpt *host1x_sp;
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||||
struct platform_device *pdev;
|
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struct host1x *host1x;
|
||||
|
||||
pdev = nvhost_get_default_device();
|
||||
if (pdev == NULL) {
|
||||
nvkms_log(NVKMS_LOG_LEVEL_ERROR, NVKMS_LOG_PREFIX,
|
||||
"Failed to get nvhost default pdev");
|
||||
return NV_FALSE;
|
||||
}
|
||||
|
||||
host1x = nvhost_get_host1x(pdev);
|
||||
if (host1x == NULL) {
|
||||
nvkms_log(NVKMS_LOG_LEVEL_ERROR, NVKMS_LOG_PREFIX,
|
||||
"Failed to get host1x");
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return NV_FALSE;
|
||||
}
|
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|
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switch (op) {
|
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|
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case NVKMS_SYNCPT_OP_ALLOC:
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host1x_sp = host1x_syncpt_alloc(host1x,
|
||||
HOST1X_SYNCPT_CLIENT_MANAGED,
|
||||
params->alloc.syncpt_name);
|
||||
if (host1x_sp == NULL) {
|
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return NV_FALSE;
|
||||
}
|
||||
|
||||
params->alloc.id = host1x_syncpt_id(host1x_sp);
|
||||
break;
|
||||
|
||||
case NVKMS_SYNCPT_OP_PUT:
|
||||
host1x_sp = host1x_syncpt_get_by_id_noref(host1x, params->put.id);
|
||||
if (host1x_sp == NULL) {
|
||||
return NV_FALSE;
|
||||
}
|
||||
|
||||
host1x_syncpt_put(host1x_sp);
|
||||
break;
|
||||
|
||||
case NVKMS_SYNCPT_OP_FD_TO_ID_AND_THRESH: {
|
||||
|
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struct dma_fence *f;
|
||||
NvU32 id, thresh;
|
||||
int err;
|
||||
|
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f = sync_file_get_fence(params->fd_to_id_and_thresh.fd);
|
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if (f == NULL) {
|
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return NV_FALSE;
|
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}
|
||||
|
||||
if (dma_fence_is_array(f)) {
|
||||
struct dma_fence_array *array = to_dma_fence_array(f);
|
||||
|
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if (array->num_fences > 1) {
|
||||
/* Syncpoint fence fd contains more than one syncpoint */
|
||||
dma_fence_put(f);
|
||||
return NV_FALSE;
|
||||
}
|
||||
|
||||
f = array->fences[0];
|
||||
}
|
||||
|
||||
err = host1x_fence_extract(f, &id, &thresh);
|
||||
dma_fence_put(f);
|
||||
|
||||
if (err < 0) {
|
||||
return NV_FALSE;
|
||||
}
|
||||
|
||||
params->fd_to_id_and_thresh.id = id;
|
||||
params->fd_to_id_and_thresh.thresh = thresh;
|
||||
|
||||
break;
|
||||
}
|
||||
|
||||
case NVKMS_SYNCPT_OP_ID_AND_THRESH_TO_FD: {
|
||||
|
||||
struct sync_file *file;
|
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struct dma_fence *f;
|
||||
int fd;
|
||||
|
||||
host1x_sp = host1x_syncpt_get_by_id_noref(host1x,
|
||||
params->id_and_thresh_to_fd.id);
|
||||
if (host1x_sp == NULL) {
|
||||
return NV_FALSE;
|
||||
}
|
||||
|
||||
f = host1x_fence_create(host1x_sp,
|
||||
params->id_and_thresh_to_fd.thresh, true);
|
||||
if (IS_ERR(f)) {
|
||||
return NV_FALSE;
|
||||
}
|
||||
|
||||
fd = get_unused_fd_flags(O_CLOEXEC);
|
||||
if (fd < 0) {
|
||||
dma_fence_put(f);
|
||||
return NV_FALSE;
|
||||
}
|
||||
|
||||
file = sync_file_create(f);
|
||||
dma_fence_put(f);
|
||||
|
||||
if (!file) {
|
||||
return NV_FALSE;
|
||||
}
|
||||
|
||||
fd_install(fd, file->file);
|
||||
|
||||
params->id_and_thresh_to_fd.fd = fd;
|
||||
break;
|
||||
}
|
||||
|
||||
case NVKMS_SYNCPT_OP_READ_MINVAL:
|
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host1x_sp = host1x_syncpt_get_by_id_noref(host1x, params->read_minval.id);
|
||||
if (host1x_sp == NULL) {
|
||||
return NV_FALSE;
|
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}
|
||||
|
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params->read_minval.minval = host1x_syncpt_read(host1x_sp);
|
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break;
|
||||
}
|
||||
|
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return NV_TRUE;
|
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}
|
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#endif
|
||||
|
||||
|
||||
|
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@@ -1098,7 +1098,6 @@ NV_STATUS NV_API_CALL nv_dma_import_dma_buf
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nv_dma_device_t *dma_dev,
|
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struct dma_buf *dma_buf,
|
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NvU32 *size,
|
||||
void **user_pages,
|
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struct sg_table **sgt,
|
||||
nv_dma_buf_t **import_priv
|
||||
)
|
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@@ -1106,13 +1105,8 @@ NV_STATUS NV_API_CALL nv_dma_import_dma_buf
|
||||
nv_dma_buf_t *nv_dma_buf = NULL;
|
||||
struct dma_buf_attachment *dma_attach = NULL;
|
||||
struct sg_table *map_sgt = NULL;
|
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struct page **page_array = NULL;
|
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NV_STATUS status = NV_OK;
|
||||
|
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struct sg_page_iter sg_iter;
|
||||
NvU32 page_count = 0, page_idx = 0;
|
||||
|
||||
|
||||
if ((dma_dev == NULL) ||
|
||||
(dma_buf == NULL) ||
|
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(size == NULL) ||
|
||||
@@ -1154,52 +1148,16 @@ NV_STATUS NV_API_CALL nv_dma_import_dma_buf
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goto dma_buf_map_fail;
|
||||
}
|
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|
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|
||||
page_count = dma_buf->size >> PAGE_SHIFT;
|
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status = os_alloc_mem((void **)&page_array,
|
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sizeof(*page_array) * page_count);
|
||||
if (status != NV_OK)
|
||||
{
|
||||
NV_DMA_DEV_PRINTF(NV_DBG_ERRORS, dma_dev,
|
||||
"Can't allocate mem for pages!\n");
|
||||
goto page_array_alloc_fail;
|
||||
}
|
||||
|
||||
#if defined(for_each_sgtable_page)
|
||||
for_each_sgtable_page(map_sgt, &sg_iter, 0)
|
||||
#else
|
||||
for_each_sg_page(map_sgt->sgl, &sg_iter, map_sgt->orig_nents, 0)
|
||||
#endif
|
||||
{
|
||||
if (page_idx >= page_count)
|
||||
{
|
||||
NV_DMA_DEV_PRINTF(NV_DBG_ERRORS, dma_dev,
|
||||
"Page iterator exceeded max page count (%u)!\n",
|
||||
page_count);
|
||||
status = NV_ERR_INVALID_REQUEST;
|
||||
|
||||
goto page_count_fail;
|
||||
}
|
||||
|
||||
page_array[page_idx++] = sg_page_iter_page(&sg_iter);
|
||||
}
|
||||
|
||||
|
||||
nv_dma_buf->dma_buf = dma_buf;
|
||||
nv_dma_buf->dma_attach = dma_attach;
|
||||
nv_dma_buf->sgt = map_sgt;
|
||||
|
||||
*size = dma_buf->size;
|
||||
*user_pages = page_array;
|
||||
*import_priv = nv_dma_buf;
|
||||
*sgt = map_sgt;
|
||||
|
||||
return NV_OK;
|
||||
|
||||
page_count_fail:
|
||||
os_free_mem(page_array);
|
||||
page_array_alloc_fail:
|
||||
dma_buf_unmap_attachment(dma_attach, map_sgt, DMA_BIDIRECTIONAL);
|
||||
dma_buf_map_fail:
|
||||
dma_buf_detach(dma_buf, dma_attach);
|
||||
dma_buf_attach_fail:
|
||||
@@ -1214,7 +1172,6 @@ NV_STATUS NV_API_CALL nv_dma_import_from_fd
|
||||
nv_dma_device_t *dma_dev,
|
||||
NvS32 fd,
|
||||
NvU32 *size,
|
||||
void **user_pages,
|
||||
struct sg_table **sgt,
|
||||
nv_dma_buf_t **import_priv
|
||||
)
|
||||
@@ -1230,7 +1187,7 @@ NV_STATUS NV_API_CALL nv_dma_import_from_fd
|
||||
}
|
||||
|
||||
status = nv_dma_import_dma_buf(dma_dev,
|
||||
dma_buf, size, user_pages, sgt, import_priv);
|
||||
dma_buf, size, sgt, import_priv);
|
||||
dma_buf_put(dma_buf);
|
||||
|
||||
return status;
|
||||
@@ -1238,7 +1195,6 @@ NV_STATUS NV_API_CALL nv_dma_import_from_fd
|
||||
|
||||
void NV_API_CALL nv_dma_release_dma_buf
|
||||
(
|
||||
void *user_pages,
|
||||
nv_dma_buf_t *import_priv
|
||||
)
|
||||
{
|
||||
@@ -1249,15 +1205,6 @@ void NV_API_CALL nv_dma_release_dma_buf
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
if (user_pages == NULL)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
nv_dma_buf = (nv_dma_buf_t *)import_priv;
|
||||
dma_buf_unmap_attachment(nv_dma_buf->dma_attach, nv_dma_buf->sgt,
|
||||
DMA_BIDIRECTIONAL);
|
||||
@@ -1265,9 +1212,6 @@ void NV_API_CALL nv_dma_release_dma_buf
|
||||
dma_buf_put(nv_dma_buf->dma_buf);
|
||||
|
||||
os_free_mem(nv_dma_buf);
|
||||
|
||||
os_free_mem(user_pages);
|
||||
|
||||
}
|
||||
|
||||
#endif /* NV_LINUX_DMA_BUF_H_PRESENT */
|
||||
@@ -1279,7 +1223,6 @@ NV_STATUS NV_API_CALL nv_dma_import_dma_buf
|
||||
nv_dma_device_t *dma_dev,
|
||||
struct dma_buf *dma_buf,
|
||||
NvU32 *size,
|
||||
void **user_pages,
|
||||
struct sg_table **sgt,
|
||||
nv_dma_buf_t **import_priv
|
||||
)
|
||||
@@ -1292,7 +1235,6 @@ NV_STATUS NV_API_CALL nv_dma_import_from_fd
|
||||
nv_dma_device_t *dma_dev,
|
||||
NvS32 fd,
|
||||
NvU32 *size,
|
||||
void **user_pages,
|
||||
struct sg_table **sgt,
|
||||
nv_dma_buf_t **import_priv
|
||||
)
|
||||
@@ -1302,7 +1244,6 @@ NV_STATUS NV_API_CALL nv_dma_import_from_fd
|
||||
|
||||
void NV_API_CALL nv_dma_release_dma_buf
|
||||
(
|
||||
void *user_pages,
|
||||
nv_dma_buf_t *import_priv
|
||||
)
|
||||
{
|
||||
|
||||
@@ -50,16 +50,16 @@ NV_STATUS nv_get_syncpoint_aperture
|
||||
}
|
||||
#endif
|
||||
|
||||
#if NV_IS_EXPORT_SYMBOL_PRESENT_nvhost_syncpt_unit_interface_get_aperture
|
||||
#if NV_IS_EXPORT_SYMBOL_PRESENT_nvhost_syncpt_unit_interface_get_aperture && \
|
||||
NV_IS_EXPORT_SYMBOL_PRESENT_nvhost_syncpt_unit_interface_get_byte_offset
|
||||
nvhost_syncpt_unit_interface_get_aperture(
|
||||
host1x_pdev, &base, &size);
|
||||
#endif
|
||||
|
||||
*physAddr = base;
|
||||
|
||||
#if NV_IS_EXPORT_SYMBOL_PRESENT_nvhost_syncpt_unit_interface_get_byte_offset
|
||||
*limit = nvhost_syncpt_unit_interface_get_byte_offset(1);
|
||||
*offset = nvhost_syncpt_unit_interface_get_byte_offset(syncpointId);
|
||||
#else
|
||||
return NV_ERR_NOT_SUPPORTED;
|
||||
#endif
|
||||
|
||||
return NV_OK;
|
||||
|
||||
@@ -395,15 +395,23 @@ NV_STATUS NV_API_CALL nv_i2c_transfer(
|
||||
return NV_ERR_INVALID_ARGUMENT;
|
||||
}
|
||||
|
||||
client = nv_i2c_get_registered_client(nv, linuxI2CSwPort, address);
|
||||
if (client == NULL)
|
||||
{
|
||||
client = nv_i2c_register_client(nv, linuxI2CSwPort, address);
|
||||
for (count = 0; count < num_msgs; count++) {
|
||||
//
|
||||
// RM style slave address is 8-bit addressing, but Linux use 7-bit
|
||||
// addressing, so convert to 7-bit addressing format.
|
||||
//
|
||||
nv_msgs[count].addr = nv_msgs[count].addr >> 1;
|
||||
|
||||
client = nv_i2c_get_registered_client(nv, linuxI2CSwPort, nv_msgs[count].addr);
|
||||
if (client == NULL)
|
||||
{
|
||||
nv_printf(NV_DBG_ERRORS, "i2c client register failed for addr:0x%x\n",
|
||||
address);
|
||||
return NV_ERR_GENERIC;
|
||||
client = nv_i2c_register_client(nv, linuxI2CSwPort, nv_msgs[count].addr);
|
||||
if (client == NULL)
|
||||
{
|
||||
nv_printf(NV_DBG_ERRORS, "i2c client register failed for addr:0x%x\n",
|
||||
nv_msgs[count].addr);
|
||||
return NV_ERR_GENERIC;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -415,7 +423,7 @@ NV_STATUS NV_API_CALL nv_i2c_transfer(
|
||||
}
|
||||
|
||||
for (count = 0; count < num_msgs; count++) {
|
||||
msgs[count].addr = client->addr;
|
||||
msgs[count].addr = nv_msgs[count].addr;
|
||||
msgs[count].flags = nv_msgs[count].flags;
|
||||
msgs[count].len = nv_msgs[count].len;
|
||||
msgs[count].buf = nv_msgs[count].buf;
|
||||
@@ -467,6 +475,7 @@ NV_STATUS NV_API_CALL nv_i2c_bus_status(
|
||||
NvS32 *scl,
|
||||
NvS32 *sda)
|
||||
{
|
||||
#if NV_IS_EXPORT_SYMBOL_PRESENT_i2c_bus_status
|
||||
NvU32 linuxI2CSwPort;
|
||||
nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv);
|
||||
struct i2c_adapter *i2c_adapter;
|
||||
@@ -510,6 +519,9 @@ NV_STATUS NV_API_CALL nv_i2c_bus_status(
|
||||
i2c_put_adapter(i2c_adapter);
|
||||
|
||||
return NV_OK;
|
||||
#else
|
||||
return NV_ERR_NOT_SUPPORTED;
|
||||
#endif
|
||||
}
|
||||
|
||||
|
||||
|
||||
@@ -1521,7 +1521,9 @@ unsigned int NV_API_CALL nv_soc_fuse_register_read (unsigned int addr)
|
||||
{
|
||||
unsigned int data = 0;
|
||||
|
||||
#if NV_IS_EXPORT_SYMBOL_PRESENT_tegra_fuse_control_read
|
||||
tegra_fuse_control_read ((unsigned long)(addr), &data);
|
||||
#endif
|
||||
|
||||
return data;
|
||||
}
|
||||
|
||||
@@ -220,6 +220,9 @@ NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_dram_clk_to_mc_clk
|
||||
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_get_dram_num_channels
|
||||
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_dram_types
|
||||
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_pxm_to_node
|
||||
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_i2c_bus_status
|
||||
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_fuse_control_read
|
||||
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_tegra_get_platform
|
||||
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += file_operations
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += kuid_t
|
||||
|
||||
@@ -1954,7 +1954,7 @@ NV_STATUS NV_API_CALL os_get_tegra_platform
|
||||
NvU32 *mode
|
||||
)
|
||||
{
|
||||
#if defined(NV_TEGRA_GET_PLATFORM_PRESENT)
|
||||
#if defined(NV_TEGRA_GET_PLATFORM_PRESENT) && NV_IS_EXPORT_SYMBOL_PRESENT_tegra_get_platform
|
||||
NvU8 platform;
|
||||
|
||||
platform = tegra_get_platform();
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
|
||||
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
|
||||
|
||||
#define NV_VERSION_STRING "35.1.0"
|
||||
#define NV_VERSION_STRING "35.2.1"
|
||||
|
||||
#else
|
||||
|
||||
|
||||
@@ -1724,6 +1724,13 @@ parseDisplayId20Timing10Descriptor(
|
||||
|
||||
status = NvTiming_CalcCVT_RB3(width, height, rr, deltaHBlank, p7bytesDescriptor->additional_vblank_timing * 35, p6bytesDescriptor->options.early_vsync, pTiming);
|
||||
}
|
||||
else // 6 byte descriptor
|
||||
{
|
||||
if (p6bytesDescriptor->options.rr1000div1001_or_hblank == 1)
|
||||
deltaHBlank = 80;
|
||||
|
||||
status = NvTiming_CalcCVT_RB3(width, height, rr, deltaHBlank, 0, p6bytesDescriptor->options.early_vsync, pTiming);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -50,7 +50,7 @@ NvBool nvValidateModeForModeset(NVDpyEvoRec *pDpyEvo,
|
||||
const struct NvKmsSize *pViewPortSizeIn,
|
||||
const struct NvKmsRect *pViewPortOut,
|
||||
NVHwModeTimingsEvo *pTimingsEvo,
|
||||
NVT_VIDEO_INFOFRAME_CTRL *pInfoFrameCtrl);
|
||||
NVDispHeadInfoFrameStateEvoRec *pInfoFrameState);
|
||||
|
||||
const NVT_TIMING *nvFindEdidNVT_TIMING(
|
||||
const NVDpyEvoRec *pDpyEvo,
|
||||
|
||||
@@ -1533,7 +1533,8 @@ typedef struct _NVDispHeadAudioStateEvoRec {
|
||||
} NVDispHeadAudioStateEvoRec;
|
||||
|
||||
typedef struct _NVDispHeadInfoFrameStateEvoRec {
|
||||
NVT_VIDEO_INFOFRAME_CTRL ctrl;
|
||||
NVT_VIDEO_INFOFRAME_CTRL videoCtrl;
|
||||
NVT_VENDOR_SPECIFIC_INFOFRAME_CTRL vendorCtrl;
|
||||
NvBool hdTimings;
|
||||
} NVDispHeadInfoFrameStateEvoRec;
|
||||
|
||||
|
||||
@@ -1395,6 +1395,12 @@ static void LogEdid(NVDpyEvoPtr pDpyEvo, NVEvoInfoStringPtr pInfoString)
|
||||
{ NVT_TYPE_CUST_AUTO, "Customized Auto Timings" },
|
||||
{ NVT_TYPE_CUST_MANUAL, "Customized Manual Timings" },
|
||||
{ NVT_TYPE_CVT_RB_2,"Reduced Blanking Coordinated Video Timings, v2" },
|
||||
{ NVT_TYPE_DMT_RB_2, "Display Monitor Timings, V2" },
|
||||
{ NVT_TYPE_DISPLAYID_7, "DisplayID Type 7 Timings" },
|
||||
{ NVT_TYPE_DISPLAYID_8, "DisplayID Type 8 Timings" },
|
||||
{ NVT_TYPE_DISPLAYID_9, "DisplayID Type 9 Timings" },
|
||||
{ NVT_TYPE_DISPLAYID_10, "DisplayID Type 10 Timings" },
|
||||
{ NVT_TYPE_CVT_RB_3, "Reduced Blanking Coordinated Video Timings, v3" },
|
||||
};
|
||||
|
||||
/*
|
||||
@@ -1441,6 +1447,12 @@ static void LogEdid(NVDpyEvoPtr pDpyEvo, NVEvoInfoStringPtr pInfoString)
|
||||
case NVT_TYPE_CUST_AUTO:
|
||||
case NVT_TYPE_CUST_MANUAL:
|
||||
case NVT_TYPE_CVT_RB_2:
|
||||
case NVT_TYPE_DMT_RB_2:
|
||||
case NVT_TYPE_DISPLAYID_7:
|
||||
case NVT_TYPE_DISPLAYID_8:
|
||||
case NVT_TYPE_DISPLAYID_9:
|
||||
case NVT_TYPE_DISPLAYID_10:
|
||||
case NVT_TYPE_CVT_RB_3:
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
@@ -5314,14 +5314,33 @@ NvBool nvConstructHwModeTimingsEvo(const NVDpyEvoRec *pDpyEvo,
|
||||
// Start off picking best possible depth based on monitor caps
|
||||
// If the monitor doesn't have an EDID version 1.4 or higher, assume
|
||||
// it's 8.
|
||||
// For monitor with EDID version 1.4 or higher:
|
||||
// if bpc >= 10 configure pixel depth to 30bpp
|
||||
// if bpc is 8 or undefined configure pixel depth to 24bpp
|
||||
// if bpc is 6 use 18bpp as pixel depth
|
||||
if (pDpyEvo->parsedEdid.valid &&
|
||||
pDpyEvo->parsedEdid.info.input.isDigital &&
|
||||
pDpyEvo->parsedEdid.info.version >= NVT_EDID_VER_1_4) {
|
||||
if (pDpyEvo->parsedEdid.info.input.u.digital.bpc >= 10) {
|
||||
pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_30_444;
|
||||
} else if (pDpyEvo->parsedEdid.info.input.u.digital.bpc < 8) {
|
||||
pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_18_444;
|
||||
switch (pDpyEvo->parsedEdid.info.input.u.digital.bpc) {
|
||||
case 16:
|
||||
case 14:
|
||||
case 12:
|
||||
case 10:
|
||||
pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_30_444;
|
||||
break;
|
||||
case 8:
|
||||
case 0:
|
||||
pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_24_444;
|
||||
break;
|
||||
case 6:
|
||||
pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_18_444;
|
||||
break;
|
||||
default:
|
||||
nvAssert(!"Invalid EDID bit depth for DP");
|
||||
return FALSE;
|
||||
}
|
||||
} else {
|
||||
pTimings->pixelDepth = NVKMS_PIXEL_DEPTH_24_444;
|
||||
}
|
||||
} else {
|
||||
/* TMDS default */
|
||||
|
||||
@@ -66,8 +66,11 @@ static inline const NVT_EDID_CEA861_INFO *GetExt861(const NVParsedEdidEvoRec *pP
|
||||
static void CalculateVideoInfoFrameColorFormat(
|
||||
const NVAttributesSetEvoRec *pAttributesSet,
|
||||
const NvU32 hdTimings,
|
||||
NVT_VIDEO_INFOFRAME_CTRL *pCtrl)
|
||||
NVT_VIDEO_INFOFRAME_CTRL *pCtrl,
|
||||
NVT_EDID_INFO *pEdidInfo)
|
||||
{
|
||||
NvBool sinkSupportsRGBQuantizationOverride = FALSE;
|
||||
|
||||
// sets video infoframe colorspace (RGB/YUV).
|
||||
switch (pAttributesSet->colorSpace) {
|
||||
case NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB:
|
||||
@@ -123,6 +126,21 @@ static void CalculateVideoInfoFrameColorFormat(
|
||||
break;
|
||||
}
|
||||
|
||||
if (pEdidInfo != NULL) {
|
||||
sinkSupportsRGBQuantizationOverride = (pEdidInfo->ext861.valid.VCDB &&
|
||||
((pEdidInfo->ext861.video_capability & NVT_CEA861_VCDB_QS_MASK) >>
|
||||
NVT_CEA861_VCDB_QS_SHIFT) != 0);
|
||||
}
|
||||
|
||||
// For RGB pixel encoding, explicitly set quantization bits in AVI Infoframe only
|
||||
// if sink supports selectable RGB quantization range in VCDB of EDID. Or else
|
||||
// set default range for the transmitted video format.
|
||||
// (HDMI 2.0 spec section 7.3.1)
|
||||
if ((pAttributesSet->colorSpace == NV_KMS_DPY_ATTRIBUTE_CURRENT_COLOR_SPACE_RGB) &&
|
||||
!sinkSupportsRGBQuantizationOverride) {
|
||||
pCtrl->rgb_quantization_range = NVT_VIDEO_INFOFRAME_BYTE3_Q1Q0_DEFAULT;
|
||||
}
|
||||
|
||||
// Only limited color range is allowed with YUV444 or YUV422 color spaces
|
||||
nvAssert(!(((pCtrl->color_space == NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_YCbCr422) ||
|
||||
(pCtrl->color_space == NVT_VIDEO_INFOFRAME_BYTE1_Y1Y0_YCbCr444)) &&
|
||||
@@ -286,34 +304,6 @@ static void HdmiSendEnable(NVDpyEvoPtr pDpyEvo, NvBool hdmiEnable)
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* Disable sending the vendor specific infoframe on this display.
|
||||
*/
|
||||
static void DisableVendorSpecificInfoFrame(
|
||||
const NVDispEvoRec *pDispEvo,
|
||||
const NvU32 head)
|
||||
{
|
||||
const NVDispHeadStateEvoRec *pHeadState = &pDispEvo->headState[head];
|
||||
NV0073_CTRL_SPECIFIC_SET_OD_PACKET_CTRL_PARAMS params = { 0 };
|
||||
NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo;
|
||||
NvU32 ret;
|
||||
|
||||
params.subDeviceInstance = pDispEvo->displayOwner;
|
||||
params.displayId = pHeadState->activeRmId;
|
||||
params.type = pktType_VendorSpecInfoFrame;
|
||||
params.transmitControl = DRF_DEF(0073_CTRL_SPECIFIC, _SET_OD_PACKET_CTRL_TRANSMIT_CONTROL, _ENABLE, _NO);
|
||||
|
||||
ret = nvRmApiControl(nvEvoGlobal.clientHandle,
|
||||
pDevEvo->displayCommonHandle,
|
||||
NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET_CTRL,
|
||||
¶ms,
|
||||
sizeof(params));
|
||||
|
||||
if (ret != NVOS_STATUS_SUCCESS) {
|
||||
nvAssert(!"NV0073_CTRL_CMD_SPECIFIC_SET_OD_PACKET_CTRL failed");
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* SendInfoFrame() - Send infoframe to the hardware through the hdmipkt
|
||||
* library.
|
||||
@@ -438,12 +428,12 @@ static void SendVideoInfoFrame(const NVDispEvoRec *pDispEvo,
|
||||
NVT_EDID_INFO *pEdidInfo)
|
||||
{
|
||||
NvBool hdTimings = pInfoFrameState->hdTimings;
|
||||
NVT_VIDEO_INFOFRAME_CTRL videoCtrl = pInfoFrameState->ctrl;
|
||||
NVT_VIDEO_INFOFRAME_CTRL videoCtrl = pInfoFrameState->videoCtrl;
|
||||
NVT_VIDEO_INFOFRAME VideoInfoFrame;
|
||||
NVT_STATUS status;
|
||||
|
||||
|
||||
CalculateVideoInfoFrameColorFormat(pAttributesSet, hdTimings, &videoCtrl);
|
||||
CalculateVideoInfoFrameColorFormat(pAttributesSet, hdTimings, &videoCtrl, pEdidInfo);
|
||||
|
||||
status = NvTiming_ConstructVideoInfoframe(pEdidInfo,
|
||||
&videoCtrl,
|
||||
@@ -462,41 +452,20 @@ static void SendVideoInfoFrame(const NVDispEvoRec *pDispEvo,
|
||||
}
|
||||
|
||||
/*
|
||||
* SendHDMI3DVendorSpecificInfoFrame() - Construct vendor specific infoframe
|
||||
* using provided EDID and call SendInfoFrame() to send it to RM. Currently
|
||||
* hardcoded to send the infoframe necessary for HDMI 3D.
|
||||
* SendHDMIVendorSpecificInfoFrame() - Construct vendor specific infoframe
|
||||
* using provided EDID and call SendInfoFrame() to send it to RM.
|
||||
*/
|
||||
|
||||
static void
|
||||
SendHDMI3DVendorSpecificInfoFrame(const NVDispEvoRec *pDispEvo,
|
||||
const NvU32 head, NVT_EDID_INFO *pEdidInfo)
|
||||
SendHDMIVendorSpecificInfoFrame(const NVDispEvoRec *pDispEvo,
|
||||
const NvU32 head,
|
||||
const NVDispHeadInfoFrameStateEvoRec *pInfoFrameState,
|
||||
NVT_EDID_INFO *pEdidInfo)
|
||||
{
|
||||
const NVDispHeadStateEvoRec *pHeadState =
|
||||
&pDispEvo->headState[head];
|
||||
NVT_VENDOR_SPECIFIC_INFOFRAME_CTRL vendorCtrl = {
|
||||
.Enable = 1,
|
||||
.HDMIFormat = NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_3D,
|
||||
.HDMI_VIC = NVT_HDMI_VS_BYTE5_HDMI_VIC_NA,
|
||||
.ThreeDStruc = NVT_HDMI_VS_BYTE5_HDMI_3DS_FRAMEPACK,
|
||||
.ThreeDDetail = NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_NA,
|
||||
.MetadataPresent = 0,
|
||||
.MetadataType = NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_NA,
|
||||
};
|
||||
NVT_VENDOR_SPECIFIC_INFOFRAME_CTRL vendorCtrl = pInfoFrameState->vendorCtrl;
|
||||
NVT_VENDOR_SPECIFIC_INFOFRAME vendorInfoFrame;
|
||||
NVT_STATUS status;
|
||||
|
||||
if (!pEdidInfo->HDMI3DSupported) {
|
||||
// Only send the HDMI 3D infoframe if the display supports HDMI 3D
|
||||
return;
|
||||
}
|
||||
|
||||
// Send the infoframe with HDMI 3D configured if we're setting an HDMI 3D
|
||||
// mode.
|
||||
if (!pHeadState->timings.hdmi3D) {
|
||||
DisableVendorSpecificInfoFrame(pDispEvo, head);
|
||||
return;
|
||||
}
|
||||
|
||||
status = NvTiming_ConstructVendorSpecificInfoframe(pEdidInfo,
|
||||
&vendorCtrl,
|
||||
&vendorInfoFrame);
|
||||
@@ -539,9 +508,10 @@ void nvUpdateHdmiInfoFrames(const NVDispEvoRec *pDispEvo,
|
||||
pInfoFrameState,
|
||||
&pDpyEvo->parsedEdid.info);
|
||||
|
||||
SendHDMI3DVendorSpecificInfoFrame(pDispEvo,
|
||||
head,
|
||||
&pDpyEvo->parsedEdid.info);
|
||||
SendHDMIVendorSpecificInfoFrame(pDispEvo,
|
||||
head,
|
||||
pInfoFrameState,
|
||||
&pDpyEvo->parsedEdid.info);
|
||||
}
|
||||
|
||||
static void SetDpAudioMute(const NVDispEvoRec *pDispEvo,
|
||||
|
||||
@@ -67,7 +67,7 @@ static NvBool ConstructModeTimingsMetaData(
|
||||
const struct NvKmsModeValidationParams *pParams,
|
||||
struct NvKmsMode *pKmsMode,
|
||||
EvoValidateModeFlags *pFlags,
|
||||
NVT_VIDEO_INFOFRAME_CTRL *pInfoFrameCtrl);
|
||||
NVDispHeadInfoFrameStateEvoRec *pInfoFrameState);
|
||||
|
||||
static NvBool ValidateMode(NVDpyEvoPtr pDpyEvo,
|
||||
const struct NvKmsMode *pKmsMode,
|
||||
@@ -139,7 +139,7 @@ nvValidateModeEvo(NVDpyEvoPtr pDpyEvo,
|
||||
.timings = pRequest->mode.timings,
|
||||
};
|
||||
EvoValidateModeFlags evoFlags;
|
||||
NVT_VIDEO_INFOFRAME_CTRL dummyInfoFrameCtrl;
|
||||
NVDispHeadInfoFrameStateEvoRec dummyInfoFrameState;
|
||||
|
||||
nvkms_memset(pReply, 0, sizeof(*pReply));
|
||||
|
||||
@@ -147,7 +147,7 @@ nvValidateModeEvo(NVDpyEvoPtr pDpyEvo,
|
||||
&pRequest->modeValidation,
|
||||
&kmsMode,
|
||||
&evoFlags,
|
||||
&dummyInfoFrameCtrl)) {
|
||||
&dummyInfoFrameState)) {
|
||||
pReply->valid = FALSE;
|
||||
return;
|
||||
}
|
||||
@@ -1801,16 +1801,25 @@ static NvBool ConstructModeTimingsMetaData(
|
||||
const struct NvKmsModeValidationParams *pParams,
|
||||
struct NvKmsMode *pKmsMode,
|
||||
EvoValidateModeFlags *pFlags,
|
||||
NVT_VIDEO_INFOFRAME_CTRL *pInfoFrameCtrl)
|
||||
NVDispHeadInfoFrameStateEvoRec *pInfoFrameState)
|
||||
{
|
||||
const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo;
|
||||
EvoValidateModeFlags flags = { 0 };
|
||||
NVT_VIDEO_INFOFRAME_CTRL infoFrameCtrl;
|
||||
NVT_VIDEO_INFOFRAME_CTRL *pVideoInfoFrameCtrl = NULL;
|
||||
NVT_VENDOR_SPECIFIC_INFOFRAME_CTRL *pVendorInfoFrameCtrl = NULL;
|
||||
NvModeTimings modeTimings = pKmsMode->timings;
|
||||
const NVT_TIMING *pTiming;
|
||||
|
||||
nvkms_memset(&infoFrameCtrl, NVT_INFOFRAME_CTRL_DONTCARE,
|
||||
sizeof(infoFrameCtrl));
|
||||
if (pInfoFrameState != NULL) {
|
||||
pVideoInfoFrameCtrl = &pInfoFrameState->videoCtrl;
|
||||
pVendorInfoFrameCtrl = &pInfoFrameState->vendorCtrl;
|
||||
|
||||
nvkms_memset(pVideoInfoFrameCtrl, NVT_INFOFRAME_CTRL_DONTCARE,
|
||||
sizeof(*pVideoInfoFrameCtrl));
|
||||
|
||||
nvkms_memset(pVendorInfoFrameCtrl, NVT_INFOFRAME_CTRL_DONTCARE,
|
||||
sizeof(*pVendorInfoFrameCtrl));
|
||||
}
|
||||
|
||||
flags.source = NvKmsModeSourceUnknown;
|
||||
|
||||
@@ -1881,7 +1890,22 @@ static NvBool ConstructModeTimingsMetaData(
|
||||
* pTimingsEvo after ValidateMode has written to it.
|
||||
*/
|
||||
if (nvDpyIsHdmiEvo(pDpyEvo)) {
|
||||
NvTiming_ConstructVideoInfoframeCtrl(&timing, &infoFrameCtrl);
|
||||
NvTiming_ConstructVideoInfoframeCtrl(&timing, pVideoInfoFrameCtrl);
|
||||
|
||||
if (pVendorInfoFrameCtrl != NULL) {
|
||||
// Currently hardcoded to send infoframe necessary for HDMI 1.4a 4kx2k extended modes.
|
||||
if (NVT_GET_TIMING_STATUS_TYPE(timing.etc.status) == NVT_TYPE_HDMI_EXT) {
|
||||
pVendorInfoFrameCtrl->Enable = 1;
|
||||
pVendorInfoFrameCtrl->HDMIFormat = NVT_HDMI_VS_BYTE4_HDMI_VID_FMT_EXT;
|
||||
pVendorInfoFrameCtrl->HDMI_VIC = NVT_GET_TIMING_STATUS_SEQ(timing.etc.status);
|
||||
pVendorInfoFrameCtrl->ThreeDStruc = NVT_HDMI_VS_BYTE5_HDMI_3DS_NA;
|
||||
pVendorInfoFrameCtrl->ThreeDDetail = NVT_HDMI_VS_BYTE_OPT1_HDMI_3DEX_NA;
|
||||
pVendorInfoFrameCtrl->MetadataPresent = 0;
|
||||
pVendorInfoFrameCtrl->MetadataType = NVT_HDMI_VS_BYTE_OPT2_HDMI_METADATA_TYPE_NA;
|
||||
} else {
|
||||
pVendorInfoFrameCtrl->Enable = 0;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
goto done;
|
||||
@@ -1901,7 +1925,6 @@ static NvBool ConstructModeTimingsMetaData(
|
||||
|
||||
done:
|
||||
*pFlags = flags;
|
||||
*pInfoFrameCtrl = infoFrameCtrl;
|
||||
pKmsMode->timings = modeTimings;
|
||||
|
||||
return TRUE;
|
||||
@@ -1924,11 +1947,10 @@ NvBool nvValidateModeForModeset(NVDpyEvoRec *pDpyEvo,
|
||||
const struct NvKmsSize *pViewPortSizeIn,
|
||||
const struct NvKmsRect *pViewPortOut,
|
||||
NVHwModeTimingsEvo *pTimingsEvo,
|
||||
NVT_VIDEO_INFOFRAME_CTRL *pInfoFrameCtrl)
|
||||
NVDispHeadInfoFrameStateEvoRec *pInfoFrameState)
|
||||
{
|
||||
EvoValidateModeFlags flags;
|
||||
struct NvKmsMode kmsMode = *pKmsMode;
|
||||
NVT_VIDEO_INFOFRAME_CTRL infoFrameCtrl;
|
||||
struct NvKmsModeValidationValidSyncs dummyValidSyncs;
|
||||
|
||||
nvkms_memset(pTimingsEvo, 0, sizeof(*pTimingsEvo));
|
||||
@@ -1937,7 +1959,7 @@ NvBool nvValidateModeForModeset(NVDpyEvoRec *pDpyEvo,
|
||||
pParams,
|
||||
&kmsMode,
|
||||
&flags,
|
||||
&infoFrameCtrl)) {
|
||||
pInfoFrameState)) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
@@ -1960,7 +1982,5 @@ NvBool nvValidateModeForModeset(NVDpyEvoRec *pDpyEvo,
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
*pInfoFrameCtrl = infoFrameCtrl;
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
@@ -175,7 +175,7 @@ static NvBool
|
||||
GetHwModeTimings(const NVDispEvoRec *pDispEvo,
|
||||
const struct NvKmsSetModeOneHeadRequest *pRequestHead,
|
||||
NVHwModeTimingsEvo *pTimings,
|
||||
NVT_VIDEO_INFOFRAME_CTRL *pInfoFrameCtrl)
|
||||
NVDispHeadInfoFrameStateEvoRec *pInfoFrameState)
|
||||
{
|
||||
NVDpyEvoPtr pDpyEvo;
|
||||
|
||||
@@ -196,7 +196,7 @@ GetHwModeTimings(const NVDispEvoRec *pDispEvo,
|
||||
pRequestHead->viewPortOutSpecified ?
|
||||
&pRequestHead->viewPortOut : NULL,
|
||||
pTimings,
|
||||
pInfoFrameCtrl);
|
||||
pInfoFrameState);
|
||||
}
|
||||
|
||||
static NvBool ApplySyncptRegistration(
|
||||
@@ -503,8 +503,8 @@ AssignProposedModeSetHwState(NVDevEvoRec *pDevEvo,
|
||||
* head so that if additional heads fail, we can report
|
||||
* more complete failure information to the client.
|
||||
*/
|
||||
if (!GetHwModeTimings(pDispEvo, pRequestHead, &pProposedHead->timings,
|
||||
&pProposedHead->infoFrame.ctrl)) {
|
||||
if (!GetHwModeTimings(pDispEvo, pRequestHead,
|
||||
&pProposedHead->timings, &pProposedHead->infoFrame)) {
|
||||
pReply->disp[sd].head[head].status =
|
||||
NVKMS_SET_MODE_ONE_HEAD_STATUS_INVALID_MODE;
|
||||
ret = FALSE;
|
||||
|
||||
@@ -854,9 +854,9 @@ struct drm_gem_object;
|
||||
|
||||
NV_STATUS NV_API_CALL nv_dma_import_sgt (nv_dma_device_t *, struct sg_table *, struct drm_gem_object *);
|
||||
void NV_API_CALL nv_dma_release_sgt(struct sg_table *, struct drm_gem_object *);
|
||||
NV_STATUS NV_API_CALL nv_dma_import_dma_buf (nv_dma_device_t *, struct dma_buf *, NvU32 *, void **, struct sg_table **, nv_dma_buf_t **);
|
||||
NV_STATUS NV_API_CALL nv_dma_import_from_fd (nv_dma_device_t *, NvS32, NvU32 *, void **, struct sg_table **, nv_dma_buf_t **);
|
||||
void NV_API_CALL nv_dma_release_dma_buf (void *, nv_dma_buf_t *);
|
||||
NV_STATUS NV_API_CALL nv_dma_import_dma_buf (nv_dma_device_t *, struct dma_buf *, NvU32 *, struct sg_table **, nv_dma_buf_t **);
|
||||
NV_STATUS NV_API_CALL nv_dma_import_from_fd (nv_dma_device_t *, NvS32, NvU32 *, struct sg_table **, nv_dma_buf_t **);
|
||||
void NV_API_CALL nv_dma_release_dma_buf (nv_dma_buf_t *);
|
||||
|
||||
void NV_API_CALL nv_schedule_uvm_isr (nv_state_t *);
|
||||
|
||||
|
||||
@@ -688,64 +688,27 @@ _createMemdescFromDmaBufSgtHelper
|
||||
return rmStatus;
|
||||
}
|
||||
|
||||
/*
|
||||
* XXX: Due to bug 200720644, direct SGT-based DMA-BUF importing is disabled for
|
||||
* GLOBAL_FEATURE_TEGRA_DISPLAY.
|
||||
*
|
||||
* Accessing the underlying pages of an SGT is illegal, and will be broken on
|
||||
* future kernels:
|
||||
* https://cgit.freedesktop.org/drm/drm-misc/commit/?id=84335675f2223cbd25d0de7d38ecc7d40b95bd4a
|
||||
*
|
||||
* This code should be deleted in favor of the version that uses
|
||||
* _createMemdescFromDmaBufSgtHelper() once the underlying cause of bug
|
||||
* 200720644 is discovered and resolved. The code handling 'user_pages' in
|
||||
* nv_dma_import_dma_buf() and nv_dma_release_dma_buf() should also be removed.
|
||||
*/
|
||||
static NV_STATUS
|
||||
_createMemdescFromDmaBuf
|
||||
(
|
||||
OBJGPU *pGpu,
|
||||
NvU32 flags,
|
||||
nv_dma_buf_t *pImportPriv,
|
||||
void *pUserPages,
|
||||
struct sg_table *pImportSgt,
|
||||
NvU32 size,
|
||||
MEMORY_DESCRIPTOR **ppMemDesc,
|
||||
void **ppPrivate
|
||||
)
|
||||
{
|
||||
NV_STATUS rmStatus = NV_OK;
|
||||
NvU32 cacheType = NV_MEMORY_UNCACHED;
|
||||
|
||||
if (FLD_TEST_DRF(OS02, _FLAGS, _COHERENCY, _WRITE_COMBINE, flags))
|
||||
{
|
||||
cacheType = NV_MEMORY_WRITECOMBINED;
|
||||
}
|
||||
else if (!FLD_TEST_DRF(OS02, _FLAGS, _COHERENCY, _UNCACHED, flags))
|
||||
{
|
||||
cacheType = NV_MEMORY_CACHED;
|
||||
}
|
||||
|
||||
*ppPrivate = pUserPages;
|
||||
|
||||
rmStatus = osCreateMemdescFromPages(pGpu, size, flags, cacheType, ppMemDesc,
|
||||
pImportPriv, ppPrivate);
|
||||
NV_STATUS rmStatus =
|
||||
_createMemdescFromDmaBufSgtHelper(pGpu, flags, pImportPriv, pImportSgt,
|
||||
size, ppMemDesc, ppPrivate,
|
||||
osDestroyOsDescriptorFromDmaBuf);
|
||||
if (rmStatus != NV_OK)
|
||||
{
|
||||
NV_PRINTF(LEVEL_ERROR,
|
||||
"%s(): Error (%d) while creating memdesc from pages!\n",
|
||||
__FUNCTION__, rmStatus);
|
||||
goto create_memdesc_fail;
|
||||
nv_dma_release_dma_buf(pImportPriv);
|
||||
}
|
||||
|
||||
memdescSetMemData(*ppMemDesc, *ppPrivate,
|
||||
osDestroyOsDescriptorFromDmaBuf);
|
||||
|
||||
return NV_OK;
|
||||
|
||||
create_memdesc_fail:
|
||||
nv_dma_release_dma_buf(pUserPages, pImportPriv);
|
||||
|
||||
return rmStatus;
|
||||
}
|
||||
|
||||
@@ -774,6 +737,23 @@ _createMemdescFromSgt
|
||||
return rmStatus;
|
||||
}
|
||||
|
||||
static nv_dma_device_t *GetDmaDeviceForImport
|
||||
(
|
||||
nv_state_t *nv,
|
||||
NvU32 flags
|
||||
)
|
||||
{
|
||||
if (FLD_TEST_DRF(OS02, _FLAGS, _ALLOC_NISO_DISPLAY, _YES, flags) &&
|
||||
(nv->niso_dma_dev != NULL))
|
||||
{
|
||||
return nv->niso_dma_dev;
|
||||
}
|
||||
else
|
||||
{
|
||||
return nv->dma_dev;
|
||||
}
|
||||
}
|
||||
|
||||
static NV_STATUS
|
||||
osCreateOsDescriptorFromFileHandle
|
||||
(
|
||||
@@ -788,8 +768,8 @@ osCreateOsDescriptorFromFileHandle
|
||||
{
|
||||
NV_STATUS rmStatus = NV_OK;
|
||||
nv_state_t *nv = NV_GET_NV_STATE(pGpu);
|
||||
nv_dma_device_t *dma_dev = NULL;
|
||||
NvU32 size = 0;
|
||||
void *pUserPages = NULL;
|
||||
nv_dma_buf_t *pImportPriv = NULL;
|
||||
struct sg_table *pImportSgt = NULL;
|
||||
NvS32 fd;
|
||||
@@ -803,8 +783,9 @@ osCreateOsDescriptorFromFileHandle
|
||||
return NV_ERR_INVALID_ARGUMENT;
|
||||
}
|
||||
|
||||
rmStatus = nv_dma_import_from_fd(nv->dma_dev, fd, &size,
|
||||
&pUserPages, &pImportSgt, &pImportPriv);
|
||||
dma_dev = GetDmaDeviceForImport(nv, flags);
|
||||
rmStatus = nv_dma_import_from_fd(dma_dev, fd, &size,
|
||||
&pImportSgt, &pImportPriv);
|
||||
if (rmStatus != NV_OK)
|
||||
{
|
||||
NV_PRINTF(LEVEL_ERROR,
|
||||
@@ -814,7 +795,7 @@ osCreateOsDescriptorFromFileHandle
|
||||
}
|
||||
|
||||
return _createMemdescFromDmaBuf(pGpu, flags, pImportPriv,
|
||||
pUserPages, pImportSgt,
|
||||
pImportSgt,
|
||||
size, ppMemDesc, ppPrivate);
|
||||
}
|
||||
|
||||
@@ -865,14 +846,15 @@ osCreateOsDescriptorFromDmaBufPtr
|
||||
{
|
||||
NV_STATUS rmStatus = NV_OK;
|
||||
nv_state_t *nv = NV_GET_NV_STATE(pGpu);
|
||||
nv_dma_device_t *dma_dev = NULL;
|
||||
NvU32 size = 0;
|
||||
void *pUserPages = NULL;
|
||||
nv_dma_buf_t *pImportPriv = NULL;
|
||||
struct sg_table *pImportSgt = NULL;
|
||||
void *dmaBuf = (void*)((NvUPtr)pDescriptor);
|
||||
|
||||
rmStatus = nv_dma_import_dma_buf(nv->dma_dev, dmaBuf, &size,
|
||||
&pUserPages, &pImportSgt, &pImportPriv);
|
||||
dma_dev = GetDmaDeviceForImport(nv, flags);
|
||||
rmStatus = nv_dma_import_dma_buf(dma_dev, dmaBuf, &size,
|
||||
&pImportSgt, &pImportPriv);
|
||||
if (rmStatus != NV_OK)
|
||||
{
|
||||
NV_PRINTF(LEVEL_ERROR,
|
||||
@@ -882,7 +864,7 @@ osCreateOsDescriptorFromDmaBufPtr
|
||||
}
|
||||
|
||||
return _createMemdescFromDmaBuf(pGpu, flags, pImportPriv,
|
||||
pUserPages, pImportSgt,
|
||||
pImportSgt,
|
||||
size, ppMemDesc, ppPrivate);
|
||||
}
|
||||
|
||||
@@ -963,19 +945,6 @@ osDestroyOsDescriptorPageArray
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* XXX: Due to bug 200720644, direct SGT-based DMA-BUF importing is disabled for
|
||||
* GLOBAL_FEATURE_TEGRA_DISPLAY.
|
||||
*
|
||||
* Accessing the underlying pages of an SGT is illegal, and will be broken on
|
||||
* future kernels:
|
||||
* https://cgit.freedesktop.org/drm/drm-misc/commit/?id=84335675f2223cbd25d0de7d38ecc7d40b95bd4a
|
||||
*
|
||||
* This code should be deleted in favor of the version that uses
|
||||
* _createMemdescFromDmaBufSgtHelper() once the underlying cause of bug
|
||||
* 200720644 is discovered and resolved. The code handling 'user_pages' in
|
||||
* nv_dma_import_dma_buf() and nv_dma_release_dma_buf() should also be removed.
|
||||
*/
|
||||
static void
|
||||
osDestroyOsDescriptorFromDmaBuf
|
||||
(
|
||||
@@ -983,13 +952,16 @@ osDestroyOsDescriptorFromDmaBuf
|
||||
)
|
||||
{
|
||||
OBJGPU *pGpu = pMemDesc->pGpu;
|
||||
NvU64 osPageCount = NV_RM_PAGES_TO_OS_PAGES(pMemDesc->PageCount);
|
||||
void *pPrivate;
|
||||
void *pPrivate = memdescGetMemData(pMemDesc);
|
||||
|
||||
struct sg_table *pImportSgt;
|
||||
void *pImportPriv;
|
||||
|
||||
pPrivate = memdescGetMemData(pMemDesc);
|
||||
|
||||
NV_ASSERT(pPrivate != NULL);
|
||||
/*
|
||||
* Unmap IOMMU now or we will get a kernel crash when it is unmapped after
|
||||
* pImportSgt is freed.
|
||||
*/
|
||||
memdescUnmapIommu(pMemDesc, pGpu->busInfo.iovaspaceId);
|
||||
|
||||
if ((NV_RM_PAGE_SIZE < os_page_size) &&
|
||||
!memdescGetContiguity(pMemDesc, AT_CPU))
|
||||
@@ -998,10 +970,16 @@ osDestroyOsDescriptorFromDmaBuf
|
||||
pMemDesc->PageCount);
|
||||
}
|
||||
|
||||
nv_unregister_user_pages(NV_GET_NV_STATE(pGpu), osPageCount, &pImportPriv,
|
||||
&pPrivate);
|
||||
nv_unregister_sgt(NV_GET_NV_STATE(pGpu), &pImportSgt,
|
||||
&pImportPriv, pPrivate);
|
||||
|
||||
nv_dma_release_dma_buf(pPrivate, pImportPriv);
|
||||
/*
|
||||
* pImportSgt doesn't need to be passed to nv_dma_release_dma_buf() because
|
||||
* the DMA-BUF associated with pImportPriv already has a reference to the
|
||||
* SGT.
|
||||
*/
|
||||
|
||||
nv_dma_release_dma_buf(pImportPriv);
|
||||
}
|
||||
|
||||
static void
|
||||
|
||||
@@ -47,6 +47,7 @@ extern "C" {
|
||||
#include "class/cl0080.h"
|
||||
#include "class/cl2080.h"
|
||||
#include "class/cl0073.h"
|
||||
#include "class/cl0005.h"
|
||||
#include "class/clc372sw.h"
|
||||
|
||||
typedef struct
|
||||
@@ -99,6 +100,24 @@ typedef struct
|
||||
NvBool valid;
|
||||
} DISPLAY_SW;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvHandle hClient;
|
||||
NvHandle hParent;
|
||||
NvHandle hObject;
|
||||
NvU32 hClass;
|
||||
NV0005_ALLOC_PARAMETERS displaySWEventAllocParams;
|
||||
NvBool valid;
|
||||
} DISPLAY_SW_EVENT;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvHandle hClient;
|
||||
NvHandle hObject;
|
||||
NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS setEventParams;
|
||||
NvBool valid;
|
||||
} DISPLAY_HPD_CTRL;
|
||||
|
||||
/*!
|
||||
* Max no of RM clients
|
||||
*/
|
||||
|
||||
@@ -32,6 +32,7 @@ typedef struct
|
||||
OS_THREAD_HANDLE threadId; //<! ID of thread owning the lock, ~0 if none
|
||||
NvU64 timestamp; //<! Timestamp of last lock acquire
|
||||
LOCK_TRACE_INFO traceInfo; //<! Lock acquire/release trace info
|
||||
NvBool bValid; //<! If ready to acquire/release the lock
|
||||
} GPULOCK;
|
||||
|
||||
static GPULOCK rmGpuLock;
|
||||
@@ -51,6 +52,7 @@ NV_STATUS rmGpuLockInfoInit(void)
|
||||
OS_THREAD_HANDLE threadId;
|
||||
osGetCurrentThread(&threadId);
|
||||
osGetCurrentTick(×tamp);
|
||||
rmGpuLock.bValid = NV_FALSE;
|
||||
|
||||
INSERT_LOCK_TRACE(&rmGpuLock.traceInfo, NV_RETURN_ADDRESS(),
|
||||
lockTraceAlloc, 0, 0, threadId,
|
||||
@@ -75,12 +77,16 @@ NV_STATUS rmGpuLockAlloc(NvU32 gpuInst)
|
||||
{
|
||||
NV_ASSERT_OR_RETURN(gpuInst == 0, NV_ERR_INVALID_ARGUMENT);
|
||||
NV_ASSERT_OR_RETURN(rmGpuLock.pLock != NULL, NV_ERR_INVALID_STATE);
|
||||
|
||||
rmGpuLock.bValid = NV_TRUE;
|
||||
|
||||
return NV_OK;
|
||||
}
|
||||
|
||||
void rmGpuLockFree(NvU32 gpuInst)
|
||||
{
|
||||
NV_ASSERT_OR_RETURN_VOID(gpuInst == 0);
|
||||
rmGpuLock.bValid = NV_FALSE;
|
||||
}
|
||||
|
||||
static NV_STATUS _rmGpuLockAcquire(NvU32 flags, void *ra)
|
||||
@@ -88,6 +94,14 @@ static NV_STATUS _rmGpuLockAcquire(NvU32 flags, void *ra)
|
||||
NvBool bCondAcquire = !!(flags & GPUS_LOCK_FLAGS_COND_ACQUIRE);
|
||||
NvBool bHighIrql = (portSyncExSafeToSleep() == NV_FALSE);
|
||||
|
||||
//
|
||||
// We may get a bValid as NV_FALSE before GPU is attached.
|
||||
//
|
||||
if (rmGpuLock.bValid == NV_FALSE)
|
||||
{
|
||||
return NV_OK;
|
||||
}
|
||||
|
||||
NV_ASSERT_OR_RETURN(rmGpuLock.pLock != NULL, NV_ERR_INVALID_STATE);
|
||||
NV_ASSERT_OR_RETURN(!rmGpuLockIsOwner(), NV_ERR_CYCLE_DETECTED);
|
||||
if (bCondAcquire || bHighIrql)
|
||||
@@ -102,6 +116,7 @@ static NV_STATUS _rmGpuLockAcquire(NvU32 flags, void *ra)
|
||||
portSyncSemaphoreAcquire(rmGpuLock.pLock);
|
||||
portAtomicDecrementU32(&rmGpuLock.waiting);
|
||||
}
|
||||
|
||||
osGetCurrentThread(&rmGpuLock.threadId);
|
||||
osGetCurrentTick(&rmGpuLock.timestamp);
|
||||
|
||||
@@ -112,6 +127,7 @@ static NV_STATUS _rmGpuLockAcquire(NvU32 flags, void *ra)
|
||||
INSERT_LOCK_TRACE(&rmGpuLock.traceInfo, ra,
|
||||
lockTraceAcquire, 0, 0, rmGpuLock.threadId,
|
||||
bHighIrql, 0, rmGpuLock.timestamp);
|
||||
|
||||
return NV_OK;
|
||||
}
|
||||
|
||||
@@ -120,6 +136,14 @@ static NV_STATUS _rmGpuLockRelease(void *ra)
|
||||
OS_THREAD_HANDLE threadId;
|
||||
NvU64 timestamp;
|
||||
|
||||
//
|
||||
// We may get a bValid as NV_FALSE before GPU is attached.
|
||||
//
|
||||
if (rmGpuLock.bValid == NV_FALSE)
|
||||
{
|
||||
return NV_OK;
|
||||
}
|
||||
|
||||
osGetCurrentThread(&threadId);
|
||||
osGetCurrentTick(×tamp);
|
||||
|
||||
|
||||
@@ -28,6 +28,10 @@ DEVICE devices[MAX_RM_CLIENTS];
|
||||
SUBDEVICE subdevices[MAX_RM_CLIENTS];
|
||||
DISPLAY_COMMON display;
|
||||
DISPLAY_SW displaySW;
|
||||
DISPLAY_SW_EVENT displaySWEventHotplug;
|
||||
DISPLAY_SW_EVENT displaySWEventDPIRQ;
|
||||
DISPLAY_HPD_CTRL displayCtrlHotplug;
|
||||
DISPLAY_HPD_CTRL displayCtrlDPIRQ;
|
||||
|
||||
NV_STATUS
|
||||
dceclientConstructEngine_IMPL
|
||||
@@ -139,6 +143,50 @@ dceclientStateLoad_IMPL
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
if (displaySWEventHotplug.valid)
|
||||
{
|
||||
nvStatus = rpcRmApiAlloc_dce(pRmApi, displaySWEventHotplug.hClient, displaySWEventHotplug.hParent,
|
||||
displaySWEventHotplug.hObject, displaySWEventHotplug.hClass, &displaySWEventHotplug.displaySWEventAllocParams);
|
||||
if (nvStatus != NV_OK)
|
||||
{
|
||||
NV_PRINTF(LEVEL_ERROR, "Cannot alloc displaySWEventHotplug object during resume\n");
|
||||
nvStatus = NV_ERR_GENERIC;
|
||||
goto out;
|
||||
}
|
||||
else if(displayCtrlHotplug.valid)
|
||||
{
|
||||
nvStatus = rpcRmApiControl_dce(pRmApi, displayCtrlHotplug.hClient, displayCtrlHotplug.hObject, NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION,
|
||||
&displayCtrlHotplug.setEventParams,sizeof(displayCtrlHotplug.setEventParams));
|
||||
if (nvStatus != NV_OK)
|
||||
{
|
||||
NV_PRINTF(LEVEL_ERROR, "rpcRmApiControl_dce for displayCtrlHotplug failed during resume\n");
|
||||
nvStatus = NV_ERR_GENERIC;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
}
|
||||
if (displaySWEventDPIRQ.valid)
|
||||
{
|
||||
nvStatus = rpcRmApiAlloc_dce(pRmApi, displaySWEventDPIRQ.hClient, displaySWEventDPIRQ.hParent,
|
||||
displaySWEventDPIRQ.hObject, displaySWEventDPIRQ.hClass, &displaySWEventDPIRQ.displaySWEventAllocParams);
|
||||
if (nvStatus != NV_OK)
|
||||
{
|
||||
NV_PRINTF(LEVEL_ERROR, "Cannot alloc displaySWEventDPIRQ object during resume\n");
|
||||
nvStatus = NV_ERR_GENERIC;
|
||||
goto out;
|
||||
}
|
||||
else if(displayCtrlDPIRQ.valid)
|
||||
{
|
||||
nvStatus = rpcRmApiControl_dce(pRmApi, displayCtrlDPIRQ.hClient, displayCtrlDPIRQ.hObject, NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION,
|
||||
&displayCtrlDPIRQ.setEventParams,sizeof(displayCtrlDPIRQ.setEventParams));
|
||||
if (nvStatus != NV_OK)
|
||||
{
|
||||
NV_PRINTF(LEVEL_ERROR, "rpcRmApiControl_dce displaySWEventDPIRQ object failed\n");
|
||||
nvStatus = NV_ERR_GENERIC;
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
out:
|
||||
@@ -191,4 +239,8 @@ dceclientStateDestroy_IMPL
|
||||
}
|
||||
display.valid = NV_FALSE;
|
||||
displaySW.valid = NV_FALSE;
|
||||
displaySWEventHotplug.valid = NV_FALSE;
|
||||
displaySWEventDPIRQ.valid = NV_FALSE;
|
||||
displayCtrlHotplug.valid = NV_FALSE;
|
||||
displayCtrlDPIRQ.valid = NV_FALSE;
|
||||
}
|
||||
|
||||
@@ -59,6 +59,10 @@ extern DEVICE devices[MAX_RM_CLIENTS];
|
||||
extern SUBDEVICE subdevices[MAX_RM_CLIENTS];
|
||||
extern DISPLAY_COMMON display;
|
||||
extern DISPLAY_SW displaySW;
|
||||
extern DISPLAY_SW_EVENT displaySWEventHotplug;
|
||||
extern DISPLAY_SW_EVENT displaySWEventDPIRQ;
|
||||
extern DISPLAY_HPD_CTRL displayCtrlHotplug;
|
||||
extern DISPLAY_HPD_CTRL displayCtrlDPIRQ;
|
||||
|
||||
NV_STATUS
|
||||
dceclientInitRpcInfra_IMPL
|
||||
@@ -413,6 +417,7 @@ NV_STATUS rpcRmApiControl_dce
|
||||
rpc_generic_union *msg_data;
|
||||
rpc_gsp_rm_control_v *rpc_params = NULL;
|
||||
NV_STATUS status = NV_ERR_NOT_SUPPORTED;
|
||||
NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS setEventParams = { };
|
||||
|
||||
NV_PRINTF(LEVEL_INFO, "NVRM_RPC_DCE : Prepare and send RmApiControl RPC\n");
|
||||
|
||||
@@ -442,6 +447,28 @@ NV_STATUS rpcRmApiControl_dce
|
||||
rpc_params->paramsSize = paramsSize;
|
||||
portMemCopy(rpc_params->params, paramsSize,pParamStructPtr, paramsSize);
|
||||
|
||||
if (!pGpu->getProperty(pGpu, PDB_PROP_GPU_IN_PM_RESUME_CODEPATH))
|
||||
{
|
||||
if (cmd == NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION)
|
||||
{
|
||||
portMemCopy(&setEventParams, paramsSize,pParamStructPtr, paramsSize);
|
||||
if (setEventParams.event == NV2080_NOTIFIERS_HOTPLUG)
|
||||
{
|
||||
displayCtrlHotplug.hClient = rpc_params->hClient;
|
||||
displayCtrlHotplug.hObject = rpc_params->hObject;
|
||||
portMemCopy(&displayCtrlHotplug.setEventParams, rpc_params->paramsSize, rpc_params->params, rpc_params->paramsSize);
|
||||
displayCtrlHotplug.valid = NV_TRUE;
|
||||
}
|
||||
if (setEventParams.event == NV2080_NOTIFIERS_DP_IRQ)
|
||||
{
|
||||
displayCtrlDPIRQ.hClient = rpc_params->hClient;
|
||||
displayCtrlDPIRQ.hObject = rpc_params->hObject;
|
||||
portMemCopy(&displayCtrlDPIRQ.setEventParams, rpc_params->paramsSize, rpc_params->params, rpc_params->paramsSize);
|
||||
displayCtrlDPIRQ.valid = NV_TRUE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
status = _dceRpcIssueAndWait(pRmApi);
|
||||
if (status != NV_OK)
|
||||
{
|
||||
@@ -482,6 +509,7 @@ NV_STATUS rpcRmApiAlloc_dce
|
||||
NV_STATUS status;
|
||||
NvU32 paramsSize;
|
||||
NvBool bNullAllowed;
|
||||
NV0005_ALLOC_PARAMETERS displaySWEventAllocParams;
|
||||
|
||||
NV_PRINTF(LEVEL_INFO, "NVRM_RPC_DCE: Prepare and send RmApiAlloc RPC\n");
|
||||
|
||||
@@ -598,6 +626,30 @@ NV_STATUS rpcRmApiAlloc_dce
|
||||
portMemCopy(&displaySW.displaySWAllocParams, rpc_params->paramsSize, rpc_params->params, rpc_params->paramsSize);
|
||||
displaySW.valid = NV_TRUE;
|
||||
}
|
||||
|
||||
if (hClass == NV01_EVENT_KERNEL_CALLBACK_EX)
|
||||
{
|
||||
portMemCopy(&displaySWEventAllocParams, rpc_params->paramsSize, rpc_params->params, rpc_params->paramsSize);
|
||||
if (0x4000001 == displaySWEventAllocParams.notifyIndex)
|
||||
{
|
||||
displaySWEventHotplug.hClient = rpc_params->hClient;
|
||||
displaySWEventHotplug.hParent = rpc_params->hParent;
|
||||
displaySWEventHotplug.hObject = rpc_params->hObject;
|
||||
displaySWEventHotplug.hClass = rpc_params->hClass;
|
||||
portMemCopy(&displaySWEventHotplug.displaySWEventAllocParams, rpc_params->paramsSize, rpc_params->params, rpc_params->paramsSize);
|
||||
displaySWEventHotplug.valid = NV_TRUE;
|
||||
}
|
||||
|
||||
if (0x4000007 == displaySWEventAllocParams.notifyIndex)
|
||||
{
|
||||
displaySWEventDPIRQ.hClient = rpc_params->hClient;
|
||||
displaySWEventDPIRQ.hParent = rpc_params->hParent;
|
||||
displaySWEventDPIRQ.hObject = rpc_params->hObject;
|
||||
displaySWEventDPIRQ.hClass = rpc_params->hClass;
|
||||
portMemCopy(&displaySWEventDPIRQ.displaySWEventAllocParams, rpc_params->paramsSize, rpc_params->params, rpc_params->paramsSize);
|
||||
displaySWEventDPIRQ.valid = NV_TRUE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
status = _dceRpcIssueAndWait(pRmApi);
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
NVIDIA_VERSION = 35.1.0
|
||||
NVIDIA_VERSION = 35.2.1
|
||||
|
||||
# This file.
|
||||
VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))
|
||||
|
||||
@@ -3,10 +3,10 @@ Updating prebuilts and/or headers
|
||||
c2e810fc3453d74ee0493168dbf7981ba482acd3 - NVIDIA-kernel-module-source-TempVersion/SECURITY.md
|
||||
7d577fdb9594ae572ff38fdda682a4796ab832ca - NVIDIA-kernel-module-source-TempVersion/COPYING
|
||||
12f1806bdc25917299525e0e48815306159de132 - NVIDIA-kernel-module-source-TempVersion/Makefile
|
||||
845f84d973e2d7122831bc1f118f27145c691080 - NVIDIA-kernel-module-source-TempVersion/README.md
|
||||
e6b4187ada7d6a39d3a30852cae28be87ccc972e - NVIDIA-kernel-module-source-TempVersion/README.md
|
||||
4f4410c3c8db46e5a98d7a35f7d909a49de6cb43 - NVIDIA-kernel-module-source-TempVersion/kernel-open/Makefile
|
||||
d8d7c839f0517ae8092f9c0679d5ca05f03ec741 - NVIDIA-kernel-module-source-TempVersion/kernel-open/conftest.sh
|
||||
fb6731582ade01ed43aab7b0ad2907736547ee11 - NVIDIA-kernel-module-source-TempVersion/kernel-open/Kbuild
|
||||
b2c1e4c27dd3a5199a8ee86028bccd61597c6b4d - NVIDIA-kernel-module-source-TempVersion/kernel-open/conftest.sh
|
||||
6959dba42eb4666c6881c247145029aea04b6179 - NVIDIA-kernel-module-source-TempVersion/kernel-open/Kbuild
|
||||
0b1508742a1c5a04b6c3a4be1b48b506f4180848 - NVIDIA-kernel-module-source-TempVersion/kernel-open/dkms.conf
|
||||
1d17329caf26cdf931122b3c3b7edf4932f43c38 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-msi.h
|
||||
88399279bd5e31b6e77cb32c7ef6220ce529526b - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-hypervisor.h
|
||||
@@ -53,7 +53,7 @@ f3e0f71abf34300d322e313adcd4fcbde9aa6f87 - NVIDIA-kernel-module-source-TempVersi
|
||||
256b5dc6f28738b3ce656c984f01d8f3e13e9faa - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-pgprot.h
|
||||
c57259130166701bf6d5e5bb1968397716d29fc0 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-platform.h
|
||||
84e9b6cba7ba26ef4032666f769c5b43fa510aad - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-list-helpers.h
|
||||
53ceca28c6a6da14ef62a4c57545089c48e6b2be - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv.h
|
||||
8e1b4b8e3cafa4b001cb9cfa4b3fbd36d6757033 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv.h
|
||||
910255a4d92e002463175a28e38c3f24716fb654 - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nvkms-api-types.h
|
||||
42ece56d0459eb9f27b2497de48f08360c4f7f6b - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nvlimits.h
|
||||
4a8b7f3cc65fa530670f510796bef51cf8c4bb6b - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/nv-register-module.h
|
||||
@@ -65,7 +65,7 @@ d25291d32caef187daf3589ce4976e4fa6bec70d - NVIDIA-kernel-module-source-TempVersi
|
||||
cda75171ca7d8bf920aab6d56ef9aadec16fd15d - NVIDIA-kernel-module-source-TempVersion/kernel-open/common/inc/os/nv_memory_type.h
|
||||
2ea1436104463c5e3d177e8574c3b4298976d37e - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-modeset/nvkms-ioctl.h
|
||||
17855f638fd09abfec7d188e49b396793a9f6106 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-modeset/nvkms.h
|
||||
8bcd1ca9c55362c03a435e226b05796be8c92226 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-modeset/nvidia-modeset-linux.c
|
||||
82765a7cb4e4ef29d76019a56bdcbe23dc6aa7c4 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-modeset/nvidia-modeset-linux.c
|
||||
0b7e063481a0e195c6e91a4d3464c4792c684f03 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-modeset/nv-kthread-q.c
|
||||
07a2d5fa54ff88a0cb30c0945ef3c33ca630a490 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-modeset/nvidia-modeset.Kbuild
|
||||
8a935bdda64e1d701279ef742b973c5dbed5727b - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h
|
||||
@@ -73,17 +73,17 @@ cda75171ca7d8bf920aab6d56ef9aadec16fd15d - NVIDIA-kernel-module-source-TempVersi
|
||||
9a0f445fda73c69e1bee7f6b121cbed33fcb01bf - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-mmap.c
|
||||
5f2dafa23c74ba7b04aaf43ef5808457ba9be2fa - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv.c
|
||||
95ae148b016e4111122c2d9f8f004b53e78998f3 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-memdbg.c
|
||||
9fb0f406f9a5af431f1b72c9c4395b4933dbcf58 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nvidia.Kbuild
|
||||
b5e5c9aa7b2f6e855d926fa0268434806efccfe6 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nvidia.Kbuild
|
||||
3ee953312a6a246d65520fc4a65407f448d1d2b8 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-gpio.c
|
||||
cded6e9b6324fd429b865173596c8e549a682bba - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv_uvm_interface.c
|
||||
9f2298f179ad00f1a914b26b274eb2a68068eece - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-i2c.c
|
||||
5f2e279a4abe0dabd478b1589be67df18de4b09d - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-i2c.c
|
||||
c1ebcfec42f7898dd9d909eacd439d288b80523f - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/os-mlock.c
|
||||
d11ab03a617b29efcf00f85e24ebce60f91cf82c - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-backlight.c
|
||||
dc39c4ee87f4dc5f5ccc179a98e07ddb82bb8bce - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-modeset-interface.c
|
||||
93511db745073b4a906fe28bea03c3b3d76d4df4 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-host1x.c
|
||||
7b1bd10726481626dd51f4eebb693794561c20f6 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-host1x.c
|
||||
06e7ec77cd21c43f900984553a4960064753e444 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-platform-pm.c
|
||||
335e7a5c99c7e8412a425adb82834234cd76b985 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/os-interface.c
|
||||
cd7e12552cb5249e5c23147d5cc924681c691e8a - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-platform.c
|
||||
4bab66073c9c68a22506693a0e6f0f8b32aca330 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/os-interface.c
|
||||
ae8e266e29e093a2edaa66169c5736df3c64727d - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-platform.c
|
||||
805042e7cdb9663a0d3ca3064baeec8aa8eb3688 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-ibmnpu.c
|
||||
c7f1aaa6a5f3a3cdf1e5f80adf40b3c9f185fb94 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-report-err.c
|
||||
0b0ec8d75dfece909db55136731196162c4152d5 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-dmabuf.c
|
||||
@@ -99,7 +99,7 @@ cf90d9ea3abced81d182ab3c4161e1b5d3ad280d - NVIDIA-kernel-module-source-TempVersi
|
||||
218aac0c408be15523a2d0b70fdbdadd7e1a2e48 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-imp.c
|
||||
6d4fbea733fdcd92fc6a8a5884e8bb359f9e8abd - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/rmp2pdefines.h
|
||||
5ac10d9b20ccd37e1e24d4a81b8ac8f83db981e4 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-vtophys.c
|
||||
cbfee8ea704ceb9f223e4f32c57e515350b8d9fd - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-dma.c
|
||||
9999872b1513360d8ecf6c0894f81c63e7d435e9 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-dma.c
|
||||
fc566df59becef7bc7511ae62a9a97b1532a5af2 - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-frontend.c
|
||||
b71bf4426322ab59e78e2a1500509a5f4b2b71ab - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-pat.h
|
||||
a3626bf1b80a81c14408c5181e8bd27696df2caf - NVIDIA-kernel-module-source-TempVersion/kernel-open/nvidia/nv-pci.c
|
||||
@@ -189,7 +189,7 @@ d2c79c8a4e914519d653d1f14f706ec4a1f787e8 - NVIDIA-kernel-module-source-TempVersi
|
||||
e6d500269128cbd93790fe68fbcad5ba45c2ba7d - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/hdmipacket/nvhdmipkt_C371.c
|
||||
90e8ce7638a28cd781b5d30df565116dc1cea9e8 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/hdmipacket/nvhdmipkt.h
|
||||
f75b1d98895bdccda0db2d8dd8feba53b88180c5 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/displayid.h
|
||||
65f2503bea8aa1847948cc0d628493e89775c4f3 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/nvt_displayid20.c
|
||||
ba9e382b24f57caa9dcf1c26a60b1f2070b1b9dd - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/nvt_displayid20.c
|
||||
28d7b753825d5f4a9402aff14488c125453e95c5 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/nvt_tv.c
|
||||
b4813a5e854e75fb38f460e0c27dca8e1ce8dc21 - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/nvt_edid.c
|
||||
1290abde75d218ae24f930c3b011042a3f360c2e - NVIDIA-kernel-module-source-TempVersion/src/common/modeset/timing/displayid20.h
|
||||
@@ -597,7 +597,7 @@ e02e5621eaea52a2266a86dcd587f4714680caf4 - NVIDIA-kernel-module-source-TempVersi
|
||||
020194b85245bad5de4dfe372a7ccb0c247d6ede - NVIDIA-kernel-module-source-TempVersion/src/common/displayport/inc/dptestutil/dp_testmessage.h
|
||||
2f60ba753549b232e1b995046a356dbe0eced04a - NVIDIA-kernel-module-source-TempVersion/src/common/shared/nvstatus/nvstatus.c
|
||||
ebccc5c2af2863509e957fe98b01d9a14d8b0367 - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nv_list.h
|
||||
cd902d07cc83444b150453d7baefd0e234c26ac2 - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nvUnixVersion.h
|
||||
a48b7d7df5dccec13695d1e52d415b6809b86b89 - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nvUnixVersion.h
|
||||
b85b49fc4ed38a241c79731a02b3b040a654a52a - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nvctassert.h
|
||||
764e5c4364922e3953b4db0411d1d3c3bdac99f4 - NVIDIA-kernel-module-source-TempVersion/src/common/inc/nvlog_defs.h
|
||||
8f0d91e1a8f0d3474fb91dc3e6234e55d2c79fcc - NVIDIA-kernel-module-source-TempVersion/src/common/inc/rmosxfac.h
|
||||
@@ -645,11 +645,11 @@ be3a1682574426c1bf75fcdf88278c18f2783c3f - NVIDIA-kernel-module-source-TempVersi
|
||||
75e8a8747795fad89b4d2b662477e5454863dcc7 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-flip.h
|
||||
d7861e2373ac04ffaf6c15caeba887f727aa41fb - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-dma.h
|
||||
182a47c12496b8b7da1c4fe7035d6b36d7316322 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-prealloc-types.h
|
||||
248d900394aa2b58669300af4f5d26eac23edd23 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-types.h
|
||||
9a3dd3f76dd4681d16ba4af5ef9f19fca984fa28 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-types.h
|
||||
ef78e73ec9c0b8341bd83306d1f3b2c35e20c43a - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-utils.h
|
||||
867e3091a945d3d43b2f28393b40edeb9d27597b - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-rmapi.h
|
||||
c1904d38785649d2614563d0cd7de28a15ce4486 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-modeset.h
|
||||
cc09ecd5ab724b244017929444309f8e77fc5a63 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-modepool.h
|
||||
118d0ea84ff81de16fbdc2c7daf249ee5c82ed6e - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-modepool.h
|
||||
412d8028a548e67e9ef85cb7d3f88385e70c56f9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-console-restore.h
|
||||
33dbf734c9757c2c40adb2fb185e964870217743 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-flip-workarea.h
|
||||
ebafc51b2b274cd1818e471850a5efa9618eb17d - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/include/nvkms-prealloc.h
|
||||
@@ -674,7 +674,7 @@ fb242aa7a53983118ee019415076033e596374af - NVIDIA-kernel-module-source-TempVersi
|
||||
f6875ef0da055900ef6ef1da5dc94cba2837e4d0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/kapi/src/nvkms-kapi-channelevent.c
|
||||
01d943d6edb0c647c2b8dbc44460948665b03e7a - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/kapi/src/nvkms-kapi-notifiers.c
|
||||
394ea31caa5957cfb2c8bb8c3cc0e4703213fe7f - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/kapi/src/nvkms-kapi.c
|
||||
3f978853dfa0435b746ff8c954b8e5e5f0451b43 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-modepool.c
|
||||
ec97ab37cdf2cec0283657c2c04a139a1a168337 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-modepool.c
|
||||
85ddb19f89833ca57fd2deff2e2b4566e162a56c - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-hal.c
|
||||
8415bcd6ab34e356374659e965790a0715ed7971 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-prealloc.c
|
||||
c98f76bcfc7c654a619762ebc3a2599f9aa89f8d - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-3dvision.c
|
||||
@@ -684,20 +684,20 @@ e9626eee225e58ec2d5be756c5015775ca5e54b9 - NVIDIA-kernel-module-source-TempVersi
|
||||
89baced4cf1a96b7693c9e2f85b01093bbba73f7 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-rm.c
|
||||
7ef594aea1e80408148c3661477a4edc6e8d8d50 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-flip.c
|
||||
07c2f10473e2fbe921b2781cc107b5e56e6373e3 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-attributes.c
|
||||
d28cd72c8dca4cb54a15630b80026eca57a9ed80 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-evo.c
|
||||
21c8184de2c9150c21ac5d6fba24e79e513a0a69 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-evo.c
|
||||
da726d20eea99a96af4c10aace88f419e8ee2a34 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-event.c
|
||||
5c79c271609ebcc739f8d73d7d47f0b376298438 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-rmapi-dgpu.c
|
||||
b55665d7bceaad04bbf29a68f44536518302c3d6 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-evo2.c
|
||||
6b79c2ce1658722fa6b3a70fb5e36f37c40d8f96 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-modeset.c
|
||||
f8bdd07a27296ef6aab86cc9dbccf8df811fff24 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-modeset.c
|
||||
1918ca3aa611cd9dfc79d46d038ab22706f0b1ed - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-cursor3.c
|
||||
add6682206360cb899ae13bae6dc2c19d830d7b7 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-dpy.c
|
||||
24156462f25922c8de5b5d2558db36b2e68b28ed - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-dpy.c
|
||||
c2870190ca4c4d5b3a439386583d0a7c193d6263 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-hw-states.c
|
||||
f27f52dc428a6adeb936c8cf99e1fc2d8b0ad667 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-dma.c
|
||||
5acf19920d56793d96c80e8461b0d0213c871b34 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-surface.c
|
||||
c2d0e6bef0c4929a3ca4adfd74bd6168fa4aa000 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-framelock.c
|
||||
673ad86616f9863766bfec0e118c918297d32010 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/g_nvkms-evo-states.c
|
||||
c799d52bdc792efc377fb5cd307b0eb445c44d6a - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-cursor2.c
|
||||
0d39e349fdf33d550497527fc8d43f14e752df6c - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-hdmi.c
|
||||
94f4736acf7981cebfd74302a21f19cdbafa8d71 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-hdmi.c
|
||||
8f22c278a5839d36f74f85469b2d927d9265cb80 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-utils.c
|
||||
eb09642e8b5d9333699f817caaf20483c840b376 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms.c
|
||||
ab17e5b4cafa92aa03691a0c187ef8c9ae53fa59 - NVIDIA-kernel-module-source-TempVersion/src/nvidia-modeset/src/nvkms-cursor.c
|
||||
@@ -724,7 +724,7 @@ aba0bd796d932fa19e8fad55ed683ae57d68bffb - NVIDIA-kernel-module-source-TempVersi
|
||||
e3679844971ecc4447259fb1bdf4fafbbdff2395 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/osapi.h
|
||||
4750735d6f3b334499c81d499a06a654a052713d - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/nv-caps.h
|
||||
1e89b4a52a5cdc6cac511ff148c7448d53cf5d5c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/os_custom.h
|
||||
d576ede913ef8cf4347ef0e8dbfe9c2d992b7965 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/nv.h
|
||||
20865ca9b29527328aeb932cde6c5fea6533164f - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/nv.h
|
||||
ddfedb3b81feb09ea9daadf1a7f63f6309ee6e3b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/rmobjexportimport.h
|
||||
9c7b09c55aabbd670c860bdaf8ec9e8ff254b5e9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/nv-kernel-rmapi-ops.h
|
||||
cc3b2163238b2a8acb7e3ca213fb1ae6c5f0a409 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/include/osfuncs.h
|
||||
@@ -740,7 +740,7 @@ b5b409625fde1b640e4e93276e35248f0fccfa4c - NVIDIA-kernel-module-source-TempVersi
|
||||
f134270af5ecd7c5ba91bf5228fe3166b101dd6e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/src/escape.c
|
||||
690927567b5344c8030e2c52d91f824bb94e956c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/src/registry.c
|
||||
53cd45a8121f8acb72be746e389246e1424176f7 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/src/osapi.c
|
||||
05b5aa5ad6a7df974f05608622ae260d70a550db - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c
|
||||
54b912b640bdcae42f38c41694eb20abcaad61a7 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/src/osmemdesc.c
|
||||
fb5272f3d0e465aedbc99ddcabb1c6c428837a6e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c
|
||||
0cff83f4fdcc8d025cd68e0a12faaeead09fa03b - NVIDIA-kernel-module-source-TempVersion/src/nvidia/kernel/inc/tmr.h
|
||||
7df66a87c9498ae73c986e60fcb9cb1cbcd19e19 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/kernel/inc/objrpc.h
|
||||
@@ -795,8 +795,8 @@ bc2b57acc8fa8644615168e3ddbaf7ac161a7a04 - NVIDIA-kernel-module-source-TempVersi
|
||||
a64c51c515eb76208a822f1f623d11e2edd8d7ac - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c
|
||||
a54628e9d2733c6d0470e1e73bca1573e6486ab3 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_event_kernel.c
|
||||
1f4d15f959df38f4f6ea48c7b10fc859c6e04b12 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/audio/hda_codec_api.c
|
||||
c3b93cf7e3c97beb1072135a58d211f67722ad10 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/dce_client/dce_client_rpc.c
|
||||
7db9691e2078d4b093f2e09c8ba0e6245e505ef1 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/dce_client/dce_client.c
|
||||
8780c5fbaf8505df6b136de0a97b6cc49bdd22b2 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/dce_client/dce_client_rpc.c
|
||||
cfcb93ff58386803393891c9d404e03f2d9f47fb - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/gpu/dce_client/dce_client.c
|
||||
f89e982b0e31a1898e1e4749c9a8ae9f0bb59a0c - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/deprecated_context.c
|
||||
d92267a3394ded5d7d218530fd16ce00a920b1d6 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/alloc_free.c
|
||||
2279fd14aab9b5f20b8fc21f04dd0fca41e418c9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/rmapi/event_notification.c
|
||||
@@ -830,7 +830,7 @@ af4ffa4b423e07cf40eb863c11dbf515c7104874 - NVIDIA-kernel-module-source-TempVersi
|
||||
1793e056a0afcc5e1f5bb58b207b49c5f1556eca - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/os/os_stubs.c
|
||||
63e5e17280d865ace8cdd8eb8a2598d3d7830ad7 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/os/os_sanity.c
|
||||
8e5af753de1725dd919185c29d03ccb0934fab6e - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/os/os_init.c
|
||||
8d96c1b4c00f3a029ba8c27dd2e8e88405c3a1b6 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/core/locks_minimal.c
|
||||
fe91b43c37b64472450cc25329d2dea74d2a9fcf - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/core/locks_minimal.c
|
||||
c0822891f614e6ec847acb971e68aad8847e0cd7 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/core/locks_common.c
|
||||
c68f2c96bfc6fce483a332a5824656d72986a145 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/core/system.c
|
||||
37000b419d23a8b052fc1218f09815fafb1d89c9 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/src/kernel/core/hal_mgr.c
|
||||
@@ -957,7 +957,7 @@ d04adc777f547ae6d1369cf4c94963e5abf90b86 - NVIDIA-kernel-module-source-TempVersi
|
||||
ac3965eea078f1998c3a3041f14212578682e599 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_vaspace_nvoc.c
|
||||
0dae533422e24d91a29c82d7be619160bbb6f6be - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_context_dma_nvoc.h
|
||||
3f5a391895fc900396bae68761fe9b4dcb382ec0 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_event_buffer_nvoc.h
|
||||
9eb042cd3feb89e0964e3f4b948ee690f02bf604 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_dce_client_nvoc.h
|
||||
ba2d5590218979b295eed05457e64c7276a208d1 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_dce_client_nvoc.h
|
||||
285af0d0517cb191387a05ad596f74291ec81737 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_mem_desc_nvoc.h
|
||||
9646d1c4d472ad800c7c93eec15cc03dd9201073 - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_disp_objs_nvoc.h
|
||||
c370a103a4c1c9cf2df3763988e77ef8f7bc6afb - NVIDIA-kernel-module-source-TempVersion/src/nvidia/generated/g_gpu_db_nvoc.h
|
||||
|
||||
@@ -1 +1 @@
|
||||
jetson_35.1
|
||||
jetson_35.2.1
|
||||
|
||||
Reference in New Issue
Block a user