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README.md
Normal file
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README.md
Normal file
@@ -0,0 +1,987 @@
|
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# NVIDIA Linux Open GPU Kernel Module Source
|
||||
|
||||
This is the source release of the NVIDIA Linux open GPU kernel modules,
|
||||
version 580.00.
|
||||
|
||||
|
||||
## How to Build
|
||||
|
||||
To build:
|
||||
|
||||
make modules -j$(nproc)
|
||||
|
||||
To install, first uninstall any existing NVIDIA kernel modules. Then,
|
||||
as root:
|
||||
|
||||
make modules_install -j$(nproc)
|
||||
|
||||
Note that the kernel modules built here must be used with GSP
|
||||
firmware and user-space NVIDIA GPU driver components from a corresponding
|
||||
580.00 driver release. This can be achieved by installing
|
||||
the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
|
||||
option. E.g.,
|
||||
|
||||
sh ./NVIDIA-Linux-[...].run --no-kernel-modules
|
||||
|
||||
|
||||
## Supported Target CPU Architectures
|
||||
|
||||
Currently, the kernel modules can be built for x86_64 or aarch64.
|
||||
If cross-compiling, set these variables on the make command line:
|
||||
|
||||
TARGET_ARCH=aarch64|x86_64
|
||||
CC
|
||||
LD
|
||||
AR
|
||||
CXX
|
||||
OBJCOPY
|
||||
|
||||
E.g.,
|
||||
|
||||
# compile on x86_64 for aarch64
|
||||
make modules -j$(nproc) \
|
||||
TARGET_ARCH=aarch64 \
|
||||
CC=aarch64-linux-gnu-gcc \
|
||||
LD=aarch64-linux-gnu-ld \
|
||||
AR=aarch64-linux-gnu-ar \
|
||||
CXX=aarch64-linux-gnu-g++ \
|
||||
OBJCOPY=aarch64-linux-gnu-objcopy
|
||||
|
||||
|
||||
## Other Build Knobs
|
||||
|
||||
NV_VERBOSE - Set this to "1" to print each complete command executed;
|
||||
otherwise, a succinct "CC" line is printed.
|
||||
|
||||
DEBUG - Set this to "1" to build the kernel modules as debug. By default, the
|
||||
build compiles without debugging information. This also enables
|
||||
various debug log messages in the kernel modules.
|
||||
|
||||
These variables can be set on the make command line. E.g.,
|
||||
|
||||
make modules -j$(nproc) NV_VERBOSE=1
|
||||
|
||||
|
||||
## Supported Toolchains
|
||||
|
||||
Any reasonably modern version of GCC or Clang can be used to build the
|
||||
kernel modules. Note that the kernel interface layers of the kernel
|
||||
modules must be built with the toolchain that was used to build the
|
||||
kernel.
|
||||
|
||||
|
||||
## Supported Linux Kernel Versions
|
||||
|
||||
The NVIDIA open kernel modules support the same range of Linux kernel
|
||||
versions that are supported with the proprietary NVIDIA kernel modules.
|
||||
This is currently Linux kernel 4.15 or newer.
|
||||
|
||||
|
||||
## How to Contribute
|
||||
|
||||
Contributions can be made by creating a pull request on
|
||||
https://github.com/NVIDIA/open-gpu-kernel-modules
|
||||
We'll respond via GitHub.
|
||||
|
||||
Note that when submitting a pull request, you will be prompted to accept
|
||||
a Contributor License Agreement.
|
||||
|
||||
This code base is shared with NVIDIA's proprietary drivers, and various
|
||||
processing is performed on the shared code to produce the source code that is
|
||||
published here. This has several implications for the foreseeable future:
|
||||
|
||||
* The GitHub repository will function mostly as a snapshot of each driver
|
||||
release.
|
||||
|
||||
* We do not expect to be able to provide revision history for individual
|
||||
changes that were made to NVIDIA's shared code base. There will likely
|
||||
only be one git commit per driver release.
|
||||
|
||||
* We may not be able to reflect individual contributions as separate
|
||||
git commits in the GitHub repository.
|
||||
|
||||
* Because the code undergoes various processing prior to publishing here,
|
||||
contributions made here require manual merging to be applied to the shared
|
||||
code base. Therefore, large refactoring changes made here may be difficult to
|
||||
merge and accept back into the shared code base. If you have large
|
||||
refactoring to suggest, please contact us in advance, so we can coordinate.
|
||||
|
||||
|
||||
## How to Report Issues
|
||||
|
||||
Problems specific to the Open GPU Kernel Modules can be reported in the
|
||||
Issues section of the https://github.com/NVIDIA/open-gpu-kernel-modules
|
||||
repository.
|
||||
|
||||
Further, any of the existing bug reporting venues can be used to communicate
|
||||
problems to NVIDIA, such as our forum:
|
||||
|
||||
https://forums.developer.nvidia.com/c/gpu-graphics/linux/148
|
||||
|
||||
or linux-bugs@nvidia.com.
|
||||
|
||||
Please see the 'NVIDIA Contact Info and Additional Resources' section
|
||||
of the NVIDIA GPU Driver README for details.
|
||||
|
||||
Please see the separate [SECURITY.md](SECURITY.md) document if you
|
||||
believe you have discovered a security vulnerability in this software.
|
||||
|
||||
|
||||
## Kernel Interface and OS-Agnostic Components of Kernel Modules
|
||||
|
||||
Most of NVIDIA's kernel modules are split into two components:
|
||||
|
||||
* An "OS-agnostic" component: this is the component of each kernel module
|
||||
that is independent of operating system.
|
||||
|
||||
* A "kernel interface layer": this is the component of each kernel module
|
||||
that is specific to the Linux kernel version and configuration.
|
||||
|
||||
When packaged in the NVIDIA .run installation package, the OS-agnostic
|
||||
component is provided as a binary: it is large and time-consuming to
|
||||
compile, so pre-built versions are provided so that the user does
|
||||
not have to compile it during every driver installation. For the
|
||||
nvidia.ko kernel module, this component is named "nv-kernel.o_binary".
|
||||
For the nvidia-modeset.ko kernel module, this component is named
|
||||
"nv-modeset-kernel.o_binary". Neither nvidia-drm.ko nor nvidia-uvm.ko
|
||||
have OS-agnostic components.
|
||||
|
||||
The kernel interface layer component for each kernel module must be built
|
||||
for the target kernel.
|
||||
|
||||
|
||||
## Directory Structure Layout
|
||||
|
||||
- `kernel-open/` The kernel interface layer
|
||||
- `kernel-open/nvidia/` The kernel interface layer for nvidia.ko
|
||||
- `kernel-open/nvidia-drm/` The kernel interface layer for nvidia-drm.ko
|
||||
- `kernel-open/nvidia-modeset/` The kernel interface layer for nvidia-modeset.ko
|
||||
- `kernel-open/nvidia-uvm/` The kernel interface layer for nvidia-uvm.ko
|
||||
|
||||
- `src/` The OS-agnostic code
|
||||
- `src/nvidia/` The OS-agnostic code for nvidia.ko
|
||||
- `src/nvidia-modeset/` The OS-agnostic code for nvidia-modeset.ko
|
||||
- `src/common/` Utility code used by one or more of nvidia.ko and nvidia-modeset.ko
|
||||
- `nouveau/` Tools for integration with the Nouveau device driver
|
||||
|
||||
|
||||
## Nouveau device driver integration
|
||||
|
||||
The Python script in the 'nouveau' directory is used to extract some of the
|
||||
firmware binary images (and related data) encoded in the source code and
|
||||
store them as distinct files. These files are used by the Nouveau device
|
||||
driver to load and communicate with the GSP firmware.
|
||||
|
||||
The layout of the binary files is described in nouveau_firmware_layout.ods,
|
||||
which is an OpenDocument Spreadsheet file, compatible with most spreadsheet
|
||||
software applications.
|
||||
|
||||
|
||||
## Compatible GPUs
|
||||
|
||||
The NVIDIA open kernel modules can be used on any Turing or later GPU (see the
|
||||
table below).
|
||||
|
||||
For details on feature support and limitations, see the NVIDIA GPU driver
|
||||
end user README here:
|
||||
|
||||
https://us.download.nvidia.com/XFree86/Linux-x86_64/580.00/README/kernel_open.html
|
||||
|
||||
For vGPU support, please refer to the README.vgpu packaged in the vGPU Host
|
||||
Package for more details.
|
||||
|
||||
In the below table, if three IDs are listed, the first is the PCI Device
|
||||
ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI
|
||||
Subsystem Device ID.
|
||||
|
||||
| Product Name | PCI ID |
|
||||
| ------------------------------------------------------- | -------------- |
|
||||
| NVIDIA TITAN RTX | 1E02 |
|
||||
| NVIDIA GeForce RTX 2080 Ti | 1E04 |
|
||||
| NVIDIA GeForce RTX 2080 Ti | 1E07 |
|
||||
| NVIDIA CMP 50HX | 1E09 |
|
||||
| Quadro RTX 6000 | 1E30 |
|
||||
| Quadro RTX 8000 | 1E30 1028 129E |
|
||||
| Quadro RTX 8000 | 1E30 103C 129E |
|
||||
| Quadro RTX 8000 | 1E30 10DE 129E |
|
||||
| Quadro RTX 6000 | 1E36 |
|
||||
| Quadro RTX 8000 | 1E78 10DE 13D8 |
|
||||
| Quadro RTX 6000 | 1E78 10DE 13D9 |
|
||||
| NVIDIA GeForce RTX 2080 SUPER | 1E81 |
|
||||
| NVIDIA GeForce RTX 2080 | 1E82 |
|
||||
| NVIDIA GeForce RTX 2070 SUPER | 1E84 |
|
||||
| NVIDIA GeForce RTX 2080 | 1E87 |
|
||||
| NVIDIA GeForce RTX 2060 | 1E89 |
|
||||
| NVIDIA GeForce RTX 2080 | 1E90 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1025 1375 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 08A1 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 08A2 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 08EA |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 08EB |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 08EC |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 08ED |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 08EE |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 08EF |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 093B |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1028 093C |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 103C 8572 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 103C 8573 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 103C 8602 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 103C 8606 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 103C 86C6 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 103C 86C7 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 103C 87A6 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 103C 87A7 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1043 131F |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1043 137F |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1043 141F |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1043 1751 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1458 1660 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1458 1661 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1458 1662 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1458 75A6 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1458 75A7 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1458 86A6 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1458 86A7 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1462 1274 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1462 1277 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 152D 1220 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1558 95E1 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1558 97E1 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1A58 2002 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1A58 2005 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1A58 2007 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1A58 3000 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1A58 3001 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1E90 1D05 1069 |
|
||||
| NVIDIA GeForce RTX 2070 Super | 1E91 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 103C 8607 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 103C 8736 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 103C 8738 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 103C 8772 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 103C 878A |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 103C 878B |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1043 1E61 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1458 1511 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1458 75B3 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1458 75B4 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1458 76B2 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1458 76B3 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1458 78A2 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1458 78A3 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1458 86B2 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1458 86B3 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1462 12AE |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1462 12B0 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1462 12C6 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 17AA 22C3 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 17AA 22C5 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1A58 2009 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1A58 200A |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 1A58 3002 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1E91 8086 3012 |
|
||||
| NVIDIA GeForce RTX 2080 Super | 1E93 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1025 1401 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1025 149C |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1028 09D2 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 103C 8607 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 103C 86C7 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 103C 8736 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 103C 8738 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 103C 8772 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 103C 87A6 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 103C 87A7 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1458 75B1 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1458 75B2 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1458 76B0 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1458 76B1 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1458 78A0 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1458 78A1 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1458 86B0 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1458 86B1 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1462 12AE |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1462 12B0 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1462 12B4 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1462 12C6 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1558 50D3 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1558 70D1 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 17AA 22C3 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 17AA 22C5 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1A58 2009 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1A58 200A |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1A58 3002 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1E93 1D05 1089 |
|
||||
| Quadro RTX 5000 | 1EB0 |
|
||||
| Quadro RTX 4000 | 1EB1 |
|
||||
| Quadro RTX 5000 | 1EB5 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 1025 1375 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 1025 1401 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 1025 149C |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 1028 09C3 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 103C 8736 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 103C 8738 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 103C 8772 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 103C 8780 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 103C 8782 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 103C 8783 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 103C 8785 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 1043 1DD1 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 1462 1274 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 1462 12B0 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 1462 12C6 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 17AA 22B8 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 17AA 22BA |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 1A58 2005 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 1A58 2007 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 1A58 2008 |
|
||||
| Quadro RTX 5000 with Max-Q Design | 1EB5 1A58 200A |
|
||||
| Quadro RTX 4000 | 1EB6 |
|
||||
| Quadro RTX 4000 with Max-Q Design | 1EB6 1028 09C3 |
|
||||
| Quadro RTX 4000 with Max-Q Design | 1EB6 103C 8736 |
|
||||
| Quadro RTX 4000 with Max-Q Design | 1EB6 103C 8738 |
|
||||
| Quadro RTX 4000 with Max-Q Design | 1EB6 103C 8772 |
|
||||
| Quadro RTX 4000 with Max-Q Design | 1EB6 103C 8780 |
|
||||
| Quadro RTX 4000 with Max-Q Design | 1EB6 103C 8782 |
|
||||
| Quadro RTX 4000 with Max-Q Design | 1EB6 103C 8783 |
|
||||
| Quadro RTX 4000 with Max-Q Design | 1EB6 103C 8785 |
|
||||
| Quadro RTX 4000 with Max-Q Design | 1EB6 1462 1274 |
|
||||
| Quadro RTX 4000 with Max-Q Design | 1EB6 1462 1277 |
|
||||
| Quadro RTX 4000 with Max-Q Design | 1EB6 1462 12B0 |
|
||||
| Quadro RTX 4000 with Max-Q Design | 1EB6 1462 12C6 |
|
||||
| Quadro RTX 4000 with Max-Q Design | 1EB6 17AA 22B8 |
|
||||
| Quadro RTX 4000 with Max-Q Design | 1EB6 17AA 22BA |
|
||||
| Tesla T4 | 1EB8 10DE 12A2 |
|
||||
| NVIDIA GeForce RTX 2070 SUPER | 1EC2 |
|
||||
| NVIDIA GeForce RTX 2070 SUPER | 1EC7 |
|
||||
| NVIDIA GeForce RTX 2080 | 1ED0 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 1025 132D |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 1028 08ED |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 1028 08EE |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 1028 08EF |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 103C 8572 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 103C 8573 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 103C 8600 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 103C 8605 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 1043 138F |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 1043 15C1 |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 17AA 3FEE |
|
||||
| NVIDIA GeForce RTX 2080 with Max-Q Design | 1ED0 17AA 3FFE |
|
||||
| NVIDIA GeForce RTX 2070 Super | 1ED1 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1ED1 1025 1432 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1ED1 103C 8746 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1ED1 103C 878A |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1ED1 1043 165F |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1ED1 144D C192 |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1ED1 17AA 3FCE |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1ED1 17AA 3FCF |
|
||||
| NVIDIA GeForce RTX 2070 Super with Max-Q Design | 1ED1 17AA 3FD0 |
|
||||
| NVIDIA GeForce RTX 2080 Super | 1ED3 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 1025 1432 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 1028 09D1 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 103C 8746 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 103C 878A |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 1043 1D61 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 1043 1E51 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 1043 1F01 |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 17AA 3FCE |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 17AA 3FCF |
|
||||
| NVIDIA GeForce RTX 2080 Super with Max-Q Design | 1ED3 17AA 3FD0 |
|
||||
| Quadro RTX 5000 | 1EF5 |
|
||||
| NVIDIA GeForce RTX 2070 | 1F02 |
|
||||
| NVIDIA GeForce RTX 2060 | 1F03 |
|
||||
| NVIDIA GeForce RTX 2060 SUPER | 1F06 |
|
||||
| NVIDIA GeForce RTX 2070 | 1F07 |
|
||||
| NVIDIA GeForce RTX 2060 | 1F08 |
|
||||
| NVIDIA GeForce GTX 1650 | 1F0A |
|
||||
| NVIDIA CMP 40HX | 1F0B |
|
||||
| NVIDIA GeForce RTX 2070 | 1F10 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1025 132D |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1025 1342 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 08A1 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 08A2 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 08EA |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 08EB |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 08EC |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 08ED |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 08EE |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 08EF |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 093B |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1028 093C |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 103C 8572 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 103C 8573 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 103C 8602 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 103C 8606 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1043 132F |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1043 136F |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1043 1881 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1043 1E6E |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1458 1658 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1458 1663 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1458 1664 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1458 75A4 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1458 75A5 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1458 86A4 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1458 86A5 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1462 1274 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1462 1277 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1558 95E1 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1558 97E1 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1A58 2002 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1A58 2005 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1A58 2007 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1A58 3000 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1A58 3001 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1D05 105E |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1D05 1070 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 1D05 2087 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F10 8086 2087 |
|
||||
| NVIDIA GeForce RTX 2060 | 1F11 |
|
||||
| NVIDIA GeForce RTX 2060 | 1F12 |
|
||||
| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 1028 098F |
|
||||
| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 103C 8741 |
|
||||
| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 103C 8744 |
|
||||
| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 103C 878E |
|
||||
| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 103C 880E |
|
||||
| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 1043 1E11 |
|
||||
| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 1043 1F11 |
|
||||
| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 1462 12D9 |
|
||||
| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 17AA 3801 |
|
||||
| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 17AA 3802 |
|
||||
| NVIDIA GeForce RTX 2060 with Max-Q Design | 1F12 17AA 3803 |
|
||||
| NVIDIA GeForce RTX 2070 | 1F14 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1025 1401 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1025 1432 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1025 1442 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1025 1446 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1025 147D |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1028 09E2 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1028 09F3 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 8607 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 86C6 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 86C7 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 8736 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 8738 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 8746 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 8772 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 878A |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 878B |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 87A6 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 103C 87A7 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1043 174F |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1458 1512 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1458 75B5 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1458 75B6 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1458 76B4 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1458 76B5 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1458 78A4 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1458 78A5 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1458 86B4 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1458 86B5 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1462 12AE |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1462 12B0 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1462 12C6 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1558 50D3 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1558 70D1 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1A58 200C |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1A58 2011 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F14 1A58 3002 |
|
||||
| NVIDIA GeForce RTX 2060 | 1F15 |
|
||||
| Quadro RTX 3000 | 1F36 |
|
||||
| Quadro RTX 3000 with Max-Q Design | 1F36 1028 0990 |
|
||||
| Quadro RTX 3000 with Max-Q Design | 1F36 103C 8736 |
|
||||
| Quadro RTX 3000 with Max-Q Design | 1F36 103C 8738 |
|
||||
| Quadro RTX 3000 with Max-Q Design | 1F36 103C 8772 |
|
||||
| Quadro RTX 3000 with Max-Q Design | 1F36 1043 13CF |
|
||||
| Quadro RTX 3000 with Max-Q Design | 1F36 1414 0032 |
|
||||
| NVIDIA GeForce RTX 2060 SUPER | 1F42 |
|
||||
| NVIDIA GeForce RTX 2060 SUPER | 1F47 |
|
||||
| NVIDIA GeForce RTX 2070 | 1F50 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 1028 08ED |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 1028 08EE |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 1028 08EF |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 103C 8572 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 103C 8573 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 103C 8574 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 103C 8600 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 103C 8605 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 17AA 3FEE |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F50 17AA 3FFE |
|
||||
| NVIDIA GeForce RTX 2060 | 1F51 |
|
||||
| NVIDIA GeForce RTX 2070 | 1F54 |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F54 103C 878A |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F54 17AA 3FCE |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F54 17AA 3FCF |
|
||||
| NVIDIA GeForce RTX 2070 with Max-Q Design | 1F54 17AA 3FD0 |
|
||||
| NVIDIA GeForce RTX 2060 | 1F55 |
|
||||
| Quadro RTX 3000 | 1F76 |
|
||||
| Matrox D-Series D2450 | 1F76 102B 2800 |
|
||||
| Matrox D-Series D2480 | 1F76 102B 2900 |
|
||||
| NVIDIA GeForce GTX 1650 | 1F82 |
|
||||
| NVIDIA GeForce GTX 1630 | 1F83 |
|
||||
| NVIDIA GeForce GTX 1650 | 1F91 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 103C 863E |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 103C 86E7 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 103C 86E8 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 1043 12CF |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 1043 156F |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 1414 0032 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 144D C822 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 1462 127E |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 1462 1281 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 1462 1284 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 1462 1285 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 1462 129C |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 17AA 229F |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 17AA 3802 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 17AA 3806 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 17AA 3F1A |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F91 1A58 1001 |
|
||||
| NVIDIA GeForce GTX 1650 Ti | 1F95 |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1025 1479 |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1025 147A |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1025 147B |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1025 147C |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 103C 86E7 |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 103C 86E8 |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 103C 8815 |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1043 1DFF |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1043 1E1F |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 144D C838 |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1462 12BD |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1462 12C5 |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1462 12D2 |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 17AA 22C0 |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 17AA 22C1 |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 17AA 3837 |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 17AA 3F95 |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1A58 1003 |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1A58 1006 |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1A58 1007 |
|
||||
| NVIDIA GeForce GTX 1650 Ti with Max-Q Design | 1F95 1E83 3E30 |
|
||||
| NVIDIA GeForce GTX 1650 | 1F96 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F96 1462 1297 |
|
||||
| NVIDIA GeForce MX450 | 1F97 |
|
||||
| NVIDIA GeForce MX450 | 1F98 |
|
||||
| NVIDIA GeForce GTX 1650 | 1F99 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1025 1479 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1025 147A |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1025 147B |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1025 147C |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 103C 8815 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1043 13B2 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1043 1402 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1043 1902 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1462 12BD |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1462 12C5 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1462 12D2 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 17AA 22DA |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 17AA 3F93 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F99 1E83 3E30 |
|
||||
| NVIDIA GeForce MX450 | 1F9C |
|
||||
| NVIDIA GeForce GTX 1650 | 1F9D |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1043 128D |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1043 130D |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1043 149C |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1043 185C |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1043 189C |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1462 12F4 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1462 1302 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1462 131B |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1462 1326 |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1462 132A |
|
||||
| NVIDIA GeForce GTX 1650 with Max-Q Design | 1F9D 1462 132E |
|
||||
| NVIDIA GeForce MX550 | 1F9F |
|
||||
| NVIDIA GeForce MX550 | 1FA0 |
|
||||
| NVIDIA T1000 | 1FB0 1028 12DB |
|
||||
| NVIDIA T1000 | 1FB0 103C 12DB |
|
||||
| NVIDIA T1000 | 1FB0 103C 8A80 |
|
||||
| NVIDIA T1000 | 1FB0 10DE 12DB |
|
||||
| NVIDIA DGX Display | 1FB0 10DE 1485 |
|
||||
| NVIDIA T1000 | 1FB0 17AA 12DB |
|
||||
| NVIDIA T600 | 1FB1 1028 1488 |
|
||||
| NVIDIA T600 | 1FB1 103C 1488 |
|
||||
| NVIDIA T600 | 1FB1 103C 8A80 |
|
||||
| NVIDIA T600 | 1FB1 10DE 1488 |
|
||||
| NVIDIA T600 | 1FB1 17AA 1488 |
|
||||
| NVIDIA T400 | 1FB2 1028 1489 |
|
||||
| NVIDIA T400 | 1FB2 103C 1489 |
|
||||
| NVIDIA T400 | 1FB2 103C 8A80 |
|
||||
| NVIDIA T400 | 1FB2 10DE 1489 |
|
||||
| NVIDIA T400 | 1FB2 17AA 1489 |
|
||||
| NVIDIA T600 Laptop GPU | 1FB6 |
|
||||
| NVIDIA T550 Laptop GPU | 1FB7 |
|
||||
| Quadro T2000 | 1FB8 |
|
||||
| Quadro T2000 with Max-Q Design | 1FB8 1028 097E |
|
||||
| Quadro T2000 with Max-Q Design | 1FB8 103C 8736 |
|
||||
| Quadro T2000 with Max-Q Design | 1FB8 103C 8738 |
|
||||
| Quadro T2000 with Max-Q Design | 1FB8 103C 8772 |
|
||||
| Quadro T2000 with Max-Q Design | 1FB8 103C 8780 |
|
||||
| Quadro T2000 with Max-Q Design | 1FB8 103C 8782 |
|
||||
| Quadro T2000 with Max-Q Design | 1FB8 103C 8783 |
|
||||
| Quadro T2000 with Max-Q Design | 1FB8 103C 8785 |
|
||||
| Quadro T2000 with Max-Q Design | 1FB8 103C 87F0 |
|
||||
| Quadro T2000 with Max-Q Design | 1FB8 1462 1281 |
|
||||
| Quadro T2000 with Max-Q Design | 1FB8 1462 12BD |
|
||||
| Quadro T2000 with Max-Q Design | 1FB8 17AA 22C0 |
|
||||
| Quadro T2000 with Max-Q Design | 1FB8 17AA 22C1 |
|
||||
| Quadro T1000 | 1FB9 |
|
||||
| Quadro T1000 with Max-Q Design | 1FB9 1025 1479 |
|
||||
| Quadro T1000 with Max-Q Design | 1FB9 1025 147A |
|
||||
| Quadro T1000 with Max-Q Design | 1FB9 1025 147B |
|
||||
| Quadro T1000 with Max-Q Design | 1FB9 1025 147C |
|
||||
| Quadro T1000 with Max-Q Design | 1FB9 103C 8736 |
|
||||
| Quadro T1000 with Max-Q Design | 1FB9 103C 8738 |
|
||||
| Quadro T1000 with Max-Q Design | 1FB9 103C 8772 |
|
||||
| Quadro T1000 with Max-Q Design | 1FB9 103C 8780 |
|
||||
| Quadro T1000 with Max-Q Design | 1FB9 103C 8782 |
|
||||
| Quadro T1000 with Max-Q Design | 1FB9 103C 8783 |
|
||||
| Quadro T1000 with Max-Q Design | 1FB9 103C 8785 |
|
||||
| Quadro T1000 with Max-Q Design | 1FB9 103C 87F0 |
|
||||
| Quadro T1000 with Max-Q Design | 1FB9 1462 12BD |
|
||||
| Quadro T1000 with Max-Q Design | 1FB9 17AA 22C0 |
|
||||
| Quadro T1000 with Max-Q Design | 1FB9 17AA 22C1 |
|
||||
| NVIDIA T600 Laptop GPU | 1FBA |
|
||||
| NVIDIA T500 | 1FBB |
|
||||
| NVIDIA T1200 Laptop GPU | 1FBC |
|
||||
| NVIDIA GeForce GTX 1650 | 1FDD |
|
||||
| NVIDIA T1000 8GB | 1FF0 1028 1612 |
|
||||
| NVIDIA T1000 8GB | 1FF0 103C 1612 |
|
||||
| NVIDIA T1000 8GB | 1FF0 103C 8A80 |
|
||||
| NVIDIA T1000 8GB | 1FF0 10DE 1612 |
|
||||
| NVIDIA T1000 8GB | 1FF0 17AA 1612 |
|
||||
| NVIDIA T400 4GB | 1FF2 1028 1613 |
|
||||
| NVIDIA T400 4GB | 1FF2 103C 1613 |
|
||||
| NVIDIA T400E | 1FF2 103C 18FF |
|
||||
| NVIDIA T400 4GB | 1FF2 103C 8A80 |
|
||||
| NVIDIA T400 4GB | 1FF2 10DE 1613 |
|
||||
| NVIDIA T400E | 1FF2 10DE 18FF |
|
||||
| NVIDIA T400 4GB | 1FF2 17AA 1613 |
|
||||
| NVIDIA T400E | 1FF2 17AA 18FF |
|
||||
| Quadro T1000 | 1FF9 |
|
||||
| NVIDIA A100-SXM4-40GB | 20B0 |
|
||||
| NVIDIA A100-PG509-200 | 20B0 10DE 1450 |
|
||||
| NVIDIA A100-SXM4-80GB | 20B2 10DE 1463 |
|
||||
| NVIDIA A100-SXM4-80GB | 20B2 10DE 147F |
|
||||
| NVIDIA A100-SXM4-80GB | 20B2 10DE 1622 |
|
||||
| NVIDIA A100-SXM4-80GB | 20B2 10DE 1623 |
|
||||
| NVIDIA PG509-210 | 20B2 10DE 1625 |
|
||||
| NVIDIA A100-SXM-64GB | 20B3 10DE 14A7 |
|
||||
| NVIDIA A100-SXM-64GB | 20B3 10DE 14A8 |
|
||||
| NVIDIA A100 80GB PCIe | 20B5 10DE 1533 |
|
||||
| NVIDIA A100 80GB PCIe | 20B5 10DE 1642 |
|
||||
| NVIDIA PG506-232 | 20B6 10DE 1492 |
|
||||
| NVIDIA A30 | 20B7 10DE 1532 |
|
||||
| NVIDIA A30 | 20B7 10DE 1804 |
|
||||
| NVIDIA A30 | 20B7 10DE 1852 |
|
||||
| NVIDIA A800-SXM4-40GB | 20BD 10DE 17F4 |
|
||||
| NVIDIA A100-PCIE-40GB | 20F1 10DE 145F |
|
||||
| NVIDIA A800-SXM4-80GB | 20F3 10DE 179B |
|
||||
| NVIDIA A800-SXM4-80GB | 20F3 10DE 179C |
|
||||
| NVIDIA A800-SXM4-80GB | 20F3 10DE 179D |
|
||||
| NVIDIA A800-SXM4-80GB | 20F3 10DE 179E |
|
||||
| NVIDIA A800-SXM4-80GB | 20F3 10DE 179F |
|
||||
| NVIDIA A800-SXM4-80GB | 20F3 10DE 17A0 |
|
||||
| NVIDIA A800-SXM4-80GB | 20F3 10DE 17A1 |
|
||||
| NVIDIA A800-SXM4-80GB | 20F3 10DE 17A2 |
|
||||
| NVIDIA A800 80GB PCIe | 20F5 10DE 1799 |
|
||||
| NVIDIA A800 80GB PCIe LC | 20F5 10DE 179A |
|
||||
| NVIDIA A800 40GB Active | 20F6 1028 180A |
|
||||
| NVIDIA A800 40GB Active | 20F6 103C 180A |
|
||||
| NVIDIA A800 40GB Active | 20F6 10DE 180A |
|
||||
| NVIDIA A800 40GB Active | 20F6 17AA 180A |
|
||||
| NVIDIA AX800 | 20FD 10DE 17F8 |
|
||||
| NVIDIA GeForce GTX 1660 Ti | 2182 |
|
||||
| NVIDIA GeForce GTX 1660 | 2184 |
|
||||
| NVIDIA GeForce GTX 1650 SUPER | 2187 |
|
||||
| NVIDIA GeForce GTX 1650 | 2188 |
|
||||
| NVIDIA CMP 30HX | 2189 |
|
||||
| NVIDIA GeForce GTX 1660 Ti | 2191 |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1028 0949 |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 103C 85FB |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 103C 85FE |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 103C 86D6 |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 103C 8741 |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 103C 8744 |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 103C 878D |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 103C 87AF |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 103C 87B3 |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1043 171F |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1043 17EF |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1043 18D1 |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1414 0032 |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1462 128A |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1462 128B |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1462 12C6 |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1462 12CB |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1462 12CC |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 1462 12D9 |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 17AA 380C |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 17AA 381D |
|
||||
| NVIDIA GeForce GTX 1660 Ti with Max-Q Design | 2191 17AA 381E |
|
||||
| NVIDIA GeForce GTX 1650 Ti | 2192 |
|
||||
| NVIDIA GeForce GTX 1660 SUPER | 21C4 |
|
||||
| NVIDIA GeForce GTX 1660 Ti | 21D1 |
|
||||
| NVIDIA GeForce RTX 3090 Ti | 2203 |
|
||||
| NVIDIA GeForce RTX 3090 | 2204 |
|
||||
| NVIDIA GeForce RTX 3080 | 2206 |
|
||||
| NVIDIA GeForce RTX 3070 Ti | 2207 |
|
||||
| NVIDIA GeForce RTX 3080 Ti | 2208 |
|
||||
| NVIDIA GeForce RTX 3080 | 220A |
|
||||
| NVIDIA CMP 90HX | 220D |
|
||||
| NVIDIA GeForce RTX 3080 | 2216 |
|
||||
| NVIDIA RTX A6000 | 2230 1028 1459 |
|
||||
| NVIDIA RTX A6000 | 2230 103C 1459 |
|
||||
| NVIDIA RTX A6000 | 2230 10DE 1459 |
|
||||
| NVIDIA RTX A6000 | 2230 17AA 1459 |
|
||||
| NVIDIA RTX A5000 | 2231 1028 147E |
|
||||
| NVIDIA RTX A5000 | 2231 103C 147E |
|
||||
| NVIDIA RTX A5000 | 2231 10DE 147E |
|
||||
| NVIDIA RTX A5000 | 2231 17AA 147E |
|
||||
| NVIDIA RTX A4500 | 2232 1028 163C |
|
||||
| NVIDIA RTX A4500 | 2232 103C 163C |
|
||||
| NVIDIA RTX A4500 | 2232 10DE 163C |
|
||||
| NVIDIA RTX A4500 | 2232 17AA 163C |
|
||||
| NVIDIA RTX A5500 | 2233 1028 165A |
|
||||
| NVIDIA RTX A5500 | 2233 103C 165A |
|
||||
| NVIDIA RTX A5500 | 2233 10DE 165A |
|
||||
| NVIDIA RTX A5500 | 2233 17AA 165A |
|
||||
| NVIDIA A40 | 2235 10DE 145A |
|
||||
| NVIDIA A10 | 2236 10DE 1482 |
|
||||
| NVIDIA A10G | 2237 10DE 152F |
|
||||
| NVIDIA A10M | 2238 10DE 1677 |
|
||||
| NVIDIA H100 NVL | 2321 10DE 1839 |
|
||||
| NVIDIA H800 PCIe | 2322 10DE 17A4 |
|
||||
| NVIDIA H800 | 2324 10DE 17A6 |
|
||||
| NVIDIA H800 | 2324 10DE 17A8 |
|
||||
| NVIDIA H20 | 2329 10DE 198B |
|
||||
| NVIDIA H20 | 2329 10DE 198C |
|
||||
| NVIDIA H20-3e | 232C 10DE 2063 |
|
||||
| NVIDIA H100 80GB HBM3 | 2330 10DE 16C0 |
|
||||
| NVIDIA H100 80GB HBM3 | 2330 10DE 16C1 |
|
||||
| NVIDIA H100 PCIe | 2331 10DE 1626 |
|
||||
| NVIDIA H200 | 2335 10DE 18BE |
|
||||
| NVIDIA H200 | 2335 10DE 18BF |
|
||||
| NVIDIA H100 | 2339 10DE 17FC |
|
||||
| NVIDIA H800 NVL | 233A 10DE 183A |
|
||||
| NVIDIA H200 NVL | 233B 10DE 1996 |
|
||||
| NVIDIA GH200 120GB | 2342 10DE 16EB |
|
||||
| NVIDIA GH200 120GB | 2342 10DE 1805 |
|
||||
| NVIDIA GH200 480GB | 2342 10DE 1809 |
|
||||
| NVIDIA GH200 144G HBM3e | 2348 10DE 18D2 |
|
||||
| NVIDIA GeForce RTX 3060 Ti | 2414 |
|
||||
| NVIDIA GeForce RTX 3080 Ti Laptop GPU | 2420 |
|
||||
| NVIDIA RTX A5500 Laptop GPU | 2438 |
|
||||
| NVIDIA GeForce RTX 3080 Ti Laptop GPU | 2460 |
|
||||
| NVIDIA GeForce RTX 3070 Ti | 2482 |
|
||||
| NVIDIA GeForce RTX 3070 | 2484 |
|
||||
| NVIDIA GeForce RTX 3060 Ti | 2486 |
|
||||
| NVIDIA GeForce RTX 3060 | 2487 |
|
||||
| NVIDIA GeForce RTX 3070 | 2488 |
|
||||
| NVIDIA GeForce RTX 3060 Ti | 2489 |
|
||||
| NVIDIA CMP 70HX | 248A |
|
||||
| NVIDIA GeForce RTX 3080 Laptop GPU | 249C |
|
||||
| NVIDIA GeForce RTX 3060 Laptop GPU | 249C 1D05 1194 |
|
||||
| NVIDIA GeForce RTX 3070 Laptop GPU | 249D |
|
||||
| NVIDIA GeForce RTX 3070 Ti Laptop GPU | 24A0 |
|
||||
| NVIDIA GeForce RTX 3060 Laptop GPU | 24A0 1D05 1192 |
|
||||
| NVIDIA RTX A4000 | 24B0 1028 14AD |
|
||||
| NVIDIA RTX A4000 | 24B0 103C 14AD |
|
||||
| NVIDIA RTX A4000 | 24B0 10DE 14AD |
|
||||
| NVIDIA RTX A4000 | 24B0 17AA 14AD |
|
||||
| NVIDIA RTX A4000H | 24B1 10DE 1658 |
|
||||
| NVIDIA RTX A5000 Laptop GPU | 24B6 |
|
||||
| NVIDIA RTX A4000 Laptop GPU | 24B7 |
|
||||
| NVIDIA RTX A3000 Laptop GPU | 24B8 |
|
||||
| NVIDIA RTX A3000 12GB Laptop GPU | 24B9 |
|
||||
| NVIDIA RTX A4500 Laptop GPU | 24BA |
|
||||
| NVIDIA RTX A3000 12GB Laptop GPU | 24BB |
|
||||
| NVIDIA GeForce RTX 3060 | 24C7 |
|
||||
| NVIDIA GeForce RTX 3060 Ti | 24C9 |
|
||||
| NVIDIA GeForce RTX 3080 Laptop GPU | 24DC |
|
||||
| NVIDIA GeForce RTX 3070 Laptop GPU | 24DD |
|
||||
| NVIDIA GeForce RTX 3070 Ti Laptop GPU | 24E0 |
|
||||
| NVIDIA RTX A4500 Embedded GPU | 24FA |
|
||||
| NVIDIA GeForce RTX 3060 | 2503 |
|
||||
| NVIDIA GeForce RTX 3060 | 2504 |
|
||||
| NVIDIA GeForce RTX 3050 | 2507 |
|
||||
| NVIDIA GeForce RTX 3050 OEM | 2508 |
|
||||
| NVIDIA GeForce RTX 3060 Laptop GPU | 2520 |
|
||||
| NVIDIA GeForce RTX 3060 Laptop GPU | 2521 |
|
||||
| NVIDIA GeForce RTX 3050 Ti Laptop GPU | 2523 |
|
||||
| NVIDIA RTX A2000 | 2531 1028 151D |
|
||||
| NVIDIA RTX A2000 | 2531 103C 151D |
|
||||
| NVIDIA RTX A2000 | 2531 10DE 151D |
|
||||
| NVIDIA RTX A2000 | 2531 17AA 151D |
|
||||
| NVIDIA GeForce RTX 3060 | 2544 |
|
||||
| NVIDIA GeForce RTX 3060 Laptop GPU | 2560 |
|
||||
| NVIDIA GeForce RTX 3050 Ti Laptop GPU | 2563 |
|
||||
| NVIDIA RTX A2000 12GB | 2571 1028 1611 |
|
||||
| NVIDIA RTX A2000 12GB | 2571 103C 1611 |
|
||||
| NVIDIA RTX A2000 12GB | 2571 10DE 1611 |
|
||||
| NVIDIA RTX A2000 12GB | 2571 17AA 1611 |
|
||||
| NVIDIA GeForce RTX 3050 | 2582 |
|
||||
| NVIDIA GeForce RTX 3050 | 2584 |
|
||||
| NVIDIA GeForce RTX 3050 Ti Laptop GPU | 25A0 |
|
||||
| NVIDIA GeForce RTX 3050Ti Laptop GPU | 25A0 103C 8928 |
|
||||
| NVIDIA GeForce RTX 3050Ti Laptop GPU | 25A0 103C 89F9 |
|
||||
| NVIDIA GeForce RTX 3060 Laptop GPU | 25A0 1D05 1196 |
|
||||
| NVIDIA GeForce RTX 3050 Laptop GPU | 25A2 |
|
||||
| NVIDIA GeForce RTX 3050 Ti Laptop GPU | 25A2 1028 0BAF |
|
||||
| NVIDIA GeForce RTX 3060 Laptop GPU | 25A2 1D05 1195 |
|
||||
| NVIDIA GeForce RTX 3050 Laptop GPU | 25A5 |
|
||||
| NVIDIA GeForce MX570 | 25A6 |
|
||||
| NVIDIA GeForce RTX 2050 | 25A7 |
|
||||
| NVIDIA GeForce RTX 2050 | 25A9 |
|
||||
| NVIDIA GeForce MX570 A | 25AA |
|
||||
| NVIDIA GeForce RTX 3050 4GB Laptop GPU | 25AB |
|
||||
| NVIDIA GeForce RTX 3050 6GB Laptop GPU | 25AC |
|
||||
| NVIDIA GeForce RTX 2050 | 25AD |
|
||||
| NVIDIA RTX A1000 | 25B0 1028 1878 |
|
||||
| NVIDIA RTX A1000 | 25B0 103C 1878 |
|
||||
| NVIDIA RTX A1000 | 25B0 103C 8D96 |
|
||||
| NVIDIA RTX A1000 | 25B0 10DE 1878 |
|
||||
| NVIDIA RTX A1000 | 25B0 17AA 1878 |
|
||||
| NVIDIA RTX A400 | 25B2 1028 1879 |
|
||||
| NVIDIA RTX A400 | 25B2 103C 1879 |
|
||||
| NVIDIA RTX A400 | 25B2 103C 8D95 |
|
||||
| NVIDIA RTX A400 | 25B2 10DE 1879 |
|
||||
| NVIDIA RTX A400 | 25B2 17AA 1879 |
|
||||
| NVIDIA A16 | 25B6 10DE 14A9 |
|
||||
| NVIDIA A2 | 25B6 10DE 157E |
|
||||
| NVIDIA RTX A2000 Laptop GPU | 25B8 |
|
||||
| NVIDIA RTX A1000 Laptop GPU | 25B9 |
|
||||
| NVIDIA RTX A2000 8GB Laptop GPU | 25BA |
|
||||
| NVIDIA RTX A500 Laptop GPU | 25BB |
|
||||
| NVIDIA RTX A1000 6GB Laptop GPU | 25BC |
|
||||
| NVIDIA RTX A500 Laptop GPU | 25BD |
|
||||
| NVIDIA GeForce RTX 3050 Ti Laptop GPU | 25E0 |
|
||||
| NVIDIA GeForce RTX 3050 Laptop GPU | 25E2 |
|
||||
| NVIDIA GeForce RTX 3050 Laptop GPU | 25E5 |
|
||||
| NVIDIA GeForce RTX 3050 6GB Laptop GPU | 25EC |
|
||||
| NVIDIA GeForce RTX 2050 | 25ED |
|
||||
| NVIDIA RTX A1000 Embedded GPU | 25F9 |
|
||||
| NVIDIA RTX A2000 Embedded GPU | 25FA |
|
||||
| NVIDIA RTX A500 Embedded GPU | 25FB |
|
||||
| NVIDIA GeForce RTX 4090 | 2684 |
|
||||
| NVIDIA GeForce RTX 4090 D | 2685 |
|
||||
| NVIDIA GeForce RTX 4070 Ti SUPER | 2689 |
|
||||
| NVIDIA RTX 6000 Ada Generation | 26B1 1028 16A1 |
|
||||
| NVIDIA RTX 6000 Ada Generation | 26B1 103C 16A1 |
|
||||
| NVIDIA RTX 6000 Ada Generation | 26B1 10DE 16A1 |
|
||||
| NVIDIA RTX 6000 Ada Generation | 26B1 17AA 16A1 |
|
||||
| NVIDIA RTX 5000 Ada Generation | 26B2 1028 17FA |
|
||||
| NVIDIA RTX 5000 Ada Generation | 26B2 103C 17FA |
|
||||
| NVIDIA RTX 5000 Ada Generation | 26B2 10DE 17FA |
|
||||
| NVIDIA RTX 5000 Ada Generation | 26B2 17AA 17FA |
|
||||
| NVIDIA RTX 5880 Ada Generation | 26B3 1028 1934 |
|
||||
| NVIDIA RTX 5880 Ada Generation | 26B3 103C 1934 |
|
||||
| NVIDIA RTX 5880 Ada Generation | 26B3 10DE 1934 |
|
||||
| NVIDIA RTX 5880 Ada Generation | 26B3 17AA 1934 |
|
||||
| NVIDIA L40 | 26B5 10DE 169D |
|
||||
| NVIDIA L40 | 26B5 10DE 17DA |
|
||||
| NVIDIA L40S | 26B9 10DE 1851 |
|
||||
| NVIDIA L40S | 26B9 10DE 18CF |
|
||||
| NVIDIA L20 | 26BA 10DE 1957 |
|
||||
| NVIDIA L20 | 26BA 10DE 1990 |
|
||||
| NVIDIA GeForce RTX 4080 SUPER | 2702 |
|
||||
| NVIDIA GeForce RTX 4080 | 2704 |
|
||||
| NVIDIA GeForce RTX 4070 Ti SUPER | 2705 |
|
||||
| NVIDIA GeForce RTX 4070 | 2709 |
|
||||
| NVIDIA GeForce RTX 4090 Laptop GPU | 2717 |
|
||||
| NVIDIA RTX 5000 Ada Generation Laptop GPU | 2730 |
|
||||
| NVIDIA GeForce RTX 4090 Laptop GPU | 2757 |
|
||||
| NVIDIA RTX 5000 Ada Generation Embedded GPU | 2770 |
|
||||
| NVIDIA GeForce RTX 4070 Ti | 2782 |
|
||||
| NVIDIA GeForce RTX 4070 SUPER | 2783 |
|
||||
| NVIDIA GeForce RTX 4070 | 2786 |
|
||||
| NVIDIA GeForce RTX 4060 Ti | 2788 |
|
||||
| NVIDIA GeForce RTX 4080 Laptop GPU | 27A0 |
|
||||
| NVIDIA RTX 4000 SFF Ada Generation | 27B0 1028 16FA |
|
||||
| NVIDIA RTX 4000 SFF Ada Generation | 27B0 103C 16FA |
|
||||
| NVIDIA RTX 4000 SFF Ada Generation | 27B0 10DE 16FA |
|
||||
| NVIDIA RTX 4000 SFF Ada Generation | 27B0 17AA 16FA |
|
||||
| NVIDIA RTX 4500 Ada Generation | 27B1 1028 180C |
|
||||
| NVIDIA RTX 4500 Ada Generation | 27B1 103C 180C |
|
||||
| NVIDIA RTX 4500 Ada Generation | 27B1 10DE 180C |
|
||||
| NVIDIA RTX 4500 Ada Generation | 27B1 17AA 180C |
|
||||
| NVIDIA RTX 4000 Ada Generation | 27B2 1028 181B |
|
||||
| NVIDIA RTX 4000 Ada Generation | 27B2 103C 181B |
|
||||
| NVIDIA RTX 4000 Ada Generation | 27B2 10DE 181B |
|
||||
| NVIDIA RTX 4000 Ada Generation | 27B2 17AA 181B |
|
||||
| NVIDIA L2 | 27B6 10DE 1933 |
|
||||
| NVIDIA L4 | 27B8 10DE 16CA |
|
||||
| NVIDIA L4 | 27B8 10DE 16EE |
|
||||
| NVIDIA RTX 4000 Ada Generation Laptop GPU | 27BA |
|
||||
| NVIDIA RTX 3500 Ada Generation Laptop GPU | 27BB |
|
||||
| NVIDIA GeForce RTX 4080 Laptop GPU | 27E0 |
|
||||
| NVIDIA RTX 3500 Ada Generation Embedded GPU | 27FB |
|
||||
| NVIDIA GeForce RTX 4060 Ti | 2803 |
|
||||
| NVIDIA GeForce RTX 4060 Ti | 2805 |
|
||||
| NVIDIA GeForce RTX 4060 | 2808 |
|
||||
| NVIDIA GeForce RTX 4070 Laptop GPU | 2820 |
|
||||
| NVIDIA GeForce RTX 3050 A Laptop GPU | 2822 |
|
||||
| NVIDIA RTX 3000 Ada Generation Laptop GPU | 2838 |
|
||||
| NVIDIA GeForce RTX 4070 Laptop GPU | 2860 |
|
||||
| NVIDIA GeForce RTX 4060 | 2882 |
|
||||
| NVIDIA GeForce RTX 4060 Laptop GPU | 28A0 |
|
||||
| NVIDIA GeForce RTX 4050 Laptop GPU | 28A1 |
|
||||
| NVIDIA GeForce RTX 3050 A Laptop GPU | 28A3 |
|
||||
| NVIDIA RTX 2000 Ada Generation | 28B0 1028 1870 |
|
||||
| NVIDIA RTX 2000 Ada Generation | 28B0 103C 1870 |
|
||||
| NVIDIA RTX 2000E Ada Generation | 28B0 103C 1871 |
|
||||
| NVIDIA RTX 2000 Ada Generation | 28B0 10DE 1870 |
|
||||
| NVIDIA RTX 2000E Ada Generation | 28B0 10DE 1871 |
|
||||
| NVIDIA RTX 2000 Ada Generation | 28B0 17AA 1870 |
|
||||
| NVIDIA RTX 2000E Ada Generation | 28B0 17AA 1871 |
|
||||
| NVIDIA RTX 2000 Ada Generation Laptop GPU | 28B8 |
|
||||
| NVIDIA RTX 1000 Ada Generation Laptop GPU | 28B9 |
|
||||
| NVIDIA RTX 500 Ada Generation Laptop GPU | 28BA |
|
||||
| NVIDIA RTX 500 Ada Generation Laptop GPU | 28BB |
|
||||
| NVIDIA GeForce RTX 4060 Laptop GPU | 28E0 |
|
||||
| NVIDIA GeForce RTX 4050 Laptop GPU | 28E1 |
|
||||
| NVIDIA GeForce RTX 3050 A Laptop GPU | 28E3 |
|
||||
| NVIDIA RTX 2000 Ada Generation Embedded GPU | 28F8 |
|
||||
| NVIDIA B200 | 2901 10DE 1999 |
|
||||
| NVIDIA B200 | 2901 10DE 199B |
|
||||
| NVIDIA B200 | 2901 10DE 20DA |
|
||||
| NVIDIA GB200 | 2941 10DE 2046 |
|
||||
| NVIDIA GB200 | 2941 10DE 20CA |
|
||||
| NVIDIA GB200 | 2941 10DE 20D5 |
|
||||
| NVIDIA GB200 | 2941 10DE 21C9 |
|
||||
| NVIDIA GB200 | 2941 10DE 21CA |
|
||||
| NVIDIA GeForce RTX 5090 | 2B85 |
|
||||
| NVIDIA GeForce RTX 5090 D | 2B87 |
|
||||
| NVIDIA RTX PRO 6000 Blackwell Workstation Edition | 2BB1 1028 204B |
|
||||
| NVIDIA RTX PRO 6000 Blackwell Workstation Edition | 2BB1 103C 204B |
|
||||
| NVIDIA RTX PRO 6000 Blackwell Workstation Edition | 2BB1 10DE 204B |
|
||||
| NVIDIA RTX PRO 6000 Blackwell Workstation Edition | 2BB1 17AA 204B |
|
||||
| NVIDIA RTX PRO 5000 Blackwell | 2BB3 1028 204D |
|
||||
| NVIDIA RTX PRO 5000 Blackwell | 2BB3 103C 204D |
|
||||
| NVIDIA RTX PRO 5000 Blackwell | 2BB3 10DE 204D |
|
||||
| NVIDIA RTX PRO 5000 Blackwell | 2BB3 17AA 204D |
|
||||
| NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition | 2BB4 1028 204C |
|
||||
| NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition | 2BB4 103C 204C |
|
||||
| NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition | 2BB4 10DE 204C |
|
||||
| NVIDIA RTX PRO 6000 Blackwell Max-Q Workstation Edition | 2BB4 17AA 204C |
|
||||
| NVIDIA RTX PRO 6000 Blackwell Server Edition | 2BB5 10DE 204E |
|
||||
| NVIDIA GeForce RTX 5080 | 2C02 |
|
||||
| NVIDIA GeForce RTX 5070 Ti | 2C05 |
|
||||
| NVIDIA GeForce RTX 5090 Laptop GPU | 2C18 |
|
||||
| NVIDIA GeForce RTX 5080 Laptop GPU | 2C19 |
|
||||
| NVIDIA RTX PRO 5000 Blackwell Generation Laptop GPU | 2C38 |
|
||||
| NVIDIA RTX PRO 4000 Blackwell Generation Laptop GPU | 2C39 |
|
||||
| NVIDIA GeForce RTX 5090 Laptop GPU | 2C58 |
|
||||
| NVIDIA GeForce RTX 5080 Laptop GPU | 2C59 |
|
||||
| NVIDIA GeForce RTX 5060 Ti | 2D04 |
|
||||
| NVIDIA GeForce RTX 5060 | 2D05 |
|
||||
| NVIDIA GeForce RTX 5070 Laptop GPU | 2D18 |
|
||||
| NVIDIA GeForce RTX 5060 Laptop GPU | 2D19 |
|
||||
| NVIDIA RTX PRO 2000 Blackwell Generation Laptop GPU | 2D39 |
|
||||
| NVIDIA GeForce RTX 5070 Laptop GPU | 2D58 |
|
||||
| NVIDIA GeForce RTX 5060 Laptop GPU | 2D59 |
|
||||
| NVIDIA RTX PRO 1000 Blackwell Generation Laptop GPU | 2DB8 |
|
||||
| NVIDIA RTX PRO 500 Blackwell Generation Laptop GPU | 2DB9 |
|
||||
| NVIDIA GeForce RTX 5070 | 2F04 |
|
||||
| NVIDIA GeForce RTX 5070 Ti Laptop GPU | 2F18 |
|
||||
| NVIDIA RTX PRO 3000 Blackwell Generation Laptop GPU | 2F38 |
|
||||
| NVIDIA GeForce RTX 5070 Ti Laptop GPU | 2F58 |
|
||||
2775
commitFile.txt
2775
commitFile.txt
File diff suppressed because it is too large
Load Diff
@@ -8,7 +8,7 @@
|
||||
# NV_KERNEL_SOURCES : The root of the kernel source tree.
|
||||
# NV_KERNEL_OUTPUT : The kernel's output tree.
|
||||
# NV_KERNEL_MODULES : A whitespace-separated list of modules to build.
|
||||
# ARCH : The target CPU architecture: x86_64|arm64|powerpc
|
||||
# ARCH : The target CPU architecture: x86_64|arm64
|
||||
#
|
||||
# Kbuild provides the variables:
|
||||
#
|
||||
@@ -57,71 +57,106 @@ ifeq ($(NV_UNDEF_BEHAVIOR_SANITIZER),1)
|
||||
UBSAN_SANITIZE := y
|
||||
endif
|
||||
|
||||
#
|
||||
# Command to create a symbolic link, explicitly resolving the symlink target
|
||||
# to an absolute path to abstract away the difference between Linux < 6.13,
|
||||
# where the CWD is the Linux kernel source tree for Kbuild extmod builds, and
|
||||
# Linux >= 6.13, where the CWD is the external module source tree.
|
||||
#
|
||||
# This is used to create the nv*-kernel.o -> nv*-kernel.o_binary symlinks for
|
||||
# kernel modules which use precompiled binary object files.
|
||||
#
|
||||
|
||||
quiet_cmd_symlink = SYMLINK $@
|
||||
cmd_symlink = ln -sf $(abspath $<) $@
|
||||
|
||||
|
||||
$(foreach _module, $(NV_KERNEL_MODULES), \
|
||||
$(eval include $(src)/$(_module)/$(_module).Kbuild))
|
||||
|
||||
|
||||
#
|
||||
# Define CFLAGS that apply to all the NVIDIA kernel modules. EXTRA_CFLAGS
|
||||
# is deprecated since 2.6.24 in favor of ccflags-y, but we need to support
|
||||
# older kernels which do not have ccflags-y. Newer kernels append
|
||||
# $(EXTRA_CFLAGS) to ccflags-y for compatibility.
|
||||
#
|
||||
ccflags-y += -I$(src)/common/inc
|
||||
ccflags-y += -I$(src)
|
||||
ccflags-y += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-format-extra-args
|
||||
ccflags-y += -D__KERNEL__ -DMODULE -DNVRM
|
||||
ccflags-y += -DNV_VERSION_STRING=\"580.00\"
|
||||
|
||||
EXTRA_CFLAGS += -I$(src)/common/inc
|
||||
EXTRA_CFLAGS += -I$(src)
|
||||
EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args
|
||||
EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
|
||||
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"540.1.0\"
|
||||
# Include and link Tegra out-of-tree modules.
|
||||
ifneq ($(wildcard /usr/src/nvidia/nvidia-oot),)
|
||||
SYSSRCNVOOT ?= /usr/src/nvidia/nvidia-oot
|
||||
endif
|
||||
|
||||
ifneq ($(SYSSRCHOST1X),)
|
||||
EXTRA_CFLAGS += -I$(SYSSRCHOST1X)
|
||||
ccflags-y += -I$(SYSSRCHOST1X)
|
||||
endif
|
||||
|
||||
EXTRA_CFLAGS += -Wno-unused-function
|
||||
ifneq ($(SYSSRCNVOOT),)
|
||||
ccflags-y += -I$(SYSSRCNVOOT)/include
|
||||
KBUILD_EXTRA_SYMBOLS = $(SYSSRCNVOOT)/Module.symvers
|
||||
endif
|
||||
|
||||
# Some Android kernels prohibit driver use of filesystem functions like
|
||||
# filp_open() and kernel_read(). Disable the NV_FILESYSTEM_ACCESS_AVAILABLE
|
||||
# functionality that uses those functions when building for Android.
|
||||
|
||||
PLATFORM_IS_ANDROID ?= 0
|
||||
|
||||
ifeq ($(PLATFORM_IS_ANDROID),1)
|
||||
ccflags-y += -DNV_FILESYSTEM_ACCESS_AVAILABLE=0
|
||||
else
|
||||
ccflags-y += -DNV_FILESYSTEM_ACCESS_AVAILABLE=1
|
||||
endif
|
||||
|
||||
ccflags-y += -Wno-unused-function
|
||||
|
||||
ifneq ($(NV_BUILD_TYPE),debug)
|
||||
EXTRA_CFLAGS += -Wuninitialized
|
||||
ccflags-y += -Wuninitialized
|
||||
endif
|
||||
|
||||
EXTRA_CFLAGS += -fno-strict-aliasing
|
||||
ccflags-y += -fno-strict-aliasing
|
||||
|
||||
ifeq ($(ARCH),arm64)
|
||||
EXTRA_CFLAGS += -mstrict-align
|
||||
ccflags-y += -mstrict-align
|
||||
endif
|
||||
|
||||
ifeq ($(NV_BUILD_TYPE),debug)
|
||||
EXTRA_CFLAGS += -g
|
||||
ccflags-y += -g
|
||||
endif
|
||||
|
||||
EXTRA_CFLAGS += -ffreestanding
|
||||
ccflags-y += -ffreestanding
|
||||
|
||||
ifeq ($(ARCH),arm64)
|
||||
EXTRA_CFLAGS += -mgeneral-regs-only -march=armv8-a
|
||||
EXTRA_CFLAGS += $(call cc-option,-mno-outline-atomics,)
|
||||
ccflags-y += -mgeneral-regs-only -march=armv8-a
|
||||
ccflags-y += $(call cc-option,-mno-outline-atomics,)
|
||||
endif
|
||||
|
||||
ifeq ($(ARCH),x86_64)
|
||||
EXTRA_CFLAGS += -mno-red-zone -mcmodel=kernel
|
||||
ccflags-y += -mno-red-zone -mcmodel=kernel
|
||||
endif
|
||||
|
||||
ifeq ($(ARCH),powerpc)
|
||||
EXTRA_CFLAGS += -mlittle-endian -mno-strict-align -mno-altivec
|
||||
endif
|
||||
|
||||
EXTRA_CFLAGS +=
|
||||
EXTRA_CFLAGS += $(call cc-option,-Werror=undef,)
|
||||
EXTRA_CFLAGS += -DNV_SPECTRE_V2=$(NV_SPECTRE_V2)
|
||||
EXTRA_CFLAGS += -DNV_KERNEL_INTERFACE_LAYER
|
||||
ccflags-y +=
|
||||
ccflags-y += $(call cc-option,-Werror=undef,)
|
||||
ccflags-y += -DNV_SPECTRE_V2=$(NV_SPECTRE_V2)
|
||||
ccflags-y += -DNV_KERNEL_INTERFACE_LAYER
|
||||
|
||||
#
|
||||
# Detect SGI UV systems and apply system-specific optimizations.
|
||||
#
|
||||
|
||||
ifneq ($(wildcard /proc/sgi_uv),)
|
||||
EXTRA_CFLAGS += -DNV_CONFIG_X86_UV
|
||||
ccflags-y += -DNV_CONFIG_X86_UV
|
||||
endif
|
||||
|
||||
ifdef VGX_FORCE_VFIO_PCI_CORE
|
||||
ccflags-y += -DNV_VGPU_FORCE_VFIO_PCI_CORE
|
||||
endif
|
||||
|
||||
WARNINGS_AS_ERRORS ?=
|
||||
ifeq ($(WARNINGS_AS_ERRORS),1)
|
||||
ccflags-y += -Werror
|
||||
else
|
||||
ccflags-y += -Wno-error
|
||||
endif
|
||||
|
||||
#
|
||||
# The conftest.sh script tests various aspects of the target kernel.
|
||||
@@ -147,7 +182,12 @@ NV_CONFTEST_CMD := /bin/sh $(NV_CONFTEST_SCRIPT) \
|
||||
|
||||
NV_CFLAGS_FROM_CONFTEST := $(shell $(NV_CONFTEST_CMD) build_cflags)
|
||||
|
||||
NV_CONFTEST_CFLAGS = $(NV_CFLAGS_FROM_CONFTEST) $(EXTRA_CFLAGS) -fno-pie
|
||||
NV_CONFTEST_CFLAGS = $(NV_CFLAGS_FROM_CONFTEST) $(ccflags-y) -fno-pie
|
||||
NV_CONFTEST_CFLAGS += $(filter -std=%,$(KBUILD_CFLAGS))
|
||||
NV_CONFTEST_CFLAGS += $(call cc-disable-warning,pointer-sign)
|
||||
NV_CONFTEST_CFLAGS += $(call cc-option,-fshort-wchar,)
|
||||
NV_CONFTEST_CFLAGS += $(call cc-option,-Werror=incompatible-pointer-types,)
|
||||
NV_CONFTEST_CFLAGS += -Wno-error
|
||||
|
||||
NV_CONFTEST_COMPILE_TEST_HEADERS := $(obj)/conftest/macros.h
|
||||
NV_CONFTEST_COMPILE_TEST_HEADERS += $(obj)/conftest/functions.h
|
||||
@@ -207,105 +247,7 @@ $(obj)/conftest/patches.h: $(NV_CONFTEST_SCRIPT)
|
||||
@mkdir -p $(obj)/conftest
|
||||
@$(NV_CONFTEST_CMD) patch_check > $@
|
||||
|
||||
|
||||
# Each of these headers is checked for presence with a test #include; a
|
||||
# corresponding #define will be generated in conftest/headers.h.
|
||||
NV_HEADER_PRESENCE_TESTS = \
|
||||
asm/system.h \
|
||||
drm/drmP.h \
|
||||
drm/drm_aperture.h \
|
||||
drm/drm_auth.h \
|
||||
drm/drm_gem.h \
|
||||
drm/drm_crtc.h \
|
||||
drm/drm_color_mgmt.h \
|
||||
drm/drm_atomic.h \
|
||||
drm/drm_atomic_helper.h \
|
||||
drm/drm_atomic_state_helper.h \
|
||||
drm/drm_encoder.h \
|
||||
drm/drm_atomic_uapi.h \
|
||||
drm/drm_drv.h \
|
||||
drm/drm_fbdev_generic.h \
|
||||
drm/drm_framebuffer.h \
|
||||
drm/drm_connector.h \
|
||||
drm/drm_probe_helper.h \
|
||||
drm/drm_blend.h \
|
||||
drm/drm_fourcc.h \
|
||||
drm/drm_prime.h \
|
||||
drm/drm_plane.h \
|
||||
drm/drm_vblank.h \
|
||||
drm/drm_file.h \
|
||||
drm/drm_ioctl.h \
|
||||
drm/drm_device.h \
|
||||
drm/drm_mode_config.h \
|
||||
drm/drm_modeset_lock.h \
|
||||
dt-bindings/interconnect/tegra_icc_id.h \
|
||||
generated/autoconf.h \
|
||||
generated/compile.h \
|
||||
generated/utsrelease.h \
|
||||
linux/efi.h \
|
||||
linux/kconfig.h \
|
||||
linux/platform/tegra/mc_utils.h \
|
||||
linux/printk.h \
|
||||
linux/ratelimit.h \
|
||||
linux/prio_tree.h \
|
||||
linux/log2.h \
|
||||
linux/of.h \
|
||||
linux/bug.h \
|
||||
linux/sched.h \
|
||||
linux/sched/mm.h \
|
||||
linux/sched/signal.h \
|
||||
linux/sched/task.h \
|
||||
linux/sched/task_stack.h \
|
||||
xen/ioemu.h \
|
||||
linux/fence.h \
|
||||
linux/dma-fence.h \
|
||||
linux/dma-resv.h \
|
||||
soc/tegra/chip-id.h \
|
||||
soc/tegra/fuse.h \
|
||||
soc/tegra/tegra_bpmp.h \
|
||||
video/nv_internal.h \
|
||||
linux/platform/tegra/dce/dce-client-ipc.h \
|
||||
linux/nvhost.h \
|
||||
linux/nvhost_t194.h \
|
||||
linux/host1x-next.h \
|
||||
asm/book3s/64/hash-64k.h \
|
||||
asm/set_memory.h \
|
||||
asm/prom.h \
|
||||
asm/powernv.h \
|
||||
linux/atomic.h \
|
||||
asm/barrier.h \
|
||||
asm/opal-api.h \
|
||||
sound/hdaudio.h \
|
||||
asm/pgtable_types.h \
|
||||
asm/page.h \
|
||||
linux/stringhash.h \
|
||||
linux/dma-map-ops.h \
|
||||
rdma/peer_mem.h \
|
||||
sound/hda_codec.h \
|
||||
linux/dma-buf.h \
|
||||
linux/time.h \
|
||||
linux/platform_device.h \
|
||||
linux/mutex.h \
|
||||
linux/reset.h \
|
||||
linux/of_platform.h \
|
||||
linux/of_device.h \
|
||||
linux/of_gpio.h \
|
||||
linux/gpio.h \
|
||||
linux/gpio/consumer.h \
|
||||
linux/interconnect.h \
|
||||
linux/pm_runtime.h \
|
||||
linux/clk.h \
|
||||
linux/clk-provider.h \
|
||||
linux/ioasid.h \
|
||||
linux/stdarg.h \
|
||||
linux/iosys-map.h \
|
||||
asm/coco.h \
|
||||
linux/vfio_pci_core.h \
|
||||
linux/mdev.h \
|
||||
soc/tegra/bpmp-abi.h \
|
||||
soc/tegra/bpmp.h \
|
||||
linux/sync_file.h \
|
||||
linux/cc_platform.h
|
||||
include $(src)/header-presence-tests.mk
|
||||
|
||||
# Filename to store the define for the header in $(1); this is only consumed by
|
||||
# the rule below that concatenates all of these together.
|
||||
@@ -28,7 +28,7 @@ else
|
||||
else
|
||||
KERNEL_UNAME ?= $(shell uname -r)
|
||||
KERNEL_MODLIB := /lib/modules/$(KERNEL_UNAME)
|
||||
KERNEL_SOURCES := $(shell test -d $(KERNEL_MODLIB)/source && echo $(KERNEL_MODLIB)/source || echo $(KERNEL_MODLIB)/build)
|
||||
KERNEL_SOURCES := $(shell ((test -d $(KERNEL_MODLIB)/source && echo $(KERNEL_MODLIB)/source) || (test -d $(KERNEL_MODLIB)/build/source && echo $(KERNEL_MODLIB)/build/source)) || echo $(KERNEL_MODLIB)/build)
|
||||
endif
|
||||
|
||||
KERNEL_OUTPUT := $(KERNEL_SOURCES)
|
||||
@@ -42,27 +42,83 @@ else
|
||||
else
|
||||
KERNEL_UNAME ?= $(shell uname -r)
|
||||
KERNEL_MODLIB := /lib/modules/$(KERNEL_UNAME)
|
||||
ifeq ($(KERNEL_SOURCES), $(KERNEL_MODLIB)/source)
|
||||
# $(filter patter...,text) - Returns all whitespace-separated words in text that
|
||||
# do match any of the pattern words, removing any words that do not match.
|
||||
# Set the KERNEL_OUTPUT only if either $(KERNEL_MODLIB)/source or
|
||||
# $(KERNEL_MODLIB)/build/source path matches the KERNEL_SOURCES.
|
||||
ifneq ($(filter $(KERNEL_SOURCES),$(KERNEL_MODLIB)/source $(KERNEL_MODLIB)/build/source),)
|
||||
KERNEL_OUTPUT := $(KERNEL_MODLIB)/build
|
||||
KBUILD_PARAMS := KBUILD_OUTPUT=$(KERNEL_OUTPUT)
|
||||
endif
|
||||
endif
|
||||
|
||||
# If CC hasn't been set explicitly, check the value of CONFIG_CC_VERSION_TEXT.
|
||||
# Look for the compiler specified there, and use it by default, if found.
|
||||
ifeq ($(origin CC),default)
|
||||
cc_version_text=$(firstword $(shell . $(KERNEL_OUTPUT)/.config; \
|
||||
echo "$$CONFIG_CC_VERSION_TEXT"))
|
||||
|
||||
ifneq ($(cc_version_text),)
|
||||
ifeq ($(shell command -v $(cc_version_text)),)
|
||||
$(warning WARNING: Unable to locate the compiler $(cc_version_text) \
|
||||
from CONFIG_CC_VERSION_TEXT in the kernel configuration.)
|
||||
else
|
||||
CC=$(cc_version_text)
|
||||
endif
|
||||
endif
|
||||
endif
|
||||
|
||||
CC ?= cc
|
||||
LD ?= ld
|
||||
OBJDUMP ?= objdump
|
||||
AWK ?= awk
|
||||
# Bake the following awk program in a string. The program is needed to add C++
|
||||
# to the languages excluded from BTF generation.
|
||||
#
|
||||
# Also, unconditionally return success (0) from the awk program, rather than
|
||||
# propagating pahole's return status (with 'exit system(pahole_cmd)'), to
|
||||
# workaround an DW_TAG_rvalue_reference_type error in
|
||||
# kernel/nvidia-modeset.ko.
|
||||
#
|
||||
# BEGIN {
|
||||
# pahole_cmd = "pahole"
|
||||
# for (i = 1; i < ARGC; i++) {
|
||||
# if (ARGV[i] ~ /--lang_exclude=/) {
|
||||
# pahole_cmd = pahole_cmd sprintf(" %s,c++", ARGV[i])
|
||||
# } else {
|
||||
# pahole_cmd = pahole_cmd sprintf(" %s", ARGV[i])
|
||||
# }
|
||||
# }
|
||||
# system(pahole_cmd)
|
||||
# }
|
||||
PAHOLE_AWK_PROGRAM = BEGIN { pahole_cmd = \"pahole\"; for (i = 1; i < ARGC; i++) { if (ARGV[i] ~ /--lang_exclude=/) { pahole_cmd = pahole_cmd sprintf(\" %s,c++\", ARGV[i]); } else { pahole_cmd = pahole_cmd sprintf(\" %s\", ARGV[i]); } } system(pahole_cmd); }
|
||||
# If scripts/pahole-flags.sh is not present in the kernel tree, add PAHOLE and
|
||||
# PAHOLE_AWK_PROGRAM assignments to PAHOLE_VARIABLES; otherwise assign the
|
||||
# empty string to PAHOLE_VARIABLES.
|
||||
PAHOLE_VARIABLES=$(if $(wildcard $(KERNEL_SOURCES)/scripts/pahole-flags.sh),,"PAHOLE=$(AWK) '$(PAHOLE_AWK_PROGRAM)'")
|
||||
|
||||
ifndef ARCH
|
||||
ARCH := $(shell uname -m | sed -e 's/i.86/i386/' \
|
||||
-e 's/armv[0-7]\w\+/arm/' \
|
||||
-e 's/aarch64/arm64/' \
|
||||
-e 's/ppc64le/powerpc/' \
|
||||
-e 's/riscv64/riscv/' \
|
||||
)
|
||||
endif
|
||||
|
||||
KERNEL_ARCH = $(ARCH)
|
||||
|
||||
ifneq ($(filter $(ARCH),i386 x86_64),)
|
||||
KERNEL_ARCH = x86
|
||||
else
|
||||
ifeq ($(filter $(ARCH),arm64 riscv),)
|
||||
$(error Unsupported architecture $(ARCH))
|
||||
endif
|
||||
endif
|
||||
|
||||
NV_KERNEL_MODULES ?= $(wildcard nvidia nvidia-modeset nvidia-drm)
|
||||
NV_KERNEL_MODULES := $(filter-out $(NV_EXCLUDE_KERNEL_MODULES), \
|
||||
$(NV_KERNEL_MODULES))
|
||||
INSTALL_MOD_DIR ?= kernel/drivers/video
|
||||
|
||||
NV_VERBOSE ?=
|
||||
SPECTRE_V2_RETPOLINE ?= 0
|
||||
|
||||
@@ -74,12 +130,13 @@ else
|
||||
KBUILD_PARAMS += NV_KERNEL_SOURCES=$(KERNEL_SOURCES)
|
||||
KBUILD_PARAMS += NV_KERNEL_OUTPUT=$(KERNEL_OUTPUT)
|
||||
KBUILD_PARAMS += NV_KERNEL_MODULES="$(NV_KERNEL_MODULES)"
|
||||
KBUILD_PARAMS += INSTALL_MOD_DIR=kernel/drivers/video
|
||||
KBUILD_PARAMS += INSTALL_MOD_DIR="$(INSTALL_MOD_DIR)"
|
||||
KBUILD_PARAMS += NV_SPECTRE_V2=$(SPECTRE_V2_RETPOLINE)
|
||||
|
||||
.PHONY: modules module clean clean_conftest modules_install
|
||||
modules clean modules_install:
|
||||
@$(MAKE) "LD=$(LD)" "CC=$(CC)" "OBJDUMP=$(OBJDUMP)" $(KBUILD_PARAMS) $@
|
||||
@$(MAKE) "LD=$(LD)" "CC=$(CC)" "OBJDUMP=$(OBJDUMP)" \
|
||||
$(PAHOLE_VARIABLES) $(KBUILD_PARAMS) $@
|
||||
@if [ "$@" = "modules" ]; then \
|
||||
for module in $(NV_KERNEL_MODULES); do \
|
||||
if [ -x split-object-file.sh ]; then \
|
||||
@@ -99,8 +156,9 @@ else
|
||||
# module symbols on which the Linux kernel's module resolution is dependent
|
||||
# and hence must be used whenever present.
|
||||
|
||||
LD_SCRIPT ?= $(KERNEL_SOURCES)/scripts/module-common.lds \
|
||||
$(KERNEL_SOURCES)/arch/$(ARCH)/kernel/module.lds \
|
||||
LD_SCRIPT ?= $(KERNEL_SOURCES)/scripts/module-common.lds \
|
||||
$(KERNEL_SOURCES)/arch/$(KERNEL_ARCH)/kernel/module.lds \
|
||||
$(KERNEL_OUTPUT)/arch/$(KERNEL_ARCH)/module.lds \
|
||||
$(KERNEL_OUTPUT)/scripts/module.lds
|
||||
NV_MODULE_COMMON_SCRIPTS := $(foreach s, $(wildcard $(LD_SCRIPT)), -T $(s))
|
||||
|
||||
43
kernel-open/common/inc/nv-chardev-numbers.h
Normal file
43
kernel-open/common/inc/nv-chardev-numbers.h
Normal file
@@ -0,0 +1,43 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
#ifndef _NV_CHARDEV_NUMBERS_H_
|
||||
#define _NV_CHARDEV_NUMBERS_H_
|
||||
|
||||
// NVIDIA's reserved major character device number (Linux).
|
||||
#define NV_MAJOR_DEVICE_NUMBER 195
|
||||
|
||||
// Minor numbers 0 to 247 reserved for regular devices
|
||||
#define NV_MINOR_DEVICE_NUMBER_REGULAR_MAX 247
|
||||
|
||||
// Minor numbers 248 to 253 currently unused
|
||||
|
||||
// Minor number 254 reserved for the modeset device (provided by NVKMS)
|
||||
#define NV_MINOR_DEVICE_NUMBER_MODESET_DEVICE 254
|
||||
|
||||
// Minor number 255 reserved for the control device
|
||||
#define NV_MINOR_DEVICE_NUMBER_CONTROL_DEVICE 255
|
||||
|
||||
#endif // _NV_CHARDEV_NUMBERS_H_
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -32,7 +32,10 @@
|
||||
typedef enum
|
||||
{
|
||||
NV_FIRMWARE_TYPE_GSP,
|
||||
NV_FIRMWARE_TYPE_GSP_LOG
|
||||
NV_FIRMWARE_TYPE_GSP_LOG,
|
||||
#if defined(NV_VMWARE)
|
||||
NV_FIRMWARE_TYPE_BINDATA
|
||||
#endif
|
||||
} nv_firmware_type_t;
|
||||
|
||||
typedef enum
|
||||
@@ -42,6 +45,10 @@ typedef enum
|
||||
NV_FIRMWARE_CHIP_FAMILY_TU11X = 2,
|
||||
NV_FIRMWARE_CHIP_FAMILY_GA100 = 3,
|
||||
NV_FIRMWARE_CHIP_FAMILY_GA10X = 4,
|
||||
NV_FIRMWARE_CHIP_FAMILY_AD10X = 5,
|
||||
NV_FIRMWARE_CHIP_FAMILY_GH100 = 6,
|
||||
NV_FIRMWARE_CHIP_FAMILY_GB10X = 8,
|
||||
NV_FIRMWARE_CHIP_FAMILY_GB10Y = 11,
|
||||
NV_FIRMWARE_CHIP_FAMILY_END,
|
||||
} nv_firmware_chip_family_t;
|
||||
|
||||
@@ -50,6 +57,10 @@ static inline const char *nv_firmware_chip_family_to_string(
|
||||
)
|
||||
{
|
||||
switch (fw_chip_family) {
|
||||
case NV_FIRMWARE_CHIP_FAMILY_GB10X: return "gb10x";
|
||||
case NV_FIRMWARE_CHIP_FAMILY_GB10Y: return "gb10y";
|
||||
case NV_FIRMWARE_CHIP_FAMILY_GH100: return "gh100";
|
||||
case NV_FIRMWARE_CHIP_FAMILY_AD10X: return "ad10x";
|
||||
case NV_FIRMWARE_CHIP_FAMILY_GA10X: return "ga10x";
|
||||
case NV_FIRMWARE_CHIP_FAMILY_GA100: return "ga100";
|
||||
case NV_FIRMWARE_CHIP_FAMILY_TU11X: return "tu11x";
|
||||
@@ -57,18 +68,18 @@ static inline const char *nv_firmware_chip_family_to_string(
|
||||
|
||||
case NV_FIRMWARE_CHIP_FAMILY_END: // fall through
|
||||
case NV_FIRMWARE_CHIP_FAMILY_NULL:
|
||||
return NULL;
|
||||
return "";
|
||||
}
|
||||
return NULL;
|
||||
return "";
|
||||
}
|
||||
|
||||
// The includer (presumably nv.c) may optionally define
|
||||
// NV_FIRMWARE_PATH_FOR_FILENAME(filename)
|
||||
// to return a string "path" given a gsp_*.bin or gsp_log_*.bin filename.
|
||||
// The includer may optionally define
|
||||
// NV_FIRMWARE_FOR_NAME(name)
|
||||
// to return a platform-defined string for a given a gsp_* or gsp_log_* name.
|
||||
//
|
||||
// The function nv_firmware_path will then be available.
|
||||
#if defined(NV_FIRMWARE_PATH_FOR_FILENAME)
|
||||
static inline const char *nv_firmware_path(
|
||||
// The function nv_firmware_for_chip_family will then be available.
|
||||
#if defined(NV_FIRMWARE_FOR_NAME)
|
||||
static inline const char *nv_firmware_for_chip_family(
|
||||
nv_firmware_type_t fw_type,
|
||||
nv_firmware_chip_family_t fw_chip_family
|
||||
)
|
||||
@@ -77,13 +88,17 @@ static inline const char *nv_firmware_path(
|
||||
{
|
||||
switch (fw_chip_family)
|
||||
{
|
||||
case NV_FIRMWARE_CHIP_FAMILY_GB10X: // fall through
|
||||
case NV_FIRMWARE_CHIP_FAMILY_GB10Y: // fall through
|
||||
case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through
|
||||
case NV_FIRMWARE_CHIP_FAMILY_AD10X: // fall through
|
||||
case NV_FIRMWARE_CHIP_FAMILY_GA10X:
|
||||
return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_ga10x.bin");
|
||||
return NV_FIRMWARE_FOR_NAME("gsp_ga10x");
|
||||
|
||||
case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through
|
||||
case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through
|
||||
case NV_FIRMWARE_CHIP_FAMILY_TU10X:
|
||||
return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_tu10x.bin");
|
||||
return NV_FIRMWARE_FOR_NAME("gsp_tu10x");
|
||||
|
||||
case NV_FIRMWARE_CHIP_FAMILY_END: // fall through
|
||||
case NV_FIRMWARE_CHIP_FAMILY_NULL:
|
||||
@@ -94,31 +109,40 @@ static inline const char *nv_firmware_path(
|
||||
{
|
||||
switch (fw_chip_family)
|
||||
{
|
||||
case NV_FIRMWARE_CHIP_FAMILY_GB10X: // fall through
|
||||
case NV_FIRMWARE_CHIP_FAMILY_GB10Y: // fall through
|
||||
case NV_FIRMWARE_CHIP_FAMILY_GH100: // fall through
|
||||
case NV_FIRMWARE_CHIP_FAMILY_AD10X: // fall through
|
||||
case NV_FIRMWARE_CHIP_FAMILY_GA10X:
|
||||
return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_ga10x.bin");
|
||||
return NV_FIRMWARE_FOR_NAME("gsp_log_ga10x");
|
||||
|
||||
case NV_FIRMWARE_CHIP_FAMILY_GA100: // fall through
|
||||
case NV_FIRMWARE_CHIP_FAMILY_TU11X: // fall through
|
||||
case NV_FIRMWARE_CHIP_FAMILY_TU10X:
|
||||
return NV_FIRMWARE_PATH_FOR_FILENAME("gsp_log_tu10x.bin");
|
||||
return NV_FIRMWARE_FOR_NAME("gsp_log_tu10x");
|
||||
|
||||
case NV_FIRMWARE_CHIP_FAMILY_END: // fall through
|
||||
case NV_FIRMWARE_CHIP_FAMILY_NULL:
|
||||
return "";
|
||||
}
|
||||
}
|
||||
|
||||
#if defined(NV_VMWARE)
|
||||
else if (fw_type == NV_FIRMWARE_TYPE_BINDATA)
|
||||
{
|
||||
return NV_FIRMWARE_FOR_NAME("bindata_image");
|
||||
}
|
||||
#endif
|
||||
return "";
|
||||
}
|
||||
#endif // defined(NV_FIRMWARE_PATH_FOR_FILENAME)
|
||||
#endif // defined(NV_FIRMWARE_FOR_NAME)
|
||||
|
||||
// The includer (presumably nv.c) may optionally define
|
||||
// NV_FIRMWARE_DECLARE_GSP_FILENAME(filename)
|
||||
// The includer may optionally define
|
||||
// NV_FIRMWARE_DECLARE_GSP(name)
|
||||
// which will then be invoked (at the top-level) for each
|
||||
// gsp_*.bin (but not gsp_log_*.bin)
|
||||
#if defined(NV_FIRMWARE_DECLARE_GSP_FILENAME)
|
||||
NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_ga10x.bin")
|
||||
NV_FIRMWARE_DECLARE_GSP_FILENAME("gsp_tu10x.bin")
|
||||
#endif // defined(NV_FIRMWARE_DECLARE_GSP_FILENAME)
|
||||
// gsp_* (but not gsp_log_*)
|
||||
#if defined(NV_FIRMWARE_DECLARE_GSP)
|
||||
NV_FIRMWARE_DECLARE_GSP("gsp_ga10x")
|
||||
NV_FIRMWARE_DECLARE_GSP("gsp_tu10x")
|
||||
#endif // defined(NV_FIRMWARE_DECLARE_GSP)
|
||||
|
||||
#endif // NV_FIRMWARE_DECLARE_GSP_FILENAME
|
||||
#endif // NV_FIRMWARE_DECLARE_GSP
|
||||
@@ -29,17 +29,9 @@
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/hash.h>
|
||||
|
||||
#if defined(NV_LINUX_STRINGHASH_H_PRESENT)
|
||||
#include <linux/stringhash.h> /* full_name_hash() */
|
||||
#else
|
||||
#include <linux/dcache.h>
|
||||
#endif
|
||||
|
||||
#if (NV_FULL_NAME_HASH_ARGUMENT_COUNT == 3)
|
||||
#define nv_string_hash(_str) full_name_hash(NULL, _str, strlen(_str))
|
||||
#else
|
||||
#define nv_string_hash(_str) full_name_hash(_str, strlen(_str))
|
||||
#endif
|
||||
|
||||
/**
|
||||
* This naive hashtable was introduced by commit d9b482c8ba19 (v3.7, 2012-10-31).
|
||||
@@ -37,13 +37,11 @@ typedef enum _HYPERVISOR_TYPE
|
||||
OS_HYPERVISOR_UNKNOWN
|
||||
} HYPERVISOR_TYPE;
|
||||
|
||||
#define CMD_VGPU_VFIO_WAKE_WAIT_QUEUE 0
|
||||
#define CMD_VGPU_VFIO_INJECT_INTERRUPT 1
|
||||
#define CMD_VGPU_VFIO_REGISTER_MDEV 2
|
||||
#define CMD_VGPU_VFIO_PRESENT 3
|
||||
#define CMD_VFIO_PCI_CORE_PRESENT 4
|
||||
#define CMD_VFIO_WAKE_REMOVE_GPU 1
|
||||
#define CMD_VGPU_VFIO_PRESENT 2
|
||||
#define CMD_VFIO_PCI_CORE_PRESENT 3
|
||||
|
||||
#define MAX_VF_COUNT_PER_GPU 64
|
||||
#define MAX_VF_COUNT_PER_GPU 64
|
||||
|
||||
typedef enum _VGPU_TYPE_INFO
|
||||
{
|
||||
@@ -54,17 +52,11 @@ typedef enum _VGPU_TYPE_INFO
|
||||
|
||||
typedef struct
|
||||
{
|
||||
void *vgpuVfioRef;
|
||||
void *waitQueue;
|
||||
void *nv;
|
||||
NvU32 *vgpuTypeIds;
|
||||
NvU8 **vgpuNames;
|
||||
NvU32 numVgpuTypes;
|
||||
NvU32 domain;
|
||||
NvU8 bus;
|
||||
NvU8 slot;
|
||||
NvU8 function;
|
||||
NvBool is_virtfn;
|
||||
NvU32 domain;
|
||||
NvU32 bus;
|
||||
NvU32 device;
|
||||
NvU32 return_status;
|
||||
} vgpu_vfio_info;
|
||||
|
||||
typedef struct
|
||||
@@ -25,14 +25,12 @@
|
||||
#ifndef NV_IOCTL_NUMA_H
|
||||
#define NV_IOCTL_NUMA_H
|
||||
|
||||
#if defined(NV_LINUX)
|
||||
|
||||
#include <nv-ioctl-numbers.h>
|
||||
|
||||
#if defined(NV_KERNEL_INTERFACE_LAYER)
|
||||
|
||||
#if defined(NV_KERNEL_INTERFACE_LAYER) && defined(NV_LINUX)
|
||||
#include <linux/types.h>
|
||||
|
||||
#elif defined (NV_KERNEL_INTERFACE_LAYER) && defined(NV_BSD)
|
||||
#include <sys/stdint.h>
|
||||
#else
|
||||
|
||||
#include <stdint.h>
|
||||
@@ -81,5 +79,3 @@ typedef struct nv_ioctl_set_numa_status
|
||||
#define NV_IOCTL_NUMA_STATUS_OFFLINE_FAILED 6
|
||||
|
||||
#endif
|
||||
|
||||
#endif
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -39,5 +39,6 @@
|
||||
#define NV_ESC_QUERY_DEVICE_INTR (NV_IOCTL_BASE + 13)
|
||||
#define NV_ESC_SYS_PARAMS (NV_IOCTL_BASE + 14)
|
||||
#define NV_ESC_EXPORT_TO_DMABUF_FD (NV_IOCTL_BASE + 17)
|
||||
#define NV_ESC_WAIT_OPEN_COMPLETE (NV_IOCTL_BASE + 18)
|
||||
|
||||
#endif
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -128,6 +128,9 @@ typedef struct nv_ioctl_register_fd
|
||||
|
||||
#define NV_DMABUF_EXPORT_MAX_HANDLES 128
|
||||
|
||||
#define NV_DMABUF_EXPORT_MAPPING_TYPE_DEFAULT 0
|
||||
#define NV_DMABUF_EXPORT_MAPPING_TYPE_FORCE_PCIE 1
|
||||
|
||||
typedef struct nv_ioctl_export_to_dma_buf_fd
|
||||
{
|
||||
int fd;
|
||||
@@ -136,10 +139,18 @@ typedef struct nv_ioctl_export_to_dma_buf_fd
|
||||
NvU32 numObjects;
|
||||
NvU32 index;
|
||||
NvU64 totalSize NV_ALIGN_BYTES(8);
|
||||
NvU8 mappingType;
|
||||
NvBool bAllowMmap;
|
||||
NvHandle handles[NV_DMABUF_EXPORT_MAX_HANDLES];
|
||||
NvU64 offsets[NV_DMABUF_EXPORT_MAX_HANDLES] NV_ALIGN_BYTES(8);
|
||||
NvU64 sizes[NV_DMABUF_EXPORT_MAX_HANDLES] NV_ALIGN_BYTES(8);
|
||||
NvU32 status;
|
||||
} nv_ioctl_export_to_dma_buf_fd_t;
|
||||
|
||||
typedef struct nv_ioctl_wait_open_complete
|
||||
{
|
||||
int rc;
|
||||
NvU32 adapterStatus;
|
||||
} nv_ioctl_wait_open_complete_t;
|
||||
|
||||
#endif
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2012-2013 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2016-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -21,35 +21,44 @@
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __NV_KTHREAD_QUEUE_OS_H__
|
||||
#define __NV_KTHREAD_QUEUE_OS_H__
|
||||
|
||||
#ifndef _NV_REGISTER_MODULE_H_
|
||||
#define _NV_REGISTER_MODULE_H_
|
||||
#include <linux/types.h> // atomic_t
|
||||
#include <linux/list.h> // list
|
||||
#include <linux/sched.h> // task_struct
|
||||
#include <linux/numa.h> // NUMA_NO_NODE
|
||||
#include <linux/semaphore.h>
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/fs.h>
|
||||
#include <linux/poll.h>
|
||||
#include "conftest.h"
|
||||
|
||||
#include "nvtypes.h"
|
||||
struct nv_kthread_q
|
||||
{
|
||||
struct list_head q_list_head;
|
||||
spinlock_t q_lock;
|
||||
|
||||
typedef struct nvidia_module_s {
|
||||
struct module *owner;
|
||||
// This is a counting semaphore. It gets incremented and decremented
|
||||
// exactly once for each item that is added to the queue.
|
||||
struct semaphore q_sem;
|
||||
atomic_t main_loop_should_exit;
|
||||
|
||||
/* nvidia0, nvidia1 ..*/
|
||||
const char *module_name;
|
||||
struct task_struct *q_kthread;
|
||||
|
||||
/* module instance */
|
||||
NvU32 instance;
|
||||
bool is_unload_flush_ongoing;
|
||||
};
|
||||
|
||||
/* file operations */
|
||||
int (*open)(struct inode *, struct file *filp);
|
||||
int (*close)(struct inode *, struct file *filp);
|
||||
int (*mmap)(struct file *filp, struct vm_area_struct *vma);
|
||||
int (*ioctl)(struct inode *, struct file * file, unsigned int cmd, unsigned long arg);
|
||||
unsigned int (*poll)(struct file * file, poll_table *wait);
|
||||
struct nv_kthread_q_item
|
||||
{
|
||||
struct list_head q_list_node;
|
||||
nv_q_func_t function_to_run;
|
||||
void *function_args;
|
||||
};
|
||||
|
||||
} nvidia_module_t;
|
||||
|
||||
int nvidia_register_module(nvidia_module_t *);
|
||||
int nvidia_unregister_module(nvidia_module_t *);
|
||||
#ifndef NUMA_NO_NODE
|
||||
#define NUMA_NO_NODE (-1)
|
||||
#endif
|
||||
|
||||
#define NV_KTHREAD_NO_NODE NUMA_NO_NODE
|
||||
|
||||
#endif
|
||||
@@ -24,13 +24,14 @@
|
||||
#ifndef __NV_KTHREAD_QUEUE_H__
|
||||
#define __NV_KTHREAD_QUEUE_H__
|
||||
|
||||
#include <linux/types.h> // atomic_t
|
||||
#include <linux/list.h> // list
|
||||
#include <linux/sched.h> // task_struct
|
||||
#include <linux/numa.h> // NUMA_NO_NODE
|
||||
#include <linux/semaphore.h>
|
||||
struct nv_kthread_q;
|
||||
struct nv_kthread_q_item;
|
||||
typedef struct nv_kthread_q nv_kthread_q_t;
|
||||
typedef struct nv_kthread_q_item nv_kthread_q_item_t;
|
||||
|
||||
#include "conftest.h"
|
||||
typedef void (*nv_q_func_t)(void *args);
|
||||
|
||||
#include "nv-kthread-q-os.h"
|
||||
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
// nv_kthread_q:
|
||||
@@ -85,38 +86,6 @@
|
||||
//
|
||||
////////////////////////////////////////////////////////////////////////////////
|
||||
|
||||
typedef struct nv_kthread_q nv_kthread_q_t;
|
||||
typedef struct nv_kthread_q_item nv_kthread_q_item_t;
|
||||
|
||||
typedef void (*nv_q_func_t)(void *args);
|
||||
|
||||
struct nv_kthread_q
|
||||
{
|
||||
struct list_head q_list_head;
|
||||
spinlock_t q_lock;
|
||||
|
||||
// This is a counting semaphore. It gets incremented and decremented
|
||||
// exactly once for each item that is added to the queue.
|
||||
struct semaphore q_sem;
|
||||
atomic_t main_loop_should_exit;
|
||||
|
||||
struct task_struct *q_kthread;
|
||||
};
|
||||
|
||||
struct nv_kthread_q_item
|
||||
{
|
||||
struct list_head q_list_node;
|
||||
nv_q_func_t function_to_run;
|
||||
void *function_args;
|
||||
};
|
||||
|
||||
|
||||
#ifndef NUMA_NO_NODE
|
||||
#define NUMA_NO_NODE (-1)
|
||||
#endif
|
||||
|
||||
#define NV_KTHREAD_NO_NODE NUMA_NO_NODE
|
||||
|
||||
//
|
||||
// The queue must not be used before calling this routine.
|
||||
//
|
||||
@@ -155,10 +124,7 @@ int nv_kthread_q_init_on_node(nv_kthread_q_t *q,
|
||||
// This routine is the same as nv_kthread_q_init_on_node() with the exception
|
||||
// that the queue stack will be allocated on the NUMA node of the caller.
|
||||
//
|
||||
static inline int nv_kthread_q_init(nv_kthread_q_t *q, const char *qname)
|
||||
{
|
||||
return nv_kthread_q_init_on_node(q, qname, NV_KTHREAD_NO_NODE);
|
||||
}
|
||||
int nv_kthread_q_init(nv_kthread_q_t *q, const char *qname);
|
||||
|
||||
//
|
||||
// The caller is responsible for stopping all queues, by calling this routine
|
||||
File diff suppressed because it is too large
Load Diff
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2017-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -28,25 +28,12 @@
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
#include <linux/rwsem.h>
|
||||
#include <linux/sched.h> /* signal_pending, cond_resched */
|
||||
#include <linux/sched.h> /* cond_resched */
|
||||
#include <linux/semaphore.h>
|
||||
#include <linux/sched/signal.h> /* signal_pending */
|
||||
|
||||
#if defined(NV_LINUX_SCHED_SIGNAL_H_PRESENT)
|
||||
#include <linux/sched/signal.h> /* signal_pending for kernels >= 4.11 */
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_PREEMPT_RT) || defined(CONFIG_PREEMPT_RT_FULL)
|
||||
typedef raw_spinlock_t nv_spinlock_t;
|
||||
#define NV_SPIN_LOCK_INIT(lock) raw_spin_lock_init(lock)
|
||||
#define NV_SPIN_LOCK_IRQ(lock) raw_spin_lock_irq(lock)
|
||||
#define NV_SPIN_UNLOCK_IRQ(lock) raw_spin_unlock_irq(lock)
|
||||
#define NV_SPIN_LOCK_IRQSAVE(lock,flags) raw_spin_lock_irqsave(lock,flags)
|
||||
#define NV_SPIN_UNLOCK_IRQRESTORE(lock,flags) raw_spin_unlock_irqrestore(lock,flags)
|
||||
#define NV_SPIN_LOCK(lock) raw_spin_lock(lock)
|
||||
#define NV_SPIN_UNLOCK(lock) raw_spin_unlock(lock)
|
||||
#define NV_SPIN_UNLOCK_WAIT(lock) raw_spin_unlock_wait(lock)
|
||||
#else
|
||||
typedef spinlock_t nv_spinlock_t;
|
||||
#define NV_DEFINE_SPINLOCK(lock) DEFINE_SPINLOCK(lock)
|
||||
#define NV_SPIN_LOCK_INIT(lock) spin_lock_init(lock)
|
||||
#define NV_SPIN_LOCK_IRQ(lock) spin_lock_irq(lock)
|
||||
#define NV_SPIN_UNLOCK_IRQ(lock) spin_unlock_irq(lock)
|
||||
@@ -55,7 +42,6 @@ typedef spinlock_t nv_spinlock_t;
|
||||
#define NV_SPIN_LOCK(lock) spin_lock(lock)
|
||||
#define NV_SPIN_UNLOCK(lock) spin_unlock(lock)
|
||||
#define NV_SPIN_UNLOCK_WAIT(lock) spin_unlock_wait(lock)
|
||||
#endif
|
||||
|
||||
#define NV_INIT_MUTEX(mutex) sema_init(mutex, 1)
|
||||
|
||||
210
kernel-open/common/inc/nv-mm.h
Normal file
210
kernel-open/common/inc/nv-mm.h
Normal file
@@ -0,0 +1,210 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2016-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef __NV_MM_H__
|
||||
#define __NV_MM_H__
|
||||
|
||||
#include "conftest.h"
|
||||
|
||||
#if !defined(NV_VM_FAULT_T_IS_PRESENT)
|
||||
typedef int vm_fault_t;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* pin_user_pages()
|
||||
*
|
||||
* Presence of pin_user_pages() also implies the presence of unpin-user_page().
|
||||
* Both were added in the v5.6.
|
||||
*
|
||||
* pin_user_pages() was added by commit eddb1c228f79
|
||||
* ("mm/gup: introduce pin_user_pages*() and FOLL_PIN") in v5.6.
|
||||
*
|
||||
* Removed vmas parameter from pin_user_pages() by commit 4c630f307455
|
||||
* ("mm/gup: remove vmas parameter from pin_user_pages()") in v6.5.
|
||||
*/
|
||||
|
||||
#include <linux/mm.h>
|
||||
#include <linux/sched.h>
|
||||
|
||||
/*
|
||||
* FreeBSD's pin_user_pages's conftest breaks since pin_user_pages is an inline
|
||||
* function. Because it simply maps to get_user_pages, we can just replace
|
||||
* NV_PIN_USER_PAGES with NV_GET_USER_PAGES on FreeBSD
|
||||
*/
|
||||
#if defined(NV_PIN_USER_PAGES_PRESENT) && !defined(NV_BSD)
|
||||
#if defined(NV_PIN_USER_PAGES_HAS_ARGS_VMAS)
|
||||
#define NV_PIN_USER_PAGES(start, nr_pages, gup_flags, pages) \
|
||||
pin_user_pages(start, nr_pages, gup_flags, pages, NULL)
|
||||
#else
|
||||
#define NV_PIN_USER_PAGES pin_user_pages
|
||||
#endif // NV_PIN_USER_PAGES_HAS_ARGS_VMAS
|
||||
#define NV_UNPIN_USER_PAGE unpin_user_page
|
||||
#else
|
||||
#define NV_PIN_USER_PAGES NV_GET_USER_PAGES
|
||||
#define NV_UNPIN_USER_PAGE put_page
|
||||
#endif // NV_PIN_USER_PAGES_PRESENT
|
||||
|
||||
/*
|
||||
* get_user_pages()
|
||||
*
|
||||
* Removed vmas parameter from get_user_pages() by commit 54d020692b34
|
||||
* ("mm/gup: remove unused vmas parameter from get_user_pages()") in v6.5.
|
||||
*
|
||||
*/
|
||||
|
||||
#if !defined(NV_GET_USER_PAGES_HAS_VMAS_ARG)
|
||||
#define NV_GET_USER_PAGES get_user_pages
|
||||
#else
|
||||
#define NV_GET_USER_PAGES(start, nr_pages, flags, pages) \
|
||||
get_user_pages(start, nr_pages, flags, pages, NULL)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* pin_user_pages_remote()
|
||||
*
|
||||
* pin_user_pages_remote() was added by commit eddb1c228f79
|
||||
* ("mm/gup: introduce pin_user_pages*() and FOLL_PIN") in v5.6.
|
||||
*
|
||||
* pin_user_pages_remote() removed 'tsk' parameter by commit
|
||||
* 64019a2e467a ("mm/gup: remove task_struct pointer for all gup code")
|
||||
* in v5.9.
|
||||
*
|
||||
* Removed unused vmas parameter from pin_user_pages_remote() by commit
|
||||
* 0b295316b3a9 ("mm/gup: remove unused vmas parameter from
|
||||
* pin_user_pages_remote()") in v6.5.
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined(NV_PIN_USER_PAGES_REMOTE_PRESENT)
|
||||
#if defined(NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK_VMAS)
|
||||
#define NV_PIN_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, locked) \
|
||||
pin_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, NULL, locked)
|
||||
#elif defined(NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_VMAS)
|
||||
#define NV_PIN_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, locked) \
|
||||
pin_user_pages_remote(mm, start, nr_pages, flags, pages, NULL, locked)
|
||||
#else
|
||||
#define NV_PIN_USER_PAGES_REMOTE pin_user_pages_remote
|
||||
#endif // NV_PIN_USER_PAGES_REMOTE_HAS_ARGS_TSK_VMAS
|
||||
#else
|
||||
#define NV_PIN_USER_PAGES_REMOTE NV_GET_USER_PAGES_REMOTE
|
||||
#endif // NV_PIN_USER_PAGES_REMOTE_PRESENT
|
||||
|
||||
/*
|
||||
* Note that get_user_pages_remote() requires the caller to hold a reference on
|
||||
* the mm_struct.
|
||||
* This will always be true when using current and current->mm. If the kernel passes
|
||||
* the driver a vma via driver callback, the kernel holds a reference on vma->vm_mm
|
||||
* over that callback.
|
||||
*
|
||||
* get_user_pages_remote() removed 'tsk' parameter by
|
||||
* commit 64019a2e467a ("mm/gup: remove task_struct pointer for
|
||||
* all gup code") in v5.9.
|
||||
*
|
||||
* Removed vmas parameter from get_user_pages_remote() by commit ca5e863233e8
|
||||
* ("mm/gup: remove vmas parameter from get_user_pages_remote()") in v6.5.
|
||||
*
|
||||
*/
|
||||
|
||||
#if defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK_VMAS)
|
||||
#define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, locked) \
|
||||
get_user_pages_remote(NULL, mm, start, nr_pages, flags, pages, NULL, locked)
|
||||
#elif defined(NV_GET_USER_PAGES_REMOTE_HAS_ARGS_TSK)
|
||||
#define NV_GET_USER_PAGES_REMOTE(mm, start, nr_pages, flags, pages, locked) \
|
||||
get_user_pages_remote(mm, start, nr_pages, flags, pages, NULL, locked)
|
||||
|
||||
#else
|
||||
#define NV_GET_USER_PAGES_REMOTE get_user_pages_remote
|
||||
#endif
|
||||
|
||||
static inline void nv_mmap_read_lock(struct mm_struct *mm)
|
||||
{
|
||||
#if defined(NV_MM_HAS_MMAP_LOCK)
|
||||
mmap_read_lock(mm);
|
||||
#else
|
||||
down_read(&mm->mmap_sem);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void nv_mmap_read_unlock(struct mm_struct *mm)
|
||||
{
|
||||
#if defined(NV_MM_HAS_MMAP_LOCK)
|
||||
mmap_read_unlock(mm);
|
||||
#else
|
||||
up_read(&mm->mmap_sem);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void nv_mmap_write_lock(struct mm_struct *mm)
|
||||
{
|
||||
#if defined(NV_MM_HAS_MMAP_LOCK)
|
||||
mmap_write_lock(mm);
|
||||
#else
|
||||
down_write(&mm->mmap_sem);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void nv_mmap_write_unlock(struct mm_struct *mm)
|
||||
{
|
||||
#if defined(NV_MM_HAS_MMAP_LOCK)
|
||||
mmap_write_unlock(mm);
|
||||
#else
|
||||
up_write(&mm->mmap_sem);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline int nv_mm_rwsem_is_locked(struct mm_struct *mm)
|
||||
{
|
||||
#if defined(NV_MM_HAS_MMAP_LOCK)
|
||||
return rwsem_is_locked(&mm->mmap_lock);
|
||||
#else
|
||||
return rwsem_is_locked(&mm->mmap_sem);
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline struct rw_semaphore *nv_mmap_get_lock(struct mm_struct *mm)
|
||||
{
|
||||
#if defined(NV_MM_HAS_MMAP_LOCK)
|
||||
return &mm->mmap_lock;
|
||||
#else
|
||||
return &mm->mmap_sem;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void nv_vm_flags_set(struct vm_area_struct *vma, vm_flags_t flags)
|
||||
{
|
||||
#if defined(NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS)
|
||||
vm_flags_set(vma, flags);
|
||||
#else
|
||||
vma->vm_flags |= flags;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline void nv_vm_flags_clear(struct vm_area_struct *vma, vm_flags_t flags)
|
||||
{
|
||||
#if defined(NV_VM_AREA_STRUCT_HAS_CONST_VM_FLAGS)
|
||||
vm_flags_clear(vma, flags);
|
||||
#else
|
||||
vma->vm_flags &= ~flags;
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif // __NV_MM_H__
|
||||
@@ -58,6 +58,12 @@ typedef struct {
|
||||
*/
|
||||
void (*suspend)(NvU32 gpu_id);
|
||||
void (*resume)(NvU32 gpu_id);
|
||||
|
||||
/* Remove callback, called when a device is going away completely. */
|
||||
void (*remove)(NvU32 gpu_id);
|
||||
|
||||
/* Probe callback, called when a device is being hotplugged. */
|
||||
void (*probe)(const nv_gpu_info_t *gpu_info);
|
||||
} nvidia_modeset_callbacks_t;
|
||||
|
||||
/*
|
||||
@@ -26,8 +26,7 @@
|
||||
|
||||
#include "nv-linux.h"
|
||||
|
||||
#if (defined(CONFIG_X86_LOCAL_APIC) || defined(NVCPU_AARCH64) || \
|
||||
defined(NVCPU_PPC64LE)) && \
|
||||
#if (defined(CONFIG_X86_LOCAL_APIC) || defined(NVCPU_AARCH64)) && \
|
||||
(defined(CONFIG_PCI_MSI) || defined(CONFIG_PCI_USE_VECTOR))
|
||||
#define NV_LINUX_PCIE_MSI_SUPPORTED
|
||||
#endif
|
||||
@@ -87,12 +86,6 @@ static inline int nv_pci_enable_msix(nv_linux_state_t *nvl, int nvec)
|
||||
{
|
||||
int rc = 0;
|
||||
|
||||
/*
|
||||
* pci_enable_msix_range() replaced pci_enable_msix() in 3.14-rc1:
|
||||
* 2014-01-03 302a2523c277bea0bbe8340312b09507905849ed
|
||||
*/
|
||||
|
||||
#if defined(NV_PCI_ENABLE_MSIX_RANGE_PRESENT)
|
||||
// We require all the vectors we are requesting so use the same min and max
|
||||
rc = pci_enable_msix_range(nvl->pci_dev, nvl->msix_entries, nvec, nvec);
|
||||
if (rc < 0)
|
||||
@@ -100,13 +93,6 @@ static inline int nv_pci_enable_msix(nv_linux_state_t *nvl, int nvec)
|
||||
return NV_ERR_OPERATING_SYSTEM;
|
||||
}
|
||||
WARN_ON(nvec != rc);
|
||||
#else
|
||||
rc = pci_enable_msix(nvl->pci_dev, nvl->msix_entries, nvec);
|
||||
if (rc != 0)
|
||||
{
|
||||
return NV_ERR_OPERATING_SYSTEM;
|
||||
}
|
||||
#endif
|
||||
|
||||
nvl->num_intr = nvec;
|
||||
return NV_OK;
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -36,5 +36,7 @@ int nv_pci_count_devices(void);
|
||||
NvU8 nv_find_pci_capability(struct pci_dev *, NvU8);
|
||||
int nvidia_dev_get_pci_info(const NvU8 *, struct pci_dev **, NvU64 *, NvU64 *);
|
||||
nv_linux_state_t * find_pci(NvU32, NvU8, NvU8, NvU8);
|
||||
|
||||
NvBool nv_pci_is_valid_topology_for_direct_pci(nv_state_t *, struct pci_dev *);
|
||||
NvBool nv_pci_has_common_pci_switch(nv_state_t *nv, struct pci_dev *);
|
||||
void nv_pci_tegra_boost_sys_uproc(struct device *dev);
|
||||
#endif
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -60,18 +60,13 @@ static inline pgprot_t pgprot_modify_writecombine(pgprot_t old_prot)
|
||||
#endif /* !defined(NV_VMWARE) */
|
||||
|
||||
#if defined(NVCPU_AARCH64)
|
||||
extern NvBool nvos_is_chipset_io_coherent(void);
|
||||
/*
|
||||
* Don't rely on the kernel's definition of pgprot_noncached(), as on 64-bit
|
||||
* ARM that's not for system memory, but device memory instead. For I/O cache
|
||||
* coherent systems, use cached mappings instead of uncached.
|
||||
* ARM that's not for system memory, but device memory instead.
|
||||
*/
|
||||
#define NV_PGPROT_UNCACHED(old_prot) \
|
||||
((nvos_is_chipset_io_coherent()) ? \
|
||||
(old_prot) : \
|
||||
__pgprot_modify((old_prot), PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC)))
|
||||
#elif defined(NVCPU_PPC64LE)
|
||||
/* Don't attempt to mark sysmem pages as uncached on ppc64le */
|
||||
#define NV_PGPROT_UNCACHED(old_prot) old_prot
|
||||
__pgprot_modify((old_prot), PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL_NC))
|
||||
#else
|
||||
#define NV_PGPROT_UNCACHED(old_prot) pgprot_noncached(old_prot)
|
||||
#endif
|
||||
@@ -93,32 +88,13 @@ static inline pgprot_t pgprot_modify_writecombine(pgprot_t old_prot)
|
||||
NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot)
|
||||
#define NV_PGPROT_READ_ONLY(old_prot) \
|
||||
__pgprot(pgprot_val((old_prot)) & ~_PAGE_RW)
|
||||
#elif defined(NVCPU_PPC64LE)
|
||||
/*
|
||||
* Some kernels use H_PAGE instead of _PAGE
|
||||
*/
|
||||
#if defined(_PAGE_RW)
|
||||
#define NV_PAGE_RW _PAGE_RW
|
||||
#elif defined(H_PAGE_RW)
|
||||
#define NV_PAGE_RW H_PAGE_RW
|
||||
#else
|
||||
#warning "The kernel does not provide page protection defines!"
|
||||
#endif
|
||||
|
||||
#if defined(_PAGE_4K_PFN)
|
||||
#define NV_PAGE_4K_PFN _PAGE_4K_PFN
|
||||
#elif defined(H_PAGE_4K_PFN)
|
||||
#define NV_PAGE_4K_PFN H_PAGE_4K_PFN
|
||||
#else
|
||||
#undef NV_PAGE_4K_PFN
|
||||
#endif
|
||||
|
||||
#elif defined(NVCPU_RISCV64)
|
||||
#define NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot) \
|
||||
pgprot_writecombine(old_prot)
|
||||
/* Don't attempt to mark sysmem pages as write combined on ppc64le */
|
||||
#define NV_PGPROT_WRITE_COMBINED(old_prot) old_prot
|
||||
/* Don't attempt to mark sysmem pages as write combined on riscv */
|
||||
#define NV_PGPROT_WRITE_COMBINED(old_prot) old_prot
|
||||
#define NV_PGPROT_READ_ONLY(old_prot) \
|
||||
__pgprot(pgprot_val((old_prot)) & ~NV_PAGE_RW)
|
||||
__pgprot(pgprot_val((old_prot)) & ~_PAGE_WRITE)
|
||||
#else
|
||||
/* Writecombine is not supported */
|
||||
#undef NV_PGPROT_WRITE_COMBINED_DEVICE(old_prot)
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2019-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2019-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -35,6 +35,26 @@ int nv_platform_count_devices(void);
|
||||
int nv_soc_register_irqs(nv_state_t *nv);
|
||||
void nv_soc_free_irqs(nv_state_t *nv);
|
||||
|
||||
int nv_remove_conflicting_framebuffers(void);
|
||||
#define NV_SUPPORTS_PLATFORM_DEVICE NV_IS_EXPORT_SYMBOL_PRESENT___platform_driver_register
|
||||
|
||||
#if defined(NV_LINUX_PLATFORM_TEGRA_DCE_DCE_CLIENT_IPC_H_PRESENT)
|
||||
#define NV_SUPPORTS_DCE_CLIENT_IPC 1
|
||||
#else
|
||||
#define NV_SUPPORTS_DCE_CLIENT_IPC 0
|
||||
#endif
|
||||
|
||||
#define NV_SUPPORTS_PLATFORM_DISPLAY_DEVICE (NV_SUPPORTS_PLATFORM_DEVICE && NV_SUPPORTS_DCE_CLIENT_IPC)
|
||||
|
||||
#if defined(CONFIG_OF)
|
||||
NV_STATUS nv_platform_get_screen_info_dt(
|
||||
NvU64 *pPhysicalAddress,
|
||||
NvU32 *pFbWidth,
|
||||
NvU32 *pFbHeight,
|
||||
NvU32 *pFbDepth,
|
||||
NvU32 *pFbPitch,
|
||||
NvU64 *pFbSize
|
||||
);
|
||||
|
||||
#endif // CONFIG_OF
|
||||
|
||||
#endif
|
||||
@@ -92,6 +92,24 @@ typedef struct file_operations nv_proc_ops_t;
|
||||
#endif
|
||||
|
||||
#define NV_DEFINE_SINGLE_PROCFS_FILE_HELPER(name, lock) \
|
||||
static ssize_t nv_procfs_read_lock_##name( \
|
||||
struct file *file, \
|
||||
char __user *buf, \
|
||||
size_t size, \
|
||||
loff_t *ppos \
|
||||
) \
|
||||
{ \
|
||||
int ret; \
|
||||
ret = nv_down_read_interruptible(&lock); \
|
||||
if (ret < 0) \
|
||||
{ \
|
||||
return ret; \
|
||||
} \
|
||||
size = seq_read(file, buf, size, ppos); \
|
||||
up_read(&lock); \
|
||||
return size; \
|
||||
} \
|
||||
\
|
||||
static int nv_procfs_open_##name( \
|
||||
struct inode *inode, \
|
||||
struct file *filep \
|
||||
@@ -104,11 +122,6 @@ typedef struct file_operations nv_proc_ops_t;
|
||||
{ \
|
||||
return ret; \
|
||||
} \
|
||||
ret = nv_down_read_interruptible(&lock); \
|
||||
if (ret < 0) \
|
||||
{ \
|
||||
single_release(inode, filep); \
|
||||
} \
|
||||
return ret; \
|
||||
} \
|
||||
\
|
||||
@@ -117,7 +130,6 @@ typedef struct file_operations nv_proc_ops_t;
|
||||
struct file *filep \
|
||||
) \
|
||||
{ \
|
||||
up_read(&lock); \
|
||||
return single_release(inode, filep); \
|
||||
}
|
||||
|
||||
@@ -127,46 +139,7 @@ typedef struct file_operations nv_proc_ops_t;
|
||||
static const nv_proc_ops_t nv_procfs_##name##_fops = { \
|
||||
NV_PROC_OPS_SET_OWNER() \
|
||||
.NV_PROC_OPS_OPEN = nv_procfs_open_##name, \
|
||||
.NV_PROC_OPS_READ = seq_read, \
|
||||
.NV_PROC_OPS_LSEEK = seq_lseek, \
|
||||
.NV_PROC_OPS_RELEASE = nv_procfs_release_##name, \
|
||||
};
|
||||
|
||||
|
||||
#define NV_DEFINE_SINGLE_PROCFS_FILE_READ_WRITE(name, lock, \
|
||||
write_callback) \
|
||||
NV_DEFINE_SINGLE_PROCFS_FILE_HELPER(name, lock) \
|
||||
\
|
||||
static ssize_t nv_procfs_write_##name( \
|
||||
struct file *file, \
|
||||
const char __user *buf, \
|
||||
size_t size, \
|
||||
loff_t *ppos \
|
||||
) \
|
||||
{ \
|
||||
ssize_t ret; \
|
||||
struct seq_file *s; \
|
||||
\
|
||||
s = file->private_data; \
|
||||
if (s == NULL) \
|
||||
{ \
|
||||
return -EIO; \
|
||||
} \
|
||||
\
|
||||
ret = write_callback(s, buf + *ppos, size - *ppos); \
|
||||
if (ret == 0) \
|
||||
{ \
|
||||
/* avoid infinite loop */ \
|
||||
ret = -EIO; \
|
||||
} \
|
||||
return ret; \
|
||||
} \
|
||||
\
|
||||
static const nv_proc_ops_t nv_procfs_##name##_fops = { \
|
||||
NV_PROC_OPS_SET_OWNER() \
|
||||
.NV_PROC_OPS_OPEN = nv_procfs_open_##name, \
|
||||
.NV_PROC_OPS_READ = seq_read, \
|
||||
.NV_PROC_OPS_WRITE = nv_procfs_write_##name, \
|
||||
.NV_PROC_OPS_READ = nv_procfs_read_lock_##name, \
|
||||
.NV_PROC_OPS_LSEEK = seq_lseek, \
|
||||
.NV_PROC_OPS_RELEASE = nv_procfs_release_##name, \
|
||||
};
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -25,11 +25,9 @@
|
||||
#define _NV_PROTO_H_
|
||||
|
||||
#include "nv-pci.h"
|
||||
#include "nv-register-module.h"
|
||||
#include "nv-platform.h"
|
||||
|
||||
extern const char *nv_device_name;
|
||||
extern nvidia_module_t nv_fops;
|
||||
|
||||
void nv_acpi_register_notifier (nv_linux_state_t *);
|
||||
void nv_acpi_unregister_notifier (nv_linux_state_t *);
|
||||
@@ -44,7 +42,7 @@ void nv_procfs_remove_gpu (nv_linux_state_t *);
|
||||
|
||||
int nvidia_mmap (struct file *, struct vm_area_struct *);
|
||||
int nvidia_mmap_helper (nv_state_t *, nv_linux_file_private_t *, nvidia_stack_t *, struct vm_area_struct *, void *);
|
||||
int nv_encode_caching (pgprot_t *, NvU32, NvU32);
|
||||
int nv_encode_caching (pgprot_t *, NvU32, nv_memory_type_t);
|
||||
void nv_revoke_gpu_mappings_locked(nv_state_t *);
|
||||
|
||||
NvUPtr nv_vm_map_pages (struct page **, NvU32, NvBool, NvBool);
|
||||
@@ -59,9 +57,9 @@ int nv_uvm_init (void);
|
||||
void nv_uvm_exit (void);
|
||||
NV_STATUS nv_uvm_suspend (void);
|
||||
NV_STATUS nv_uvm_resume (void);
|
||||
void nv_uvm_notify_start_device (const NvU8 *uuid);
|
||||
void nv_uvm_notify_stop_device (const NvU8 *uuid);
|
||||
NV_STATUS nv_uvm_event_interrupt (const NvU8 *uuid);
|
||||
NV_STATUS nv_uvm_drain_P2P (const NvU8 *uuid);
|
||||
NV_STATUS nv_uvm_resume_P2P (const NvU8 *uuid);
|
||||
|
||||
/* Move these to nv.h once implemented by other UNIX platforms */
|
||||
NvBool nvidia_get_gpuid_list (NvU32 *gpu_ids, NvU32 *gpu_count);
|
||||
@@ -78,6 +76,8 @@ NV_STATUS nv_set_system_power_state (nv_power_state_t, nv_pm_action_depth_t)
|
||||
|
||||
void nvidia_modeset_suspend (NvU32 gpuId);
|
||||
void nvidia_modeset_resume (NvU32 gpuId);
|
||||
void nvidia_modeset_remove (NvU32 gpuId);
|
||||
void nvidia_modeset_probe (const nv_linux_state_t *nvl);
|
||||
NvBool nv_is_uuid_in_gpu_exclusion_list (const char *);
|
||||
|
||||
NV_STATUS nv_parse_per_device_option_string(nvidia_stack_t *sp);
|
||||
@@ -87,8 +87,11 @@ void nv_shutdown_adapter(nvidia_stack_t *, nv_state_t *, nv_linux_state
|
||||
void nv_dev_free_stacks(nv_linux_state_t *);
|
||||
NvBool nv_lock_init_locks(nvidia_stack_t *, nv_state_t *);
|
||||
void nv_lock_destroy_locks(nvidia_stack_t *, nv_state_t *);
|
||||
void nv_linux_add_device_locked(nv_linux_state_t *);
|
||||
int nv_linux_add_device_locked(nv_linux_state_t *);
|
||||
void nv_linux_remove_device_locked(nv_linux_state_t *);
|
||||
NvBool nv_acpi_power_resource_method_present(struct pci_dev *);
|
||||
|
||||
int nv_linux_init_open_q(nv_linux_state_t *);
|
||||
void nv_linux_stop_open_q(nv_linux_state_t *);
|
||||
|
||||
#endif /* _NV_PROTO_H_ */
|
||||
@@ -36,13 +36,6 @@
|
||||
#define NV_MAX_ISR_DELAY_MS (NV_MAX_ISR_DELAY_US / 1000)
|
||||
#define NV_NSECS_TO_JIFFIES(nsec) ((nsec) * HZ / 1000000000)
|
||||
|
||||
#if !defined(NV_TIMESPEC64_PRESENT)
|
||||
struct timespec64 {
|
||||
__s64 tv_sec;
|
||||
long tv_nsec;
|
||||
};
|
||||
#endif
|
||||
|
||||
#if !defined(NV_KTIME_GET_RAW_TS64_PRESENT)
|
||||
static inline void ktime_get_raw_ts64(struct timespec64 *ts64)
|
||||
{
|
||||
@@ -53,16 +46,6 @@ static inline void ktime_get_raw_ts64(struct timespec64 *ts64)
|
||||
}
|
||||
#endif
|
||||
|
||||
#if !defined(NV_KTIME_GET_REAL_TS64_PRESENT)
|
||||
static inline void ktime_get_real_ts64(struct timespec64 *ts64)
|
||||
{
|
||||
struct timeval tv;
|
||||
do_gettimeofday(&tv);
|
||||
ts64->tv_sec = tv.tv_sec;
|
||||
ts64->tv_nsec = tv.tv_usec * (NvU64) NSEC_PER_USEC;
|
||||
}
|
||||
#endif
|
||||
|
||||
static NvBool nv_timer_less_than
|
||||
(
|
||||
const struct timespec64 *a,
|
||||
@@ -73,49 +56,6 @@ static NvBool nv_timer_less_than
|
||||
: (a->tv_sec < b->tv_sec);
|
||||
}
|
||||
|
||||
#if !defined(NV_TIMESPEC64_PRESENT)
|
||||
static inline struct timespec64 timespec64_add
|
||||
(
|
||||
const struct timespec64 a,
|
||||
const struct timespec64 b
|
||||
)
|
||||
{
|
||||
struct timespec64 result;
|
||||
|
||||
result.tv_sec = a.tv_sec + b.tv_sec;
|
||||
result.tv_nsec = a.tv_nsec + b.tv_nsec;
|
||||
while (result.tv_nsec >= NSEC_PER_SEC)
|
||||
{
|
||||
++result.tv_sec;
|
||||
result.tv_nsec -= NSEC_PER_SEC;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
static inline struct timespec64 timespec64_sub
|
||||
(
|
||||
const struct timespec64 a,
|
||||
const struct timespec64 b
|
||||
)
|
||||
{
|
||||
struct timespec64 result;
|
||||
|
||||
result.tv_sec = a.tv_sec - b.tv_sec;
|
||||
result.tv_nsec = a.tv_nsec - b.tv_nsec;
|
||||
while (result.tv_nsec < 0)
|
||||
{
|
||||
--(result.tv_sec);
|
||||
result.tv_nsec += NSEC_PER_SEC;
|
||||
}
|
||||
return result;
|
||||
}
|
||||
|
||||
static inline s64 timespec64_to_ns(struct timespec64 *ts)
|
||||
{
|
||||
return ((s64) ts->tv_sec * NSEC_PER_SEC) + ts->tv_nsec;
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline NvU64 nv_ktime_get_raw_ns(void)
|
||||
{
|
||||
struct timespec64 ts;
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2017-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -42,24 +42,20 @@ static inline void nv_timer_callback_typed_data(struct timer_list *timer)
|
||||
nv_timer->nv_timer_callback(nv_timer);
|
||||
}
|
||||
|
||||
static inline void nv_timer_callback_anon_data(unsigned long arg)
|
||||
{
|
||||
struct nv_timer *nv_timer = (struct nv_timer *)arg;
|
||||
|
||||
nv_timer->nv_timer_callback(nv_timer);
|
||||
}
|
||||
|
||||
static inline void nv_timer_setup(struct nv_timer *nv_timer,
|
||||
void (*callback)(struct nv_timer *nv_timer))
|
||||
{
|
||||
nv_timer->nv_timer_callback = callback;
|
||||
|
||||
#if defined(NV_TIMER_SETUP_PRESENT)
|
||||
timer_setup(&nv_timer->kernel_timer, nv_timer_callback_typed_data, 0);
|
||||
}
|
||||
|
||||
static inline void nv_timer_delete_sync(struct timer_list *timer)
|
||||
{
|
||||
#if !defined(NV_BSD) && NV_IS_EXPORT_SYMBOL_PRESENT_timer_delete_sync
|
||||
timer_delete_sync(timer);
|
||||
#else
|
||||
init_timer(&nv_timer->kernel_timer);
|
||||
nv_timer->kernel_timer.function = nv_timer_callback_anon_data;
|
||||
nv_timer->kernel_timer.data = (unsigned long)nv_timer;
|
||||
del_timer_sync(timer);
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -42,7 +42,9 @@
|
||||
#include <nv-caps.h>
|
||||
#include <nv-firmware.h>
|
||||
#include <nv-ioctl.h>
|
||||
#include <nv-ioctl-numa.h>
|
||||
#include <nvmisc.h>
|
||||
#include <os/nv_memory_area.h>
|
||||
|
||||
extern nv_cap_t *nvidia_caps_root;
|
||||
|
||||
@@ -53,9 +55,6 @@ extern const NvBool nv_is_rm_firmware_supported_os;
|
||||
|
||||
#include <nv-kernel-interface-api.h>
|
||||
|
||||
/* NVIDIA's reserved major character device number (Linux). */
|
||||
#define NV_MAJOR_DEVICE_NUMBER 195
|
||||
|
||||
#define GPU_UUID_LEN (16)
|
||||
|
||||
/*
|
||||
@@ -87,6 +86,20 @@ extern const NvBool nv_is_rm_firmware_supported_os;
|
||||
|
||||
#define NV_RM_DEVICE_INTR_ADDRESS 0x100
|
||||
|
||||
#define NV_TEGRA_PCI_IGPU_PG_MASK_DEFAULT 0xFFFFFFFF
|
||||
|
||||
/*
|
||||
* Clock domain identifier, which is used for fetching the engine
|
||||
* load backed by the specified clock domain for Tegra platforms
|
||||
* conforming linux devfreq framework to realize dynamic frequency
|
||||
* scaling.
|
||||
*/
|
||||
typedef enum _TEGRASOC_DEVFREQ_CLK
|
||||
{
|
||||
TEGRASOC_DEVFREQ_CLK_GPC,
|
||||
TEGRASOC_DEVFREQ_CLK_NVD,
|
||||
} TEGRASOC_DEVFREQ_CLK;
|
||||
|
||||
/*!
|
||||
* @brief The order of the display clocks in the below defined enum
|
||||
* should be synced with below mapping array and macro.
|
||||
@@ -109,27 +122,47 @@ typedef enum _TEGRASOC_WHICH_CLK
|
||||
TEGRASOC_WHICH_CLK_NVDISPLAY_DISP,
|
||||
TEGRASOC_WHICH_CLK_NVDISPLAY_P0,
|
||||
TEGRASOC_WHICH_CLK_NVDISPLAY_P1,
|
||||
TEGRASOC_WHICH_CLK_NVDISPLAY_P2,
|
||||
TEGRASOC_WHICH_CLK_NVDISPLAY_P3,
|
||||
TEGRASOC_WHICH_CLK_NVDISPLAY_P4,
|
||||
TEGRASOC_WHICH_CLK_NVDISPLAY_P5,
|
||||
TEGRASOC_WHICH_CLK_NVDISPLAY_P6,
|
||||
TEGRASOC_WHICH_CLK_NVDISPLAY_P7,
|
||||
TEGRASOC_WHICH_CLK_DPAUX0,
|
||||
TEGRASOC_WHICH_CLK_FUSE,
|
||||
TEGRASOC_WHICH_CLK_DSIPLL_VCO,
|
||||
TEGRASOC_WHICH_CLK_DSIPLL_CLKOUTPN,
|
||||
TEGRASOC_WHICH_CLK_DSIPLL_CLKOUTA,
|
||||
TEGRASOC_WHICH_CLK_SPPLL0_VCO,
|
||||
TEGRASOC_WHICH_CLK_SPPLL0_CLKOUTPN,
|
||||
TEGRASOC_WHICH_CLK_SPPLL0_CLKOUTA,
|
||||
TEGRASOC_WHICH_CLK_SPPLL0_CLKOUTB,
|
||||
TEGRASOC_WHICH_CLK_SPPLL0_CLKOUTPN,
|
||||
TEGRASOC_WHICH_CLK_SPPLL1_CLKOUTPN,
|
||||
TEGRASOC_WHICH_CLK_SPPLL0_DIV27,
|
||||
TEGRASOC_WHICH_CLK_SPPLL1_DIV27,
|
||||
TEGRASOC_WHICH_CLK_SPPLL0_DIV10,
|
||||
TEGRASOC_WHICH_CLK_SPPLL0_DIV25,
|
||||
TEGRASOC_WHICH_CLK_SPPLL0_DIV27,
|
||||
TEGRASOC_WHICH_CLK_SPPLL1_VCO,
|
||||
TEGRASOC_WHICH_CLK_SPPLL1_CLKOUTPN,
|
||||
TEGRASOC_WHICH_CLK_SPPLL1_DIV27,
|
||||
TEGRASOC_WHICH_CLK_SPPLL0,
|
||||
TEGRASOC_WHICH_CLK_SPPLL1,
|
||||
TEGRASOC_WHICH_CLK_VPLL0_REF,
|
||||
TEGRASOC_WHICH_CLK_VPLL0,
|
||||
TEGRASOC_WHICH_CLK_VPLL1,
|
||||
TEGRASOC_WHICH_CLK_VPLL2,
|
||||
TEGRASOC_WHICH_CLK_VPLL3,
|
||||
TEGRASOC_WHICH_CLK_VPLL4,
|
||||
TEGRASOC_WHICH_CLK_VPLL5,
|
||||
TEGRASOC_WHICH_CLK_VPLL6,
|
||||
TEGRASOC_WHICH_CLK_VPLL7,
|
||||
TEGRASOC_WHICH_CLK_NVDISPLAY_P0_REF,
|
||||
TEGRASOC_WHICH_CLK_RG0,
|
||||
TEGRASOC_WHICH_CLK_RG1,
|
||||
TEGRASOC_WHICH_CLK_RG2,
|
||||
TEGRASOC_WHICH_CLK_RG3,
|
||||
TEGRASOC_WHICH_CLK_RG4,
|
||||
TEGRASOC_WHICH_CLK_RG5,
|
||||
TEGRASOC_WHICH_CLK_RG6,
|
||||
TEGRASOC_WHICH_CLK_RG7,
|
||||
TEGRASOC_WHICH_CLK_DISPPLL,
|
||||
TEGRASOC_WHICH_CLK_DISPHUBPLL,
|
||||
TEGRASOC_WHICH_CLK_DSI_LP,
|
||||
@@ -137,9 +170,20 @@ typedef enum _TEGRASOC_WHICH_CLK
|
||||
TEGRASOC_WHICH_CLK_DSI_PIXEL,
|
||||
TEGRASOC_WHICH_CLK_PRE_SOR0,
|
||||
TEGRASOC_WHICH_CLK_PRE_SOR1,
|
||||
TEGRASOC_WHICH_CLK_DP_LINK_REF,
|
||||
TEGRASOC_WHICH_CLK_PRE_SOR2,
|
||||
TEGRASOC_WHICH_CLK_PRE_SOR3,
|
||||
TEGRASOC_WHICH_CLK_DP_LINKA_REF,
|
||||
TEGRASOC_WHICH_CLK_DP_LINKB_REF,
|
||||
TEGRASOC_WHICH_CLK_DP_LINKC_REF,
|
||||
TEGRASOC_WHICH_CLK_DP_LINKD_REF,
|
||||
TEGRASOC_WHICH_CLK_SOR_LINKA_INPUT,
|
||||
TEGRASOC_WHICH_CLK_SOR_LINKB_INPUT,
|
||||
TEGRASOC_WHICH_CLK_SOR_LINKC_INPUT,
|
||||
TEGRASOC_WHICH_CLK_SOR_LINKD_INPUT,
|
||||
TEGRASOC_WHICH_CLK_SOR_LINKA_AFIFO,
|
||||
TEGRASOC_WHICH_CLK_SOR_LINKB_AFIFO,
|
||||
TEGRASOC_WHICH_CLK_SOR_LINKC_AFIFO,
|
||||
TEGRASOC_WHICH_CLK_SOR_LINKD_AFIFO,
|
||||
TEGRASOC_WHICH_CLK_SOR_LINKA_AFIFO_M,
|
||||
TEGRASOC_WHICH_CLK_RG0_M,
|
||||
TEGRASOC_WHICH_CLK_RG1_M,
|
||||
@@ -148,17 +192,36 @@ typedef enum _TEGRASOC_WHICH_CLK
|
||||
TEGRASOC_WHICH_CLK_PLLHUB,
|
||||
TEGRASOC_WHICH_CLK_SOR0,
|
||||
TEGRASOC_WHICH_CLK_SOR1,
|
||||
TEGRASOC_WHICH_CLK_SOR_PAD_INPUT,
|
||||
TEGRASOC_WHICH_CLK_SOR2,
|
||||
TEGRASOC_WHICH_CLK_SOR3,
|
||||
TEGRASOC_WHICH_CLK_SOR_PADA_INPUT,
|
||||
TEGRASOC_WHICH_CLK_SOR_PADB_INPUT,
|
||||
TEGRASOC_WHICH_CLK_SOR_PADC_INPUT,
|
||||
TEGRASOC_WHICH_CLK_SOR_PADD_INPUT,
|
||||
TEGRASOC_WHICH_CLK_SOR0_PAD,
|
||||
TEGRASOC_WHICH_CLK_SOR1_PAD,
|
||||
TEGRASOC_WHICH_CLK_SOR2_PAD,
|
||||
TEGRASOC_WHICH_CLK_SOR3_PAD,
|
||||
TEGRASOC_WHICH_CLK_PRE_SF0,
|
||||
TEGRASOC_WHICH_CLK_SF0,
|
||||
TEGRASOC_WHICH_CLK_SF1,
|
||||
TEGRASOC_WHICH_CLK_SF2,
|
||||
TEGRASOC_WHICH_CLK_SF3,
|
||||
TEGRASOC_WHICH_CLK_SF4,
|
||||
TEGRASOC_WHICH_CLK_SF5,
|
||||
TEGRASOC_WHICH_CLK_SF6,
|
||||
TEGRASOC_WHICH_CLK_SF7,
|
||||
TEGRASOC_WHICH_CLK_DSI_PAD_INPUT,
|
||||
TEGRASOC_WHICH_CLK_PRE_SOR0_REF,
|
||||
TEGRASOC_WHICH_CLK_PRE_SOR1_REF,
|
||||
TEGRASOC_WHICH_CLK_SOR0_PLL_REF,
|
||||
TEGRASOC_WHICH_CLK_SOR1_PLL_REF,
|
||||
TEGRASOC_WHICH_CLK_SOR2_PLL_REF,
|
||||
TEGRASOC_WHICH_CLK_SOR3_PLL_REF,
|
||||
TEGRASOC_WHICH_CLK_SOR0_REF,
|
||||
TEGRASOC_WHICH_CLK_SOR1_REF,
|
||||
TEGRASOC_WHICH_CLK_SOR2_REF,
|
||||
TEGRASOC_WHICH_CLK_SOR3_REF,
|
||||
TEGRASOC_WHICH_CLK_OSC,
|
||||
TEGRASOC_WHICH_CLK_DSC,
|
||||
TEGRASOC_WHICH_CLK_MAUD,
|
||||
@@ -167,11 +230,35 @@ typedef enum _TEGRASOC_WHICH_CLK
|
||||
TEGRASOC_WHICH_CLK_MIPI_CAL,
|
||||
TEGRASOC_WHICH_CLK_UART_FST_MIPI_CAL,
|
||||
TEGRASOC_WHICH_CLK_SOR0_DIV,
|
||||
TEGRASOC_WHICH_CLK_SOR1_DIV,
|
||||
TEGRASOC_WHICH_CLK_SOR2_DIV,
|
||||
TEGRASOC_WHICH_CLK_SOR3_DIV,
|
||||
TEGRASOC_WHICH_CLK_DISP_ROOT,
|
||||
TEGRASOC_WHICH_CLK_HUB_ROOT,
|
||||
TEGRASOC_WHICH_CLK_PLLA_DISP,
|
||||
TEGRASOC_WHICH_CLK_PLLA_DISPHUB,
|
||||
TEGRASOC_WHICH_CLK_PLLA,
|
||||
TEGRASOC_WHICH_CLK_VPLLX_SOR0_MUXED,
|
||||
TEGRASOC_WHICH_CLK_VPLLX_SOR1_MUXED,
|
||||
TEGRASOC_WHICH_CLK_VPLLX_SOR2_MUXED,
|
||||
TEGRASOC_WHICH_CLK_VPLLX_SOR3_MUXED,
|
||||
TEGRASOC_WHICH_CLK_SF0_SOR,
|
||||
TEGRASOC_WHICH_CLK_SF1_SOR,
|
||||
TEGRASOC_WHICH_CLK_SF2_SOR,
|
||||
TEGRASOC_WHICH_CLK_SF3_SOR,
|
||||
TEGRASOC_WHICH_CLK_SF4_SOR,
|
||||
TEGRASOC_WHICH_CLK_SF5_SOR,
|
||||
TEGRASOC_WHICH_CLK_SF6_SOR,
|
||||
TEGRASOC_WHICH_CLK_SF7_SOR,
|
||||
TEGRASOC_WHICH_CLK_EMC,
|
||||
TEGRASOC_WHICH_CLK_GPU_FIRST,
|
||||
TEGRASOC_WHICH_CLK_GPU_SYS = TEGRASOC_WHICH_CLK_GPU_FIRST,
|
||||
TEGRASOC_WHICH_CLK_GPU_NVD,
|
||||
TEGRASOC_WHICH_CLK_GPU_UPROC,
|
||||
TEGRASOC_WHICH_CLK_GPU_GPC0,
|
||||
TEGRASOC_WHICH_CLK_GPU_GPC1,
|
||||
TEGRASOC_WHICH_CLK_GPU_GPC2,
|
||||
TEGRASOC_WHICH_CLK_GPU_LAST = TEGRASOC_WHICH_CLK_GPU_GPC2,
|
||||
TEGRASOC_WHICH_CLK_MAX, // TEGRASOC_WHICH_CLK_MAX is defined for boundary checks only.
|
||||
} TEGRASOC_WHICH_CLK;
|
||||
|
||||
@@ -226,7 +313,6 @@ typedef struct
|
||||
#define NV_RM_PAGE_MASK (NV_RM_PAGE_SIZE - 1)
|
||||
|
||||
#define NV_RM_TO_OS_PAGE_SHIFT (os_page_shift - NV_RM_PAGE_SHIFT)
|
||||
#define NV_RM_PAGES_PER_OS_PAGE (1U << NV_RM_TO_OS_PAGE_SHIFT)
|
||||
#define NV_RM_PAGES_TO_OS_PAGES(count) \
|
||||
((((NvUPtr)(count)) >> NV_RM_TO_OS_PAGE_SHIFT) + \
|
||||
((((count) & ((1 << NV_RM_TO_OS_PAGE_SHIFT) - 1)) != 0) ? 1 : 0))
|
||||
@@ -285,11 +371,9 @@ typedef struct nv_usermap_access_params_s
|
||||
NvU64 offset;
|
||||
NvU64 *page_array;
|
||||
NvU64 num_pages;
|
||||
NvU64 mmap_start;
|
||||
NvU64 mmap_size;
|
||||
MemoryArea memArea;
|
||||
NvU64 access_start;
|
||||
NvU64 access_size;
|
||||
NvU64 remap_prot_extra;
|
||||
NvBool contig;
|
||||
NvU32 caching;
|
||||
} nv_usermap_access_params_t;
|
||||
@@ -302,11 +386,9 @@ typedef struct nv_alloc_mapping_context_s {
|
||||
NvU64 page_index;
|
||||
NvU64 *page_array;
|
||||
NvU64 num_pages;
|
||||
NvU64 mmap_start;
|
||||
NvU64 mmap_size;
|
||||
MemoryArea memArea;
|
||||
NvU64 access_start;
|
||||
NvU64 access_size;
|
||||
NvU64 remap_prot_extra;
|
||||
NvU32 prot;
|
||||
NvBool valid;
|
||||
NvU32 caching;
|
||||
@@ -319,6 +401,8 @@ typedef enum
|
||||
NV_SOC_IRQ_GPIO_TYPE,
|
||||
NV_SOC_IRQ_HDACODEC_TYPE,
|
||||
NV_SOC_IRQ_TCPC2DISP_TYPE,
|
||||
NV_SOC_IRQ_HFRP0_TYPE,
|
||||
NV_SOC_IRQ_HFRP1_TYPE,
|
||||
NV_SOC_IRQ_INVALID_TYPE
|
||||
} nv_soc_irq_type_t;
|
||||
|
||||
@@ -336,13 +420,12 @@ typedef struct nv_soc_irq_info_s {
|
||||
NvS32 ref_count;
|
||||
} nv_soc_irq_info_t;
|
||||
|
||||
#define NV_MAX_SOC_IRQS 6
|
||||
#define NV_MAX_SOC_IRQS 10
|
||||
#define NV_MAX_DPAUX_NUM_DEVICES 4
|
||||
#define NV_MAX_SOC_DPAUX_NUM_DEVICES 2 // From SOC_DEV_MAPPING
|
||||
#define NV_MAX_DPAUX_DEV_NAME_SIZE 10
|
||||
|
||||
#define NV_MAX_SOC_DPAUX_NUM_DEVICES 4
|
||||
|
||||
#define NV_IGPU_LEGACY_STALL_IRQ 70
|
||||
#define NV_IGPU_MAX_STALL_IRQS 3
|
||||
#define NV_IGPU_MAX_NONSTALL_IRQS 1
|
||||
/*
|
||||
* per device state
|
||||
*/
|
||||
@@ -373,6 +456,8 @@ typedef struct nv_state_t
|
||||
{
|
||||
NvBool valid;
|
||||
NvU8 uuid[GPU_UUID_LEN];
|
||||
NvBool pci_uuid_read_attempted;
|
||||
NV_STATUS pci_uuid_status;
|
||||
} nv_uuid_cache;
|
||||
void *handle;
|
||||
|
||||
@@ -384,28 +469,35 @@ typedef struct nv_state_t
|
||||
nv_aperture_t *dpaux[NV_MAX_DPAUX_NUM_DEVICES];
|
||||
nv_aperture_t *hdacodec_regs;
|
||||
nv_aperture_t *mipical_regs;
|
||||
nv_aperture_t *hfrp0_regs;
|
||||
nv_aperture_t *hfrp1_regs;
|
||||
nv_aperture_t *fb, ud;
|
||||
nv_aperture_t *simregs;
|
||||
nv_aperture_t *emc_regs;
|
||||
|
||||
NvU32 num_dpaux_instance;
|
||||
NvU32 interrupt_line;
|
||||
NvU32 dpaux_irqs[NV_MAX_DPAUX_NUM_DEVICES];
|
||||
char dpaux_devname[NV_MAX_DPAUX_NUM_DEVICES][NV_MAX_DPAUX_DEV_NAME_SIZE];
|
||||
nv_soc_irq_info_t soc_irq_info[NV_MAX_SOC_IRQS];
|
||||
NvS32 current_soc_irq;
|
||||
NvU32 num_soc_irqs;
|
||||
NvU32 hdacodec_irq;
|
||||
NvU32 tcpc2disp_irq;
|
||||
NvU32 hfrp0_irq;
|
||||
NvU32 hfrp1_irq;
|
||||
NvU8 *soc_dcb_blob;
|
||||
NvU32 soc_dcb_size;
|
||||
NvU32 disp_sw_soc_chip_id;
|
||||
NvBool soc_is_dpalt_mode_supported;
|
||||
NvBool soc_is_hfrp_supported;
|
||||
|
||||
NvU32 igpu_stall_irq[NV_IGPU_MAX_STALL_IRQS];
|
||||
NvU32 igpu_nonstall_irq;
|
||||
NvU32 num_stall_irqs;
|
||||
NvU64 dma_mask;
|
||||
|
||||
|
||||
NvBool is_tegra_pci_igpu;
|
||||
NvBool supports_tegra_igpu_rg;
|
||||
NvBool is_tegra_pci_igpu_rg_enabled;
|
||||
NvU32 tegra_pci_igpu_pg_mask;
|
||||
|
||||
NvBool primary_vga;
|
||||
|
||||
NvU32 sim_env;
|
||||
@@ -472,17 +564,9 @@ typedef struct nv_state_t
|
||||
NvHandle hDisp;
|
||||
} rmapi;
|
||||
|
||||
/* Bool to check if ISO iommu enabled */
|
||||
NvBool iso_iommu_present;
|
||||
|
||||
/* Bool to check if NISO iommu enabled */
|
||||
NvBool niso_iommu_present;
|
||||
|
||||
/* Bool to check if dma-buf is supported */
|
||||
NvBool dma_buf_supported;
|
||||
|
||||
NvBool printed_openrm_enable_unsupported_gpus_error;
|
||||
|
||||
/* Check if NVPCF DSM function is implemented under NVPCF or GPU device scope */
|
||||
NvBool nvpcf_dsm_in_gpu_scope;
|
||||
|
||||
@@ -491,13 +575,41 @@ typedef struct nv_state_t
|
||||
|
||||
/* Bool to check if the GPU has a coherent sysmem link */
|
||||
NvBool coherent;
|
||||
} nv_state_t;
|
||||
|
||||
// These define need to be in sync with defines in system.h
|
||||
#define OS_TYPE_LINUX 0x1
|
||||
#define OS_TYPE_FREEBSD 0x2
|
||||
#define OS_TYPE_SUNOS 0x3
|
||||
#define OS_TYPE_VMWARE 0x4
|
||||
/*
|
||||
* Bool to check if GPU memory is backed by struct page.
|
||||
* False for non-coherent platforms. May also be false
|
||||
* on coherent platforms if GPU memory is not onlined to the kernel.
|
||||
*/
|
||||
NvBool mem_has_struct_page;
|
||||
|
||||
/* OS detected GPU has ATS capability */
|
||||
NvBool ats_support;
|
||||
/*
|
||||
* NUMA node ID of the CPU to which the GPU is attached.
|
||||
* Holds NUMA_NO_NODE on platforms that don't support NUMA configuration.
|
||||
*/
|
||||
NvS32 cpu_numa_node_id;
|
||||
|
||||
struct {
|
||||
/* Bool to check if ISO iommu enabled */
|
||||
NvBool iso_iommu_present;
|
||||
/* Bool to check if NISO iommu enabled */
|
||||
NvBool niso_iommu_present;
|
||||
/* Display SMMU Stream IDs */
|
||||
NvU32 dispIsoStreamId;
|
||||
NvU32 dispNisoStreamId;
|
||||
} iommus;
|
||||
|
||||
struct {
|
||||
NvU32 max_dispclk_rate_using_disppllkhz;
|
||||
NvU32 max_dispclk_rate_using_sppll0clkoutakhz;
|
||||
NvU32 max_hubclk_rate_using_sppll0clkoutbkhz;
|
||||
} clocks;
|
||||
|
||||
/* Console is managed by drm drivers or NVKMS */
|
||||
NvBool client_managed_console;
|
||||
} nv_state_t;
|
||||
|
||||
#define NVFP_TYPE_NONE 0x0
|
||||
#define NVFP_TYPE_REFCOUNTED 0x1
|
||||
@@ -508,6 +620,7 @@ struct nv_file_private_t
|
||||
NvHandle *handles;
|
||||
NvU16 maxHandles;
|
||||
NvU32 deviceInstance;
|
||||
NvU32 gpuInstanceId;
|
||||
NvU8 metadata[64];
|
||||
|
||||
nv_file_private_t *ctl_nvfp;
|
||||
@@ -536,16 +649,18 @@ typedef struct UvmGpuAddressSpaceInfo_tag *nvgpuAddressSpaceInfo_t;
|
||||
typedef struct UvmGpuAllocInfo_tag *nvgpuAllocInfo_t;
|
||||
typedef struct UvmGpuP2PCapsParams_tag *nvgpuP2PCapsParams_t;
|
||||
typedef struct UvmGpuFbInfo_tag *nvgpuFbInfo_t;
|
||||
typedef struct UvmGpuNvlinkInfo_tag *nvgpuNvlinkInfo_t;
|
||||
typedef struct UvmGpuEccInfo_tag *nvgpuEccInfo_t;
|
||||
typedef struct UvmGpuFaultInfo_tag *nvgpuFaultInfo_t;
|
||||
typedef struct UvmGpuAccessCntrInfo_tag *nvgpuAccessCntrInfo_t;
|
||||
typedef struct UvmGpuAccessCntrConfig_tag *nvgpuAccessCntrConfig_t;
|
||||
typedef struct UvmGpuInfo_tag nvgpuInfo_t;
|
||||
typedef struct UvmGpuClientInfo_tag nvgpuClientInfo_t;
|
||||
typedef struct UvmGpuAccessCntrConfig_tag nvgpuAccessCntrConfig_t;
|
||||
typedef struct UvmGpuInfo_tag nvgpuInfo_t;
|
||||
typedef struct UvmGpuClientInfo_tag nvgpuClientInfo_t;
|
||||
typedef struct UvmPmaAllocationOptions_tag *nvgpuPmaAllocationOptions_t;
|
||||
typedef struct UvmPmaStatistics_tag *nvgpuPmaStatistics_t;
|
||||
typedef struct UvmGpuMemoryInfo_tag *nvgpuMemoryInfo_t;
|
||||
typedef struct UvmGpuExternalMappingInfo_tag *nvgpuExternalMappingInfo_t;
|
||||
typedef struct UvmGpuExternalPhysAddrInfo_tag *nvgpuExternalPhysAddrInfo_t;
|
||||
typedef struct UvmGpuChannelResourceInfo_tag *nvgpuChannelResourceInfo_t;
|
||||
typedef struct UvmGpuChannelInstanceInfo_tag *nvgpuChannelInstanceInfo_t;
|
||||
typedef struct UvmGpuChannelResourceBindParams_tag *nvgpuChannelResourceBindParams_t;
|
||||
@@ -560,23 +675,24 @@ typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64, nvgpuGpuMemor
|
||||
* flags
|
||||
*/
|
||||
|
||||
#define NV_FLAG_OPEN 0x0001
|
||||
#define NV_FLAG_EXCLUDE 0x0002
|
||||
#define NV_FLAG_CONTROL 0x0004
|
||||
// Unused 0x0008
|
||||
#define NV_FLAG_SOC_DISPLAY 0x0010
|
||||
#define NV_FLAG_USES_MSI 0x0020
|
||||
#define NV_FLAG_USES_MSIX 0x0040
|
||||
#define NV_FLAG_PASSTHRU 0x0080
|
||||
#define NV_FLAG_SUSPENDED 0x0100
|
||||
#define NV_FLAG_SOC_IGPU 0x0200
|
||||
// Unused 0x0400
|
||||
#define NV_FLAG_PERSISTENT_SW_STATE 0x0800
|
||||
#define NV_FLAG_IN_RECOVERY 0x1000
|
||||
// Unused 0x2000
|
||||
#define NV_FLAG_UNBIND_LOCK 0x4000
|
||||
#define NV_FLAG_OPEN 0x0001
|
||||
#define NV_FLAG_EXCLUDE 0x0002
|
||||
#define NV_FLAG_CONTROL 0x0004
|
||||
#define NV_FLAG_PCI_P2P_UNSUPPORTED_CHIPSET 0x0008
|
||||
#define NV_FLAG_SOC_DISPLAY 0x0010
|
||||
#define NV_FLAG_USES_MSI 0x0020
|
||||
#define NV_FLAG_USES_MSIX 0x0040
|
||||
#define NV_FLAG_PASSTHRU 0x0080
|
||||
#define NV_FLAG_SUSPENDED 0x0100
|
||||
#define NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT 0x0200
|
||||
/* To be set when an FLR needs to be triggered after device shut down. */
|
||||
#define NV_FLAG_TRIGGER_FLR 0x0400
|
||||
#define NV_FLAG_PERSISTENT_SW_STATE 0x0800
|
||||
#define NV_FLAG_IN_RECOVERY 0x1000
|
||||
#define NV_FLAG_PCI_REMOVE_IN_PROGRESS 0x2000
|
||||
#define NV_FLAG_UNBIND_LOCK 0x4000
|
||||
/* To be set when GPU is not present on the bus, to help device teardown */
|
||||
#define NV_FLAG_IN_SURPRISE_REMOVAL 0x8000
|
||||
#define NV_FLAG_IN_SURPRISE_REMOVAL 0x8000
|
||||
|
||||
typedef enum
|
||||
{
|
||||
@@ -606,23 +722,63 @@ typedef enum
|
||||
NV_POWER_STATE_RUNNING
|
||||
} nv_power_state_t;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
const char *vidmem_power_status;
|
||||
const char *dynamic_power_status;
|
||||
const char *gc6_support;
|
||||
const char *gcoff_support;
|
||||
const char *s0ix_status;
|
||||
const char *db_support;
|
||||
} nv_power_info_t;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
NV_MEMORY_TYPE_SYSTEM, /* Memory mapped for ROM, SBIOS and physical RAM. */
|
||||
NV_MEMORY_TYPE_REGISTERS,
|
||||
NV_MEMORY_TYPE_FRAMEBUFFER,
|
||||
NV_MEMORY_TYPE_DEVICE_MMIO, /* All kinds of MMIO referred by NVRM e.g. BARs and MCFG of device */
|
||||
} nv_memory_type_t;
|
||||
|
||||
typedef struct nv_allocation_request_s
|
||||
{
|
||||
NvU32 count;
|
||||
NvU64 page_size;
|
||||
NvBool alloc_type_contiguous;
|
||||
NvU32 cache_type;
|
||||
NvBool alloc_type_zeroed;
|
||||
NvBool unencrypted;
|
||||
NvBool no_reclaim;
|
||||
NvS32 node_id;
|
||||
NvU64 *pte_array;
|
||||
void **private;
|
||||
} nv_allocation_request_t;
|
||||
|
||||
#define NV_PRIMARY_VGA(nv) ((nv)->primary_vga)
|
||||
|
||||
#define NV_IS_CTL_DEVICE(nv) ((nv)->flags & NV_FLAG_CONTROL)
|
||||
#define NV_IS_SOC_DISPLAY_DEVICE(nv) \
|
||||
((nv)->flags & NV_FLAG_SOC_DISPLAY)
|
||||
|
||||
#define NV_IS_SOC_IGPU_DEVICE(nv) \
|
||||
((nv)->flags & NV_FLAG_SOC_IGPU)
|
||||
|
||||
#define NV_IS_DEVICE_IN_SURPRISE_REMOVAL(nv) \
|
||||
(((nv)->flags & NV_FLAG_IN_SURPRISE_REMOVAL) != 0)
|
||||
|
||||
#define NV_HAS_CONSOLE_IN_SYSMEM_CARVEOUT(nv) \
|
||||
(((nv)->flags & NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT) != 0)
|
||||
|
||||
/*
|
||||
* For console setup by EFI GOP, the base address is BAR1.
|
||||
* For console setup by VBIOS, the base address is BAR2 + 16MB.
|
||||
*/
|
||||
#define NV_IS_CONSOLE_MAPPED(nv, addr) \
|
||||
(((addr) == (nv)->bars[NV_GPU_BAR_INDEX_FB].cpu_address) || \
|
||||
((addr) == ((nv)->bars[NV_GPU_BAR_INDEX_IMEM].cpu_address + 0x1000000)))
|
||||
|
||||
#define NV_SOC_IS_ISO_IOMMU_PRESENT(nv) \
|
||||
((nv)->iso_iommu_present)
|
||||
((nv)->iommus.iso_iommu_present)
|
||||
|
||||
#define NV_SOC_IS_NISO_IOMMU_PRESENT(nv) \
|
||||
((nv)->niso_iommu_present)
|
||||
((nv)->iommus.niso_iommu_present)
|
||||
/*
|
||||
* GPU add/remove events
|
||||
*/
|
||||
@@ -741,6 +897,7 @@ static inline NvBool IS_IMEM_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length)
|
||||
#define NV_ALIGN_DOWN(v,g) ((v) & ~((g) - 1))
|
||||
#endif
|
||||
|
||||
|
||||
/*
|
||||
* driver internal interfaces
|
||||
*/
|
||||
@@ -755,9 +912,9 @@ static inline NvBool IS_IMEM_OFFSET(nv_state_t *nv, NvU64 offset, NvU64 length)
|
||||
|
||||
NvU32 NV_API_CALL nv_get_dev_minor (nv_state_t *);
|
||||
void* NV_API_CALL nv_alloc_kernel_mapping (nv_state_t *, void *, NvU64, NvU32, NvU64, void **);
|
||||
NV_STATUS NV_API_CALL nv_free_kernel_mapping (nv_state_t *, void *, void *, void *);
|
||||
void NV_API_CALL nv_free_kernel_mapping (nv_state_t *, void *, void *, void *);
|
||||
NV_STATUS NV_API_CALL nv_alloc_user_mapping (nv_state_t *, void *, NvU64, NvU32, NvU64, NvU32, NvU64 *, void **);
|
||||
NV_STATUS NV_API_CALL nv_free_user_mapping (nv_state_t *, void *, NvU64, void *);
|
||||
void NV_API_CALL nv_free_user_mapping (nv_state_t *, void *, NvU64, void *);
|
||||
NV_STATUS NV_API_CALL nv_add_mapping_context_to_file (nv_state_t *, nv_usermap_access_params_t*, NvU32, void *, NvU64, NvU32);
|
||||
|
||||
NvU64 NV_API_CALL nv_get_kern_phys_address (NvU64);
|
||||
@@ -767,11 +924,11 @@ nv_state_t* NV_API_CALL nv_get_ctl_state (void);
|
||||
|
||||
void NV_API_CALL nv_set_dma_address_size (nv_state_t *, NvU32 );
|
||||
|
||||
NV_STATUS NV_API_CALL nv_alias_pages (nv_state_t *, NvU32, NvU32, NvU32, NvU64, NvU64 *, void **);
|
||||
NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvBool, NvU32, NvBool, NvBool, NvS32, NvU64 *, void **);
|
||||
NV_STATUS NV_API_CALL nv_alias_pages (nv_state_t *, NvU32, NvU64, NvU32, NvU32, NvU64, NvU64 *, NvBool, void **);
|
||||
NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, nv_allocation_request_t *);
|
||||
NV_STATUS NV_API_CALL nv_free_pages (nv_state_t *, NvU32, NvBool, NvU32, void *);
|
||||
|
||||
NV_STATUS NV_API_CALL nv_register_user_pages (nv_state_t *, NvU64, NvU64 *, void *, void **);
|
||||
NV_STATUS NV_API_CALL nv_register_user_pages (nv_state_t *, NvU64, NvU64 *, void *, void **, NvBool);
|
||||
void NV_API_CALL nv_unregister_user_pages (nv_state_t *, NvU64, void **, void **);
|
||||
|
||||
NV_STATUS NV_API_CALL nv_register_peer_io_mem (nv_state_t *, NvU64 *, NvU64, void **);
|
||||
@@ -779,26 +936,26 @@ void NV_API_CALL nv_unregister_peer_io_mem(nv_state_t *, void *);
|
||||
|
||||
struct sg_table;
|
||||
|
||||
NV_STATUS NV_API_CALL nv_register_sgt (nv_state_t *, NvU64 *, NvU64, NvU32, void **, struct sg_table *, void *);
|
||||
NV_STATUS NV_API_CALL nv_register_sgt (nv_state_t *, NvU64 *, NvU64, NvU32, void **,
|
||||
struct sg_table *, void *, NvBool);
|
||||
void NV_API_CALL nv_unregister_sgt (nv_state_t *, struct sg_table **, void **, void *);
|
||||
NV_STATUS NV_API_CALL nv_register_phys_pages (nv_state_t *, NvU64 *, NvU64, NvU32, void **);
|
||||
void NV_API_CALL nv_unregister_phys_pages (nv_state_t *, void *);
|
||||
|
||||
NV_STATUS NV_API_CALL nv_dma_map_sgt (nv_dma_device_t *, NvU64, NvU64 *, NvU32, void **);
|
||||
NV_STATUS NV_API_CALL nv_dma_map_pages (nv_dma_device_t *, NvU64, NvU64 *, NvBool, NvU32, void **);
|
||||
NV_STATUS NV_API_CALL nv_dma_unmap_pages (nv_dma_device_t *, NvU64, NvU64 *, void **);
|
||||
|
||||
NV_STATUS NV_API_CALL nv_dma_map_alloc (nv_dma_device_t *, NvU64, NvU64 *, NvBool, void **);
|
||||
NV_STATUS NV_API_CALL nv_dma_unmap_alloc (nv_dma_device_t *, NvU64, NvU64 *, void **);
|
||||
|
||||
NV_STATUS NV_API_CALL nv_dma_map_peer (nv_dma_device_t *, nv_dma_device_t *, NvU8, NvU64, NvU64 *);
|
||||
NV_STATUS NV_API_CALL nv_dma_map_non_pci_peer (nv_dma_device_t *, NvU64, NvU64 *);
|
||||
void NV_API_CALL nv_dma_unmap_peer (nv_dma_device_t *, NvU64, NvU64);
|
||||
|
||||
NV_STATUS NV_API_CALL nv_dma_map_mmio (nv_dma_device_t *, NvU64, NvU64 *);
|
||||
void NV_API_CALL nv_dma_unmap_mmio (nv_dma_device_t *, NvU64, NvU64);
|
||||
|
||||
void NV_API_CALL nv_dma_cache_invalidate (nv_dma_device_t *, void *);
|
||||
void NV_API_CALL nv_dma_enable_nvlink (nv_dma_device_t *);
|
||||
NvBool NV_API_CALL nv_grdma_pci_topology_supported(nv_state_t *, nv_dma_device_t *);
|
||||
|
||||
NvS32 NV_API_CALL nv_start_rc_timer (nv_state_t *);
|
||||
NvS32 NV_API_CALL nv_stop_rc_timer (nv_state_t *);
|
||||
@@ -813,6 +970,7 @@ void NV_API_CALL nv_acpi_methods_init (NvU32 *);
|
||||
void NV_API_CALL nv_acpi_methods_uninit (void);
|
||||
|
||||
NV_STATUS NV_API_CALL nv_acpi_method (NvU32, NvU32, NvU32, void *, NvU16, NvU32 *, void *, NvU16 *);
|
||||
NV_STATUS NV_API_CALL nv_acpi_d3cold_dsm_for_upstream_port (nv_state_t *, NvU8 *, NvU32, NvU32, NvU32 *);
|
||||
NV_STATUS NV_API_CALL nv_acpi_dsm_method (nv_state_t *, NvU8 *, NvU32, NvBool, NvU32, void *, NvU16, NvU32 *, void *, NvU16 *);
|
||||
NV_STATUS NV_API_CALL nv_acpi_ddc_method (nv_state_t *, void *, NvU32 *, NvBool);
|
||||
NV_STATUS NV_API_CALL nv_acpi_dod_method (nv_state_t *, NvU32 *, NvU32 *);
|
||||
@@ -824,9 +982,7 @@ NV_STATUS NV_API_CALL nv_acpi_mux_method (nv_state_t *, NvU32 *, NvU32,
|
||||
|
||||
NV_STATUS NV_API_CALL nv_log_error (nv_state_t *, NvU32, const char *, va_list);
|
||||
|
||||
NvU64 NV_API_CALL nv_get_dma_start_address (nv_state_t *);
|
||||
NV_STATUS NV_API_CALL nv_set_primary_vga_status(nv_state_t *);
|
||||
NV_STATUS NV_API_CALL nv_pci_trigger_recovery (nv_state_t *);
|
||||
NvBool NV_API_CALL nv_requires_dma_remap (nv_state_t *);
|
||||
|
||||
NvBool NV_API_CALL nv_is_rm_firmware_active(nv_state_t *);
|
||||
@@ -836,21 +992,11 @@ void NV_API_CALL nv_put_firmware(const void *);
|
||||
nv_file_private_t* NV_API_CALL nv_get_file_private(NvS32, NvBool, void **);
|
||||
void NV_API_CALL nv_put_file_private(void *);
|
||||
|
||||
NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU32 *, NvS32 *);
|
||||
|
||||
NV_STATUS NV_API_CALL nv_get_ibmnpu_genreg_info(nv_state_t *, NvU64 *, NvU64 *, void**);
|
||||
NV_STATUS NV_API_CALL nv_get_ibmnpu_relaxed_ordering_mode(nv_state_t *nv, NvBool *mode);
|
||||
|
||||
void NV_API_CALL nv_wait_for_ibmnpu_rsync(nv_state_t *nv);
|
||||
|
||||
void NV_API_CALL nv_ibmnpu_cache_flush_range(nv_state_t *nv, NvU64, NvU64);
|
||||
NV_STATUS NV_API_CALL nv_get_device_memory_config(nv_state_t *, NvU64 *, NvU64 *, NvU64 *, NvU32 *, NvS32 *);
|
||||
NV_STATUS NV_API_CALL nv_get_egm_info(nv_state_t *, NvU64 *, NvU64 *, NvS32 *);
|
||||
|
||||
void NV_API_CALL nv_p2p_free_platform_data(void *data);
|
||||
|
||||
#if defined(NVCPU_PPC64LE)
|
||||
NV_STATUS NV_API_CALL nv_get_nvlink_line_rate (nv_state_t *, NvU32 *);
|
||||
#endif
|
||||
|
||||
NV_STATUS NV_API_CALL nv_revoke_gpu_mappings (nv_state_t *);
|
||||
void NV_API_CALL nv_acquire_mmap_lock (nv_state_t *);
|
||||
void NV_API_CALL nv_release_mmap_lock (nv_state_t *);
|
||||
@@ -873,24 +1019,32 @@ void NV_API_CALL nv_cap_drv_exit(void);
|
||||
NvBool NV_API_CALL nv_is_gpu_accessible(nv_state_t *);
|
||||
NvBool NV_API_CALL nv_match_gpu_os_info(nv_state_t *, void *);
|
||||
|
||||
NvU32 NV_API_CALL nv_get_os_type(void);
|
||||
|
||||
void NV_API_CALL nv_get_updated_emu_seg(NvU32 *start, NvU32 *end);
|
||||
void NV_API_CALL nv_get_screen_info(nv_state_t *, NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU32 *, NvU64 *);
|
||||
void NV_API_CALL nv_set_gpu_pg_mask(nv_state_t *);
|
||||
|
||||
struct dma_buf;
|
||||
typedef struct nv_dma_buf nv_dma_buf_t;
|
||||
struct drm_gem_object;
|
||||
|
||||
NV_STATUS NV_API_CALL nv_dma_import_sgt (nv_dma_device_t *, struct sg_table *, struct drm_gem_object *);
|
||||
void NV_API_CALL nv_dma_release_sgt(struct sg_table *, struct drm_gem_object *);
|
||||
NV_STATUS NV_API_CALL nv_dma_import_dma_buf (nv_dma_device_t *, struct dma_buf *, NvU32 *, struct sg_table **, nv_dma_buf_t **);
|
||||
NV_STATUS NV_API_CALL nv_dma_import_from_fd (nv_dma_device_t *, NvS32, NvU32 *, struct sg_table **, nv_dma_buf_t **);
|
||||
NV_STATUS NV_API_CALL nv_dma_import_dma_buf (nv_dma_device_t *, struct dma_buf *, NvBool, NvU32 *, struct sg_table **, nv_dma_buf_t **);
|
||||
NV_STATUS NV_API_CALL nv_dma_import_from_fd (nv_dma_device_t *, NvS32, NvBool, NvU32 *, struct sg_table **, nv_dma_buf_t **);
|
||||
void NV_API_CALL nv_dma_release_dma_buf (nv_dma_buf_t *);
|
||||
|
||||
void NV_API_CALL nv_schedule_uvm_isr (nv_state_t *);
|
||||
|
||||
NV_STATUS NV_API_CALL nv_schedule_uvm_drain_p2p (NvU8 *);
|
||||
void NV_API_CALL nv_schedule_uvm_resume_p2p (NvU8 *);
|
||||
|
||||
NvBool NV_API_CALL nv_platform_supports_s0ix (void);
|
||||
NvBool NV_API_CALL nv_s2idle_pm_configured (void);
|
||||
|
||||
NvBool NV_API_CALL nv_pci_tegra_register_power_domain (nv_state_t *, NvBool);
|
||||
NvBool NV_API_CALL nv_pci_tegra_pm_init (nv_state_t *);
|
||||
void NV_API_CALL nv_pci_tegra_pm_deinit (nv_state_t *);
|
||||
|
||||
NvBool NV_API_CALL nv_is_chassis_notebook (void);
|
||||
void NV_API_CALL nv_allow_runtime_suspend (nv_state_t *nv);
|
||||
void NV_API_CALL nv_disallow_runtime_suspend (nv_state_t *nv);
|
||||
@@ -899,26 +1053,24 @@ typedef void (*nvTegraDceClientIpcCallback)(NvU32, NvU32, NvU32, void *, void *)
|
||||
|
||||
NV_STATUS NV_API_CALL nv_get_num_phys_pages (void *, NvU32 *);
|
||||
NV_STATUS NV_API_CALL nv_get_phys_pages (void *, void *, NvU32 *);
|
||||
void NV_API_CALL nv_get_disp_smmu_stream_ids (nv_state_t *, NvU32 *, NvU32 *);
|
||||
|
||||
typedef struct TEGRA_IMP_IMPORT_DATA TEGRA_IMP_IMPORT_DATA;
|
||||
typedef struct nv_i2c_msg_s nv_i2c_msg_t;
|
||||
|
||||
NV_STATUS NV_API_CALL nv_bpmp_send_mrq (nv_state_t *, NvU32, const void *, NvU32, void *, NvU32, NvS32 *, NvS32 *);
|
||||
NV_STATUS NV_API_CALL nv_i2c_transfer(nv_state_t *, NvU32, NvU8, nv_i2c_msg_t *, int);
|
||||
void NV_API_CALL nv_i2c_unregister_clients(nv_state_t *);
|
||||
NV_STATUS NV_API_CALL nv_i2c_bus_status(nv_state_t *, NvU32, NvS32 *, NvS32 *);
|
||||
NV_STATUS NV_API_CALL nv_clk_get_handles (nv_state_t *);
|
||||
void NV_API_CALL nv_clk_clear_handles (nv_state_t *);
|
||||
NV_STATUS NV_API_CALL nv_enable_clk (nv_state_t *, TEGRASOC_WHICH_CLK);
|
||||
NvBool NV_API_CALL nv_is_clk_enabled (nv_state_t *, TEGRASOC_WHICH_CLK);
|
||||
void NV_API_CALL nv_disable_clk (nv_state_t *, TEGRASOC_WHICH_CLK);
|
||||
NV_STATUS NV_API_CALL nv_get_curr_freq (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32 *);
|
||||
NV_STATUS NV_API_CALL nv_get_max_freq (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32 *);
|
||||
NV_STATUS NV_API_CALL nv_get_min_freq (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32 *);
|
||||
NV_STATUS NV_API_CALL nv_set_freq (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32);
|
||||
NV_STATUS NV_API_CALL nv_set_parent (nv_state_t *, TEGRASOC_WHICH_CLK, TEGRASOC_WHICH_CLK);
|
||||
NV_STATUS NV_API_CALL nv_get_parent (nv_state_t *, TEGRASOC_WHICH_CLK, TEGRASOC_WHICH_CLK*);
|
||||
NV_STATUS NV_API_CALL nv_soc_device_reset (nv_state_t *);
|
||||
NV_STATUS NV_API_CALL nv_imp_get_import_data (TEGRA_IMP_IMPORT_DATA *);
|
||||
NV_STATUS NV_API_CALL nv_imp_get_uefi_data (nv_state_t *nv, NvU32 *iso_bw_kbps, NvU32 *floor_bw_kbps);
|
||||
NV_STATUS NV_API_CALL nv_imp_enable_disable_rfl (nv_state_t *nv, NvBool bEnable);
|
||||
NV_STATUS NV_API_CALL nv_imp_icc_set_bw (nv_state_t *nv, NvU32 avg_bw_kbps, NvU32 floor_bw_kbps);
|
||||
NV_STATUS NV_API_CALL nv_get_num_dpaux_instances(nv_state_t *nv, NvU32 *num_instances);
|
||||
NV_STATUS NV_API_CALL nv_get_tegra_brightness_level(nv_state_t *, NvU32 *);
|
||||
NV_STATUS NV_API_CALL nv_set_tegra_brightness_level(nv_state_t *, NvU32);
|
||||
|
||||
NV_STATUS NV_API_CALL nv_soc_device_reset (nv_state_t *);
|
||||
NV_STATUS NV_API_CALL nv_soc_pm_powergate (nv_state_t *);
|
||||
NV_STATUS NV_API_CALL nv_soc_pm_unpowergate (nv_state_t *);
|
||||
NV_STATUS NV_API_CALL nv_gpio_get_pin_state(nv_state_t *, NvU32, NvU32 *);
|
||||
@@ -928,10 +1080,6 @@ NV_STATUS NV_API_CALL nv_gpio_get_pin_direction(nv_state_t *, NvU32, NvU32 *);
|
||||
NV_STATUS NV_API_CALL nv_gpio_get_pin_number(nv_state_t *, NvU32, NvU32 *);
|
||||
NvBool NV_API_CALL nv_gpio_get_pin_interrupt_status(nv_state_t *, NvU32, NvU32);
|
||||
NV_STATUS NV_API_CALL nv_gpio_set_pin_interrupt(nv_state_t *, NvU32, NvU32);
|
||||
NV_STATUS NV_API_CALL nv_get_num_dpaux_instances(nv_state_t *nv, NvU32 *num_instances);
|
||||
NV_STATUS NV_API_CALL nv_get_tegra_brightness_level(nv_state_t *, NvU32 *);
|
||||
NV_STATUS NV_API_CALL nv_set_tegra_brightness_level(nv_state_t *, NvU32);
|
||||
NV_STATUS NV_API_CALL nv_get_syncpoint_aperture(NvU32, NvU64 *, NvU64 *, NvU32 *);
|
||||
NvU32 NV_API_CALL nv_tegra_get_rm_interface_type(NvU32);
|
||||
NV_STATUS NV_API_CALL nv_tegra_dce_register_ipc_client(NvU32, void *, nvTegraDceClientIpcCallback, NvU32 *);
|
||||
NV_STATUS NV_API_CALL nv_tegra_dce_client_ipc_send_recv(NvU32, void *, NvU32);
|
||||
@@ -955,6 +1103,17 @@ NvU32 NV_API_CALL nv_soc_tsec_event_register(nv_soc_tsec_cb_func_t cb_func,
|
||||
NvU32 NV_API_CALL nv_soc_tsec_event_unregister(NvBool is_init_event);
|
||||
void* NV_API_CALL nv_soc_tsec_alloc_mem_desc(NvU32 num_bytes, NvU32 *flcn_addr);
|
||||
void NV_API_CALL nv_soc_tsec_free_mem_desc(void *mem_desc);
|
||||
NvBool NV_API_CALL nv_is_clk_enabled (nv_state_t *, TEGRASOC_WHICH_CLK);
|
||||
NV_STATUS NV_API_CALL nv_set_parent (nv_state_t *, TEGRASOC_WHICH_CLK, TEGRASOC_WHICH_CLK);
|
||||
NV_STATUS NV_API_CALL nv_get_parent (nv_state_t *, TEGRASOC_WHICH_CLK, TEGRASOC_WHICH_CLK*);
|
||||
NV_STATUS NV_API_CALL nv_clk_get_handles (nv_state_t *);
|
||||
void NV_API_CALL nv_clk_clear_handles (nv_state_t *);
|
||||
NV_STATUS NV_API_CALL nv_enable_clk (nv_state_t *, TEGRASOC_WHICH_CLK);
|
||||
void NV_API_CALL nv_disable_clk (nv_state_t *, TEGRASOC_WHICH_CLK);
|
||||
NV_STATUS NV_API_CALL nv_get_curr_freq (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32 *);
|
||||
NV_STATUS NV_API_CALL nv_get_max_freq (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32 *);
|
||||
NV_STATUS NV_API_CALL nv_get_min_freq (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32 *);
|
||||
NV_STATUS NV_API_CALL nv_set_freq (nv_state_t *, TEGRASOC_WHICH_CLK, NvU32);
|
||||
|
||||
/*
|
||||
* ---------------------------------------------------------------------------
|
||||
@@ -982,6 +1141,9 @@ NV_STATUS NV_API_CALL rm_ioctl (nvidia_stack_t *, nv_state_t *
|
||||
NvBool NV_API_CALL rm_isr (nvidia_stack_t *, nv_state_t *, NvU32 *);
|
||||
void NV_API_CALL rm_isr_bh (nvidia_stack_t *, nv_state_t *);
|
||||
void NV_API_CALL rm_isr_bh_unlocked (nvidia_stack_t *, nv_state_t *);
|
||||
NvBool NV_API_CALL rm_is_msix_allowed (nvidia_stack_t *, nv_state_t *);
|
||||
NvBool NV_API_CALL rm_wait_for_bar_firewall (nvidia_stack_t *, NvU32 domain, NvU8 bus, NvU8 device, NvU8 function, NvU16 devId, NvU16 subsystemId);
|
||||
NV_STATUS NV_API_CALL rm_pmu_perfmon_get_load (nvidia_stack_t *, nv_state_t *, NvU32 *, TEGRASOC_DEVFREQ_CLK);
|
||||
NV_STATUS NV_API_CALL rm_power_management (nvidia_stack_t *, nv_state_t *, nv_pm_action_t);
|
||||
NV_STATUS NV_API_CALL rm_stop_user_channels (nvidia_stack_t *, nv_state_t *);
|
||||
NV_STATUS NV_API_CALL rm_restart_user_channels (nvidia_stack_t *, nv_state_t *);
|
||||
@@ -1001,6 +1163,7 @@ void NV_API_CALL rm_parse_option_string (nvidia_stack_t *, const char *
|
||||
char* NV_API_CALL rm_remove_spaces (const char *);
|
||||
char* NV_API_CALL rm_string_token (char **, const char);
|
||||
void NV_API_CALL rm_vgpu_vfio_set_driver_vm(nvidia_stack_t *, NvBool);
|
||||
NV_STATUS NV_API_CALL rm_get_adapter_status_external(nvidia_stack_t *, nv_state_t *);
|
||||
|
||||
NV_STATUS NV_API_CALL rm_run_rc_callback (nvidia_stack_t *, nv_state_t *);
|
||||
void NV_API_CALL rm_execute_work_item (nvidia_stack_t *, void *);
|
||||
@@ -1028,20 +1191,28 @@ void NV_API_CALL rm_request_dnotifier_state (nvidia_stack_t *, n
|
||||
void NV_API_CALL rm_disable_gpu_state_persistence (nvidia_stack_t *sp, nv_state_t *);
|
||||
NV_STATUS NV_API_CALL rm_p2p_init_mapping (nvidia_stack_t *, NvU64, NvU64 *, NvU64 *, NvU64 *, NvU64 *, NvU64, NvU64, NvU64, NvU64, void (*)(void *), void *);
|
||||
NV_STATUS NV_API_CALL rm_p2p_destroy_mapping (nvidia_stack_t *, NvU64);
|
||||
NV_STATUS NV_API_CALL rm_p2p_get_pages (nvidia_stack_t *, NvU64, NvU32, NvU64, NvU64, NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU8 **, void *);
|
||||
NV_STATUS NV_API_CALL rm_p2p_get_pages (nvidia_stack_t *, NvU64, NvU32, NvU64, NvU64, NvU64 *, NvU32 *, NvU32 *, NvU32 *, NvU8 **, void *, NvBool *);
|
||||
NV_STATUS NV_API_CALL rm_p2p_get_gpu_info (nvidia_stack_t *, NvU64, NvU64, NvU8 **, void **);
|
||||
NV_STATUS NV_API_CALL rm_p2p_get_pages_persistent (nvidia_stack_t *, NvU64, NvU64, void **, NvU64 *, NvU32 *, void *, void *);
|
||||
NV_STATUS NV_API_CALL rm_p2p_get_pages_persistent (nvidia_stack_t *, NvU64, NvU64, void **, NvU64 *, NvU32 *, NvBool, void *, void *, void **, NvBool *);
|
||||
NV_STATUS NV_API_CALL rm_p2p_register_callback (nvidia_stack_t *, NvU64, NvU64, NvU64, void *, void (*)(void *), void *);
|
||||
NV_STATUS NV_API_CALL rm_p2p_put_pages (nvidia_stack_t *, NvU64, NvU32, NvU64, void *);
|
||||
NV_STATUS NV_API_CALL rm_p2p_put_pages_persistent(nvidia_stack_t *, void *, void *);
|
||||
NV_STATUS NV_API_CALL rm_p2p_put_pages_persistent(nvidia_stack_t *, void *, void *, void *);
|
||||
NV_STATUS NV_API_CALL rm_p2p_dma_map_pages (nvidia_stack_t *, nv_dma_device_t *, NvU8 *, NvU64, NvU32, NvU64 *, void **);
|
||||
NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, NvHandle, void *, NvHandle, NvU64, NvU64, NvHandle *, void **);
|
||||
NV_STATUS NV_API_CALL rm_dma_buf_dup_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle,
|
||||
NvHandle, void *, NvHandle, NvU64, NvU64, NvHandle *, void **,
|
||||
NvBool *, NvU32 *, NvBool *, nv_memory_type_t *);
|
||||
void NV_API_CALL rm_dma_buf_undup_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle);
|
||||
NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle (nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, NvU64, void *, nv_phys_addr_range_t **, NvU32 *);
|
||||
void NV_API_CALL rm_dma_buf_unmap_mem_handle(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvU64, nv_phys_addr_range_t **, NvU32);
|
||||
NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle *, NvHandle *, NvHandle *, void **, NvBool *);
|
||||
NV_STATUS NV_API_CALL rm_dma_buf_map_mem_handle (nvidia_stack_t *, nv_state_t *,
|
||||
NvHandle, NvHandle, MemoryRange,
|
||||
NvU8, void *, NvBool, MemoryArea *);
|
||||
void NV_API_CALL rm_dma_buf_unmap_mem_handle(nvidia_stack_t *, nv_state_t *,
|
||||
NvHandle, NvHandle, NvU8, void *,
|
||||
NvBool, MemoryArea);
|
||||
NV_STATUS NV_API_CALL rm_dma_buf_get_client_and_device(nvidia_stack_t *,
|
||||
nv_state_t *, NvHandle, NvHandle,
|
||||
NvU8, NvHandle *, NvHandle *,
|
||||
NvHandle *, void **, NvBool *, NvBool *);
|
||||
void NV_API_CALL rm_dma_buf_put_client_and_device(nvidia_stack_t *, nv_state_t *, NvHandle, NvHandle, NvHandle, void *);
|
||||
NV_STATUS NV_API_CALL rm_log_gpu_crash (nv_stack_t *, nv_state_t *);
|
||||
|
||||
void NV_API_CALL rm_kernel_rmapi_op(nvidia_stack_t *sp, void *ops_cmd);
|
||||
NvBool NV_API_CALL rm_get_device_remove_flag(nvidia_stack_t *sp, NvU32 gpu_id);
|
||||
@@ -1051,44 +1222,47 @@ NvBool NV_API_CALL rm_gpu_need_4k_page_isolation(nv_state_t *);
|
||||
NvBool NV_API_CALL rm_is_chipset_io_coherent(nv_stack_t *);
|
||||
NvBool NV_API_CALL rm_init_event_locks(nvidia_stack_t *, nv_state_t *);
|
||||
void NV_API_CALL rm_destroy_event_locks(nvidia_stack_t *, nv_state_t *);
|
||||
NV_STATUS NV_API_CALL rm_get_gpu_numa_info(nvidia_stack_t *, nv_state_t *, NvS32 *, NvU64 *, NvU64 *, NvU64 *, NvU32 *);
|
||||
NV_STATUS NV_API_CALL rm_get_gpu_numa_info(nvidia_stack_t *, nv_state_t *, nv_ioctl_numa_info_t *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_numa_online(nvidia_stack_t *, nv_state_t *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_numa_offline(nvidia_stack_t *, nv_state_t *);
|
||||
NvBool NV_API_CALL rm_is_device_sequestered(nvidia_stack_t *, nv_state_t *);
|
||||
void NV_API_CALL rm_check_for_gpu_surprise_removal(nvidia_stack_t *, nv_state_t *);
|
||||
NV_STATUS NV_API_CALL rm_set_external_kernel_client_count(nvidia_stack_t *, nv_state_t *, NvBool);
|
||||
NV_STATUS NV_API_CALL rm_schedule_gpu_wakeup(nvidia_stack_t *, nv_state_t *);
|
||||
NvBool NV_API_CALL rm_is_iommu_needed_for_sriov(nvidia_stack_t *, nv_state_t *);
|
||||
NvBool NV_API_CALL rm_disable_iomap_wc(void);
|
||||
|
||||
void NV_API_CALL rm_init_tegra_dynamic_power_management(nvidia_stack_t *, nv_state_t *);
|
||||
void NV_API_CALL rm_init_dynamic_power_management(nvidia_stack_t *, nv_state_t *, NvBool);
|
||||
void NV_API_CALL rm_cleanup_dynamic_power_management(nvidia_stack_t *, nv_state_t *);
|
||||
void NV_API_CALL rm_enable_dynamic_power_management(nvidia_stack_t *, nv_state_t *);
|
||||
NV_STATUS NV_API_CALL rm_ref_dynamic_power(nvidia_stack_t *, nv_state_t *, nv_dynamic_power_mode_t);
|
||||
void NV_API_CALL rm_unref_dynamic_power(nvidia_stack_t *, nv_state_t *, nv_dynamic_power_mode_t);
|
||||
NV_STATUS NV_API_CALL rm_transition_dynamic_power(nvidia_stack_t *, nv_state_t *, NvBool);
|
||||
const char* NV_API_CALL rm_get_vidmem_power_status(nvidia_stack_t *, nv_state_t *);
|
||||
const char* NV_API_CALL rm_get_dynamic_power_management_status(nvidia_stack_t *, nv_state_t *);
|
||||
const char* NV_API_CALL rm_get_gpu_gcx_support(nvidia_stack_t *, nv_state_t *, NvBool);
|
||||
NV_STATUS NV_API_CALL rm_transition_dynamic_power(nvidia_stack_t *, nv_state_t *, NvBool, NvBool *);
|
||||
void NV_API_CALL rm_get_power_info(nvidia_stack_t *, nv_state_t *, nv_power_info_t *);
|
||||
|
||||
void NV_API_CALL rm_acpi_notify(nvidia_stack_t *, nv_state_t *, NvU32);
|
||||
void NV_API_CALL rm_acpi_nvpcf_notify(nvidia_stack_t *);
|
||||
|
||||
NvBool NV_API_CALL rm_is_altstack_in_use(void);
|
||||
|
||||
void NV_API_CALL rm_notify_gpu_addition(nvidia_stack_t *, nv_state_t *);
|
||||
void NV_API_CALL rm_notify_gpu_removal(nvidia_stack_t *, nv_state_t *);
|
||||
|
||||
/* vGPU VFIO specific functions */
|
||||
NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *, NvU32);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_create_request(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU16 *,
|
||||
NvU32 *, NvU32 *, NvU32);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_delete(nvidia_stack_t *, const NvU8 *, NvU16);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_get_type_ids(nvidia_stack_t *, nv_state_t *, NvU32 *, NvU32 *, NvBool, NvU8, NvBool);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_get_type_info(nvidia_stack_t *, nv_state_t *, NvU32, char *, int, NvU8);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_get_bar_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU32, void *, NvBool *);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_start(nvidia_stack_t *, const NvU8 *, void *, NvS32 *, NvU8 *, NvU32);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_get_sparse_mmap(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 **, NvU64 **, NvU32 *);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_get_bar_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *,
|
||||
NvU64 *, NvU64 *, NvU32 *, NvBool *, NvU8 *);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_update_sysfs_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU32, NvU32 *);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_get_hbm_info(nvidia_stack_t *, nv_state_t *, const NvU8 *, NvU64 *, NvU64 *);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_process_vf_info(nvidia_stack_t *, nv_state_t *, NvU8, NvU32, NvU8, NvU8, NvU8, NvBool, void *);
|
||||
NV_STATUS NV_API_CALL nv_vgpu_update_request(nvidia_stack_t *, const NvU8 *, NvU32, NvU64 *, NvU64 *, const char *);
|
||||
NV_STATUS NV_API_CALL nv_gpu_bind_event(nvidia_stack_t *);
|
||||
NV_STATUS NV_API_CALL nv_gpu_bind_event(nvidia_stack_t *, NvU32, NvBool *);
|
||||
NV_STATUS NV_API_CALL nv_gpu_unbind_event(nvidia_stack_t *, NvU32, NvBool *);
|
||||
|
||||
NV_STATUS NV_API_CALL nv_get_usermap_access_params(nv_state_t*, nv_usermap_access_params_t*);
|
||||
NV_STATUS NV_API_CALL nv_check_usermap_access_params(nv_state_t*, const nv_usermap_access_params_t*);
|
||||
nv_soc_irq_type_t NV_API_CALL nv_get_current_irq_type(nv_state_t*);
|
||||
void NV_API_CALL nv_flush_coherent_cpu_cache_range(nv_state_t *nv, NvU64 cpu_virtual, NvU64 size);
|
||||
|
||||
@@ -1117,6 +1291,9 @@ NV_STATUS NV_API_CALL rm_run_nano_timer_callback(nvidia_stack_t *, nv_state_t
|
||||
void NV_API_CALL nv_cancel_nano_timer(nv_state_t *, nv_nano_timer_t *);
|
||||
void NV_API_CALL nv_destroy_nano_timer(nv_state_t *nv, nv_nano_timer_t *);
|
||||
|
||||
// Host1x specific functions.
|
||||
NV_STATUS NV_API_CALL nv_get_syncpoint_aperture(NvU32, NvU64 *, NvU64 *, NvU32 *);
|
||||
|
||||
#if defined(NVCPU_X86_64)
|
||||
|
||||
static inline NvU64 nv_rdtsc(void)
|
||||
46
kernel-open/common/inc/nv_mig_types.h
Normal file
46
kernel-open/common/inc/nv_mig_types.h
Normal file
@@ -0,0 +1,46 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#ifndef __NV_MIG_TYPES_H__
|
||||
#define __NV_MIG_TYPES_H__
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "nvtypes.h"
|
||||
|
||||
typedef NvU32 MIGDeviceId;
|
||||
|
||||
#define NO_MIG_DEVICE 0L
|
||||
|
||||
/* Convert a MIGDeviceId into a 0-based per-GPU subdevice index. */
|
||||
#define MIG_DEVICE_ID_SUBDEV_MASK 0xf0000000
|
||||
#define MIG_DEVICE_ID_SUBDEV_SHIFT 28
|
||||
|
||||
#define MIG_DEVICE_ID_TO_SUBDEV(migDeviceId) (((migDeviceId) & MIG_DEVICE_ID_SUBDEV_MASK) >> MIG_DEVICE_ID_SUBDEV_SHIFT)
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __NV_MIG_TYPES_H__ */
|
||||
@@ -86,7 +86,7 @@
|
||||
/* Not currently implemented for MSVC/ARM64. See bug 3366890. */
|
||||
# define nv_speculation_barrier()
|
||||
# define speculation_barrier() nv_speculation_barrier()
|
||||
#elif defined(NVCPU_NVRISCV64) && NVOS_IS_LIBOS
|
||||
#elif defined(NVCPU_IS_RISCV64)
|
||||
# define nv_speculation_barrier()
|
||||
#else
|
||||
#error "Unknown compiler/chip family"
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2013-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2013-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -29,7 +29,7 @@
|
||||
#define _NV_UVM_INTERFACE_H_
|
||||
|
||||
// Forward references, to break circular header file dependencies:
|
||||
struct UvmOpsUvmEvents;
|
||||
struct UvmEventsLinux;
|
||||
|
||||
#if defined(NVIDIA_UVM_ENABLED)
|
||||
|
||||
@@ -46,6 +46,7 @@ struct UvmOpsUvmEvents;
|
||||
#include "nvgputypes.h"
|
||||
#include "nvstatus.h"
|
||||
#include "nv_uvm_types.h"
|
||||
#include "nv_uvm_user_types.h"
|
||||
|
||||
|
||||
// Define the type here as it's Linux specific, used only by the Linux specific
|
||||
@@ -62,10 +63,10 @@ typedef struct
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceRegisterGpu
|
||||
|
||||
Registers the GPU with the provided UUID for use. A GPU must be registered
|
||||
before its UUID can be used with any other API. This call is ref-counted so
|
||||
every nvUvmInterfaceRegisterGpu must be paired with a corresponding
|
||||
nvUvmInterfaceUnregisterGpu.
|
||||
Registers the GPU with the provided physical UUID for use. A GPU must be
|
||||
registered before its UUID can be used with any other API. This call is
|
||||
ref-counted so every nvUvmInterfaceRegisterGpu must be paired with a
|
||||
corresponding nvUvmInterfaceUnregisterGpu.
|
||||
|
||||
You don't need to call nvUvmInterfaceSessionCreate before calling this.
|
||||
|
||||
@@ -79,12 +80,13 @@ NV_STATUS nvUvmInterfaceRegisterGpu(const NvProcessorUuid *gpuUuid, UvmGpuPlatfo
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceUnregisterGpu
|
||||
|
||||
Unregisters the GPU with the provided UUID. This drops the ref count from
|
||||
nvUvmInterfaceRegisterGpu. Once the reference count goes to 0 the device may
|
||||
no longer be accessible until the next nvUvmInterfaceRegisterGpu call. No
|
||||
automatic resource freeing is performed, so only make the last unregister
|
||||
call after destroying all your allocations associated with that UUID (such
|
||||
as those from nvUvmInterfaceAddressSpaceCreate).
|
||||
Unregisters the GPU with the provided physical UUID. This drops the ref
|
||||
count from nvUvmInterfaceRegisterGpu. Once the reference count goes to 0
|
||||
the device may no longer be accessible until the next
|
||||
nvUvmInterfaceRegisterGpu call. No automatic resource freeing is performed,
|
||||
so only make the last unregister call after destroying all your allocations
|
||||
associated with that UUID (such as those from
|
||||
nvUvmInterfaceAddressSpaceCreate).
|
||||
|
||||
If the UUID is not found, no operation is performed.
|
||||
*/
|
||||
@@ -121,10 +123,10 @@ NV_STATUS nvUvmInterfaceSessionDestroy(uvmGpuSessionHandle session);
|
||||
nvUvmInterfaceDeviceCreate
|
||||
|
||||
Creates a device object under the given session for the GPU with the given
|
||||
UUID. Also creates a partition object for the device iff bCreateSmcPartition
|
||||
is true and pGpuInfo->smcEnabled is true. pGpuInfo->smcUserClientInfo will
|
||||
be used to determine the SMC partition in this case. A device handle is
|
||||
returned in the device output parameter.
|
||||
physical UUID. Also creates a partition object for the device iff
|
||||
bCreateSmcPartition is true and pGpuInfo->smcEnabled is true.
|
||||
pGpuInfo->smcUserClientInfo will be used to determine the SMC partition in
|
||||
this case. A device handle is returned in the device output parameter.
|
||||
|
||||
Error codes:
|
||||
NV_ERR_GENERIC
|
||||
@@ -161,6 +163,7 @@ void nvUvmInterfaceDeviceDestroy(uvmGpuDeviceHandle device);
|
||||
NV_STATUS nvUvmInterfaceAddressSpaceCreate(uvmGpuDeviceHandle device,
|
||||
unsigned long long vaBase,
|
||||
unsigned long long vaSize,
|
||||
NvBool enableAts,
|
||||
uvmGpuAddressSpaceHandle *vaSpace,
|
||||
UvmGpuAddressSpaceInfo *vaSpaceInfo);
|
||||
|
||||
@@ -422,33 +425,6 @@ NV_STATUS nvUvmInterfacePmaPinPages(void *pPma,
|
||||
NvU64 pageSize,
|
||||
NvU32 flags);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfacePmaUnpinPages
|
||||
|
||||
This function will unpin the physical memory allocated using PMA. The pages
|
||||
passed as input must be already pinned, else this function will return an
|
||||
error and rollback any change if any page is not previously marked "pinned".
|
||||
Behaviour is undefined if any blacklisted pages are unpinned.
|
||||
|
||||
Arguments:
|
||||
pPma[IN] - Pointer to PMA object.
|
||||
pPages[IN] - Array of pointers, containing the PA base
|
||||
address of each page to be unpinned.
|
||||
pageCount [IN] - Number of pages required to be unpinned.
|
||||
pageSize [IN] - Page size of each page to be unpinned.
|
||||
|
||||
Error codes:
|
||||
NV_ERR_INVALID_ARGUMENT - Invalid input arguments.
|
||||
NV_ERR_GENERIC - Unexpected error. We try hard to avoid
|
||||
returning this error code as is not very
|
||||
informative.
|
||||
NV_ERR_NOT_SUPPORTED - Operation not supported on broken FB
|
||||
*/
|
||||
NV_STATUS nvUvmInterfacePmaUnpinPages(void *pPma,
|
||||
NvU64 *pPages,
|
||||
NvLength pageCount,
|
||||
NvU64 pageSize);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceMemoryFree
|
||||
|
||||
@@ -617,6 +593,14 @@ void nvUvmInterfaceChannelDestroy(uvmGpuChannelHandle channel);
|
||||
Error codes:
|
||||
NV_ERR_GENERIC
|
||||
NV_ERR_NO_MEMORY
|
||||
NV_ERR_INVALID_STATE
|
||||
NV_ERR_NOT_SUPPORTED
|
||||
NV_ERR_NOT_READY
|
||||
NV_ERR_INVALID_LOCK_STATE
|
||||
NV_ERR_INVALID_STATE
|
||||
NV_ERR_NVLINK_FABRIC_NOT_READY
|
||||
NV_ERR_NVLINK_FABRIC_FAILURE
|
||||
NV_ERR_GPU_MEMORY_ONLINING_FAILURE
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceQueryCaps(uvmGpuDeviceHandle device,
|
||||
UvmGpuCaps *caps);
|
||||
@@ -638,6 +622,8 @@ NV_STATUS nvUvmInterfaceQueryCopyEnginesCaps(uvmGpuDeviceHandle device,
|
||||
nvUvmInterfaceGetGpuInfo
|
||||
|
||||
Return various gpu info, refer to the UvmGpuInfo struct for details.
|
||||
The input UUID is for the physical GPU and the pGpuClientInfo identifies
|
||||
the SMC partition if SMC is enabled and the partition exists.
|
||||
If no gpu matching the uuid is found, an error will be returned.
|
||||
|
||||
On Ampere+ GPUs, pGpuClientInfo contains SMC information provided by the
|
||||
@@ -645,6 +631,9 @@ NV_STATUS nvUvmInterfaceQueryCopyEnginesCaps(uvmGpuDeviceHandle device,
|
||||
|
||||
Error codes:
|
||||
NV_ERR_GENERIC
|
||||
NV_ERR_NO_MEMORY
|
||||
NV_ERR_GPU_UUID_NOT_FOUND
|
||||
NV_ERR_INSUFFICIENT_PERMISSIONS
|
||||
NV_ERR_INSUFFICIENT_RESOURCES
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceGetGpuInfo(const NvProcessorUuid *gpuUuid,
|
||||
@@ -672,14 +661,20 @@ NV_STATUS nvUvmInterfaceServiceDeviceInterruptsRM(uvmGpuDeviceHandle device);
|
||||
RM will propagate the update to all channels using the provided VA space.
|
||||
All channels must be idle when this call is made.
|
||||
|
||||
If the pageDirectory is in system memory then a CPU physical address must be
|
||||
provided. RM will establish and manage the DMA mapping for the
|
||||
pageDirectory.
|
||||
|
||||
Arguments:
|
||||
vaSpace[IN} - VASpace Object
|
||||
physAddress[IN] - Physical address of new page directory
|
||||
physAddress[IN] - Physical address of new page directory. If
|
||||
!bVidMemAperture this is a CPU physical address.
|
||||
numEntries[IN] - Number of entries including previous PDE which will be copied
|
||||
bVidMemAperture[IN] - If set pageDirectory will reside in VidMem aperture else sysmem
|
||||
pasid[IN] - PASID (Process Address Space IDentifier) of the process
|
||||
corresponding to the VA space. Ignored unless the VA space
|
||||
object has ATS enabled.
|
||||
dmaAddress[OUT] - DMA mapping created for physAddress.
|
||||
|
||||
Error codes:
|
||||
NV_ERR_GENERIC
|
||||
@@ -687,7 +682,8 @@ NV_STATUS nvUvmInterfaceServiceDeviceInterruptsRM(uvmGpuDeviceHandle device);
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceSetPageDirectory(uvmGpuAddressSpaceHandle vaSpace,
|
||||
NvU64 physAddress, unsigned numEntries,
|
||||
NvBool bVidMemAperture, NvU32 pasid);
|
||||
NvBool bVidMemAperture, NvU32 pasid,
|
||||
NvU64 *dmaAddress);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceUnsetPageDirectory
|
||||
@@ -857,7 +853,7 @@ NV_STATUS nvUvmInterfaceGetEccInfo(uvmGpuDeviceHandle device,
|
||||
UVM GPU UNLOCK
|
||||
|
||||
Arguments:
|
||||
gpuUuid[IN] - UUID of the GPU to operate on
|
||||
device[IN] - Device handle associated with the gpu
|
||||
bOwnInterrupts - Set to NV_TRUE for UVM to take ownership of the
|
||||
replayable page fault interrupts. Set to NV_FALSE
|
||||
to return ownership of the page fault interrupts
|
||||
@@ -973,14 +969,45 @@ NV_STATUS nvUvmInterfaceGetNonReplayableFaults(UvmGpuFaultInfo *pFaultInfo,
|
||||
NOTES:
|
||||
- This function DOES NOT acquire the RM API or GPU locks. That is because
|
||||
it is called during fault servicing, which could produce deadlocks.
|
||||
- This function should not be called when interrupts are disabled.
|
||||
|
||||
Arguments:
|
||||
device[IN] - Device handle associated with the gpu
|
||||
pFaultInfo[IN] - information provided by RM for fault handling.
|
||||
used for obtaining the device handle without locks.
|
||||
bCopyAndFlush[IN] - Instructs RM to perform the flush in the Copy+Flush mode.
|
||||
In this mode, RM will perform a copy of the packets from
|
||||
the HW buffer to UVM's SW buffer as part of performing
|
||||
the flush. This mode gives UVM the opportunity to observe
|
||||
the packets contained within the HW buffer at the time
|
||||
of issuing the call.
|
||||
|
||||
Error codes:
|
||||
NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceFlushReplayableFaultBuffer(uvmGpuDeviceHandle device);
|
||||
NV_STATUS nvUvmInterfaceFlushReplayableFaultBuffer(UvmGpuFaultInfo *pFaultInfo,
|
||||
NvBool bCopyAndFlush);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceTogglePrefetchFaults
|
||||
|
||||
This function sends an RPC to GSP in order to toggle the prefetch fault PRI.
|
||||
|
||||
NOTES:
|
||||
- This function DOES NOT acquire the RM API or GPU locks. That is because
|
||||
it is called during fault servicing, which could produce deadlocks.
|
||||
- This function should not be called when interrupts are disabled.
|
||||
|
||||
Arguments:
|
||||
pFaultInfo[IN] - Information provided by RM for fault handling.
|
||||
Used for obtaining the device handle without locks.
|
||||
bEnable[IN] - Instructs RM whether to toggle generating faults on
|
||||
prefetch on/off.
|
||||
|
||||
Error codes:
|
||||
NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceTogglePrefetchFaults(UvmGpuFaultInfo *pFaultInfo,
|
||||
NvBool bEnable);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceInitAccessCntrInfo
|
||||
@@ -1037,7 +1064,7 @@ NV_STATUS nvUvmInterfaceDestroyAccessCntrInfo(uvmGpuDeviceHandle device,
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceEnableAccessCntr(uvmGpuDeviceHandle device,
|
||||
UvmGpuAccessCntrInfo *pAccessCntrInfo,
|
||||
UvmGpuAccessCntrConfig *pAccessCntrConfig);
|
||||
const UvmGpuAccessCntrConfig *pAccessCntrConfig);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceDisableAccessCntr
|
||||
@@ -1059,20 +1086,36 @@ NV_STATUS nvUvmInterfaceDisableAccessCntr(uvmGpuDeviceHandle device,
|
||||
UvmGpuAccessCntrInfo *pAccessCntrInfo);
|
||||
|
||||
//
|
||||
// Called by the UVM driver to register operations with RM. Only one set of
|
||||
// Called by the UVM driver to register event callbacks with RM. Only one set of
|
||||
// callbacks can be registered by any driver at a time. If another set of
|
||||
// callbacks was already registered, NV_ERR_IN_USE is returned.
|
||||
//
|
||||
NV_STATUS nvUvmInterfaceRegisterUvmCallbacks(struct UvmOpsUvmEvents *importedUvmOps);
|
||||
NV_STATUS nvUvmInterfaceRegisterUvmEvents(struct UvmEventsLinux *importedEvents);
|
||||
|
||||
//
|
||||
// Counterpart to nvUvmInterfaceRegisterUvmCallbacks. This must only be called
|
||||
// if nvUvmInterfaceRegisterUvmCallbacks returned NV_OK.
|
||||
// Counterpart to nvUvmInterfaceRegisterUvmEvents. This must only be called if
|
||||
// nvUvmInterfaceRegisterUvmEvents returned NV_OK.
|
||||
//
|
||||
// Upon return, the caller is guaranteed that any outstanding callbacks are done
|
||||
// and no new ones will be invoked.
|
||||
//
|
||||
void nvUvmInterfaceDeRegisterUvmOps(void);
|
||||
void nvUvmInterfaceDeRegisterUvmEvents(void);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceGetNvlinkInfo
|
||||
|
||||
Gets NVLINK information from RM.
|
||||
|
||||
Arguments:
|
||||
device[IN] - GPU device handle
|
||||
nvlinkInfo [OUT] - Pointer to NvlinkInfo structure
|
||||
|
||||
Error codes:
|
||||
NV_ERROR
|
||||
NV_ERR_INVALID_ARGUMENT
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceGetNvlinkInfo(uvmGpuDeviceHandle device,
|
||||
UvmGpuNvlinkInfo *nvlinkInfo);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceP2pObjectCreate
|
||||
@@ -1087,7 +1130,8 @@ void nvUvmInterfaceDeRegisterUvmOps(void);
|
||||
|
||||
Error codes:
|
||||
NV_ERR_INVALID_ARGUMENT
|
||||
NV_ERR_OBJECT_NOT_FOUND : If device object associated with the uuids aren't found.
|
||||
NV_ERR_OBJECT_NOT_FOUND : If device object associated with the device
|
||||
handles isn't found.
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceP2pObjectCreate(uvmGpuDeviceHandle device1,
|
||||
uvmGpuDeviceHandle device2,
|
||||
@@ -1147,6 +1191,46 @@ NV_STATUS nvUvmInterfaceGetExternalAllocPtes(uvmGpuAddressSpaceHandle vaSpace,
|
||||
NvU64 size,
|
||||
UvmGpuExternalMappingInfo *gpuExternalMappingInfo);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceGetExternalAllocPhysAddrs
|
||||
|
||||
The interface builds the RM physical addrs using the provided input parameters.
|
||||
|
||||
Arguments:
|
||||
vaSpace[IN] - vaSpace handle.
|
||||
hMemory[IN] - Memory handle.
|
||||
offset [IN] - Offset from the beginning of the allocation
|
||||
where PTE mappings should begin.
|
||||
Should be aligned with mappingPagesize
|
||||
in gpuExternalMappingInfo associated
|
||||
with the allocation.
|
||||
size [IN] - Length of the allocation for which PhysAddrs
|
||||
should be built.
|
||||
Should be aligned with mappingPagesize
|
||||
in gpuExternalMappingInfo associated
|
||||
with the allocation.
|
||||
size = 0 will be interpreted as the total size
|
||||
of the allocation.
|
||||
gpuExternalMappingInfo[IN/OUT] - See nv_uvm_types.h for more information.
|
||||
|
||||
Error codes:
|
||||
NV_ERR_INVALID_ARGUMENT - Invalid parameter/s is passed.
|
||||
NV_ERR_INVALID_OBJECT_HANDLE - Invalid memory handle is passed.
|
||||
NV_ERR_NOT_SUPPORTED - Functionality is not supported (see comments in nv_gpu_ops.c)
|
||||
NV_ERR_INVALID_BASE - offset is beyond the allocation size
|
||||
NV_ERR_INVALID_LIMIT - (offset + size) is beyond the allocation size.
|
||||
NV_ERR_BUFFER_TOO_SMALL - gpuExternalMappingInfo.physAddrBufferSize is insufficient to
|
||||
store single physAddr.
|
||||
NV_ERR_NOT_READY - Returned when querying the physAddrs requires a deferred setup
|
||||
which has not yet completed. It is expected that the caller
|
||||
will reattempt the call until a different code is returned.
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceGetExternalAllocPhysAddrs(uvmGpuAddressSpaceHandle vaSpace,
|
||||
NvHandle hMemory,
|
||||
NvU64 offset,
|
||||
NvU64 size,
|
||||
UvmGpuExternalPhysAddrInfo *gpuExternalPhysAddrsInfo);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceRetainChannel
|
||||
|
||||
@@ -1449,18 +1533,17 @@ NV_STATUS nvUvmInterfacePagingChannelPushStream(UvmGpuPagingChannelHandle channe
|
||||
NvU32 methodStreamSize);
|
||||
|
||||
/*******************************************************************************
|
||||
CSL Interface and Locking
|
||||
nvUvmInterfaceReportFatalError
|
||||
|
||||
The following functions do not acquire the RM API or GPU locks and must not be called
|
||||
concurrently with the same UvmCslContext parameter in different threads. The caller must
|
||||
guarantee this exclusion.
|
||||
Reports a global fatal error so RM can inform the clients that a node reboot
|
||||
is necessary to recover from this error. This function can be called from
|
||||
any lock environment, bottom half or non-interrupt context.
|
||||
|
||||
* nvUvmInterfaceCslRotateIv
|
||||
* nvUvmInterfaceCslEncrypt
|
||||
* nvUvmInterfaceCslDecrypt
|
||||
* nvUvmInterfaceCslSign
|
||||
* nvUvmInterfaceCslQueryMessagePool
|
||||
* nvUvmInterfaceCslIncrementIv
|
||||
*/
|
||||
void nvUvmInterfaceReportFatalError(NV_STATUS error);
|
||||
|
||||
/*******************************************************************************
|
||||
Cryptography Services Library (CSL) Interface
|
||||
*/
|
||||
|
||||
/*******************************************************************************
|
||||
@@ -1471,8 +1554,11 @@ NV_STATUS nvUvmInterfacePagingChannelPushStream(UvmGpuPagingChannelHandle channe
|
||||
The lifetime of the context is the same as the lifetime of the secure channel
|
||||
it is paired with.
|
||||
|
||||
Locking: This function acquires an API lock.
|
||||
Memory : This function dynamically allocates memory.
|
||||
|
||||
Arguments:
|
||||
uvmCslContext[IN/OUT] - The CSL context.
|
||||
uvmCslContext[IN/OUT] - The CSL context associated with a channel.
|
||||
channel[IN] - Handle to a secure channel.
|
||||
|
||||
Error codes:
|
||||
@@ -1490,30 +1576,62 @@ NV_STATUS nvUvmInterfaceCslInitContext(UvmCslContext *uvmCslContext,
|
||||
|
||||
If context is already deinitialized then function returns immediately.
|
||||
|
||||
Locking: This function does not acquire an API or GPU lock.
|
||||
Memory : This function may free memory.
|
||||
|
||||
Arguments:
|
||||
uvmCslContext[IN] - The CSL context.
|
||||
uvmCslContext[IN] - The CSL context associated with a channel.
|
||||
*/
|
||||
void nvUvmInterfaceDeinitCslContext(UvmCslContext *uvmCslContext);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceCslRotateKey
|
||||
|
||||
Disables channels and rotates keys.
|
||||
|
||||
This function disables channels and rotates associated keys. The channels
|
||||
associated with the given CSL contexts must be idled before this function is
|
||||
called. To trigger key rotation all allocated channels for a given key must
|
||||
be present in the list. If the function returns successfully then the CSL
|
||||
contexts have been updated with the new key.
|
||||
|
||||
Locking: This function attempts to acquire the GPU lock. In case of failure
|
||||
to acquire the return code is NV_ERR_STATE_IN_USE. The caller must
|
||||
guarantee that no CSL function, including this one, is invoked
|
||||
concurrently with the CSL contexts in contextList.
|
||||
Memory : This function dynamically allocates memory.
|
||||
|
||||
Arguments:
|
||||
contextList[IN/OUT] - An array of pointers to CSL contexts.
|
||||
contextListCount[IN] - Number of CSL contexts in contextList. Its value
|
||||
must be greater than 0.
|
||||
Error codes:
|
||||
NV_ERR_INVALID_ARGUMENT - contextList is NULL or contextListCount is 0.
|
||||
NV_ERR_STATE_IN_USE - Unable to acquire lock / resource. Caller
|
||||
can retry at a later time.
|
||||
NV_ERR_GENERIC - A failure other than _STATE_IN_USE occurred
|
||||
when attempting to acquire a lock.
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceCslRotateKey(UvmCslContext *contextList[],
|
||||
NvU32 contextListCount);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceCslRotateIv
|
||||
|
||||
Rotates the IV for a given channel and operation.
|
||||
|
||||
This function will rotate the IV on both the CPU and the GPU.
|
||||
Outstanding messages that have been encrypted by the GPU should first be
|
||||
decrypted before calling this function with operation equal to
|
||||
UVM_CSL_OPERATION_DECRYPT. Similarly, outstanding messages that have been
|
||||
encrypted by the CPU should first be decrypted before calling this function
|
||||
with operation equal to UVM_CSL_OPERATION_ENCRYPT. For a given operation
|
||||
the channel must be idle before calling this function. This function can be
|
||||
called regardless of the value of the IV's message counter.
|
||||
For a given operation the channel must be idle before calling this function.
|
||||
This function can be called regardless of the value of the IV's message counter.
|
||||
|
||||
See "CSL Interface and Locking" for locking requirements.
|
||||
This function does not perform dynamic memory allocation.
|
||||
Locking: This function attempts to acquire the GPU lock. In case of failure to
|
||||
acquire the return code is NV_ERR_STATE_IN_USE. The caller must guarantee
|
||||
that no CSL function, including this one, is invoked concurrently with
|
||||
the same CSL context.
|
||||
Memory : This function does not dynamically allocate memory.
|
||||
|
||||
Arguments:
|
||||
uvmCslContext[IN/OUT] - The CSL context.
|
||||
uvmCslContext[IN/OUT] - The CSL context associated with a channel.
|
||||
operation[IN] - Either
|
||||
- UVM_CSL_OPERATION_ENCRYPT
|
||||
- UVM_CSL_OPERATION_DECRYPT
|
||||
@@ -1521,7 +1639,11 @@ Arguments:
|
||||
Error codes:
|
||||
NV_ERR_INSUFFICIENT_RESOURCES - The rotate operation would cause a counter
|
||||
to overflow.
|
||||
NV_ERR_STATE_IN_USE - Unable to acquire lock / resource. Caller
|
||||
can retry at a later time.
|
||||
NV_ERR_INVALID_ARGUMENT - Invalid value for operation.
|
||||
NV_ERR_GENERIC - A failure other than _STATE_IN_USE occurred
|
||||
when attempting to acquire a lock.
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceCslRotateIv(UvmCslContext *uvmCslContext,
|
||||
UvmCslOperation operation);
|
||||
@@ -1538,11 +1660,13 @@ NV_STATUS nvUvmInterfaceCslRotateIv(UvmCslContext *uvmCslContext,
|
||||
The encryptIV can be obtained from nvUvmInterfaceCslIncrementIv.
|
||||
However, it is optional. If it is NULL, the next IV in line will be used.
|
||||
|
||||
See "CSL Interface and Locking" for locking requirements.
|
||||
This function does not perform dynamic memory allocation.
|
||||
Locking: This function does not acquire an API or GPU lock.
|
||||
The caller must guarantee that no CSL function, including this one,
|
||||
is invoked concurrently with the same CSL context.
|
||||
Memory : This function does not dynamically allocate memory.
|
||||
|
||||
Arguments:
|
||||
uvmCslContext[IN/OUT] - The CSL context.
|
||||
uvmCslContext[IN/OUT] - The CSL context associated with a channel.
|
||||
bufferSize[IN] - Size of the input and output buffers in
|
||||
units of bytes. Value can range from 1 byte
|
||||
to (2^32) - 1 bytes.
|
||||
@@ -1553,8 +1677,9 @@ Arguments:
|
||||
Its size is UVM_CSL_CRYPT_AUTH_TAG_SIZE_BYTES.
|
||||
|
||||
Error codes:
|
||||
NV_ERR_INVALID_ARGUMENT - The size of the data is 0 bytes.
|
||||
- The encryptIv has already been used.
|
||||
NV_ERR_INVALID_ARGUMENT - The CSL context is not associated with a channel.
|
||||
- The size of the data is 0 bytes.
|
||||
- The encryptIv has already been used.
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceCslEncrypt(UvmCslContext *uvmCslContext,
|
||||
NvU32 bufferSize,
|
||||
@@ -1573,8 +1698,15 @@ NV_STATUS nvUvmInterfaceCslEncrypt(UvmCslContext *uvmCslContext,
|
||||
maximized when the input and output buffers are 16-byte aligned. This is
|
||||
natural alignment for AES block.
|
||||
|
||||
See "CSL Interface and Locking" for locking requirements.
|
||||
This function does not perform dynamic memory allocation.
|
||||
During a key rotation event the previous key is stored in the CSL context.
|
||||
This allows data encrypted by the GPU to be decrypted with the previous key.
|
||||
The keyRotationId parameter identifies which key is used. The first key rotation
|
||||
ID has a value of 0 that increments by one for each key rotation event.
|
||||
|
||||
Locking: This function does not acquire an API or GPU lock.
|
||||
The caller must guarantee that no CSL function, including this one,
|
||||
is invoked concurrently with the same CSL context.
|
||||
Memory : This function does not dynamically allocate memory.
|
||||
|
||||
Arguments:
|
||||
uvmCslContext[IN/OUT] - The CSL context.
|
||||
@@ -1583,6 +1715,8 @@ NV_STATUS nvUvmInterfaceCslEncrypt(UvmCslContext *uvmCslContext,
|
||||
decryptIv[IN] - IV used to decrypt the ciphertext. Its value can either be given by
|
||||
nvUvmInterfaceCslIncrementIv, or, if NULL, the CSL context's
|
||||
internal counter is used.
|
||||
keyRotationId[IN] - Specifies the key that is used for decryption.
|
||||
A value of NV_U32_MAX specifies the current key.
|
||||
inputBuffer[IN] - Address of ciphertext input buffer.
|
||||
outputBuffer[OUT] - Address of plaintext output buffer.
|
||||
addAuthData[IN] - Address of the plaintext additional authenticated data used to
|
||||
@@ -1603,6 +1737,7 @@ NV_STATUS nvUvmInterfaceCslDecrypt(UvmCslContext *uvmCslContext,
|
||||
NvU32 bufferSize,
|
||||
NvU8 const *inputBuffer,
|
||||
UvmCslIv const *decryptIv,
|
||||
NvU32 keyRotationId,
|
||||
NvU8 *outputBuffer,
|
||||
NvU8 const *addAuthData,
|
||||
NvU32 addAuthDataSize,
|
||||
@@ -1616,11 +1751,13 @@ NV_STATUS nvUvmInterfaceCslDecrypt(UvmCslContext *uvmCslContext,
|
||||
Auth and input buffers must not overlap. If they do then calling this function produces
|
||||
undefined behavior.
|
||||
|
||||
See "CSL Interface and Locking" for locking requirements.
|
||||
This function does not perform dynamic memory allocation.
|
||||
Locking: This function does not acquire an API or GPU lock.
|
||||
The caller must guarantee that no CSL function, including this one,
|
||||
is invoked concurrently with the same CSL context.
|
||||
Memory : This function does not dynamically allocate memory.
|
||||
|
||||
Arguments:
|
||||
uvmCslContext[IN/OUT] - The CSL context.
|
||||
uvmCslContext[IN/OUT] - The CSL context associated with a channel.
|
||||
bufferSize[IN] - Size of the input buffer in units of bytes.
|
||||
Value can range from 1 byte to (2^32) - 1 bytes.
|
||||
inputBuffer[IN] - Address of plaintext input buffer.
|
||||
@@ -1629,7 +1766,8 @@ NV_STATUS nvUvmInterfaceCslDecrypt(UvmCslContext *uvmCslContext,
|
||||
|
||||
Error codes:
|
||||
NV_ERR_INSUFFICIENT_RESOURCES - The signing operation would cause a counter overflow to occur.
|
||||
NV_ERR_INVALID_ARGUMENT - The size of the data is 0 bytes.
|
||||
NV_ERR_INVALID_ARGUMENT - The CSL context is not associated with a channel.
|
||||
- The size of the data is 0 bytes.
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceCslSign(UvmCslContext *uvmCslContext,
|
||||
NvU32 bufferSize,
|
||||
@@ -1641,8 +1779,10 @@ NV_STATUS nvUvmInterfaceCslSign(UvmCslContext *uvmCslContext,
|
||||
|
||||
Returns the number of messages that can be encrypted before the message counter will overflow.
|
||||
|
||||
See "CSL Interface and Locking" for locking requirements.
|
||||
This function does not perform dynamic memory allocation.
|
||||
Locking: This function does not acquire an API or GPU lock.
|
||||
Memory : This function does not dynamically allocate memory.
|
||||
The caller must guarantee that no CSL function, including this one,
|
||||
is invoked concurrently with the same CSL context.
|
||||
|
||||
Arguments:
|
||||
uvmCslContext[IN/OUT] - The CSL context.
|
||||
@@ -1666,8 +1806,10 @@ NV_STATUS nvUvmInterfaceCslQueryMessagePool(UvmCslContext *uvmCslContext,
|
||||
can be used in nvUvmInterfaceCslEncrypt. If operation is UVM_CSL_OPERATION_DECRYPT then
|
||||
the returned IV can be used in nvUvmInterfaceCslDecrypt.
|
||||
|
||||
See "CSL Interface and Locking" for locking requirements.
|
||||
This function does not perform dynamic memory allocation.
|
||||
Locking: This function does not acquire an API or GPU lock.
|
||||
The caller must guarantee that no CSL function, including this one,
|
||||
is invoked concurrently with the same CSL context.
|
||||
Memory : This function does not dynamically allocate memory.
|
||||
|
||||
Arguments:
|
||||
uvmCslContext[IN/OUT] - The CSL context.
|
||||
@@ -1675,7 +1817,7 @@ Arguments:
|
||||
- UVM_CSL_OPERATION_ENCRYPT
|
||||
- UVM_CSL_OPERATION_DECRYPT
|
||||
increment[IN] - The amount by which the IV is incremented. Can be 0.
|
||||
iv[out] - If non-NULL, a buffer to store the incremented IV.
|
||||
iv[OUT] - If non-NULL, a buffer to store the incremented IV.
|
||||
|
||||
Error codes:
|
||||
NV_ERR_INVALID_ARGUMENT - The value of the operation parameter is illegal.
|
||||
@@ -1687,4 +1829,41 @@ NV_STATUS nvUvmInterfaceCslIncrementIv(UvmCslContext *uvmCslContext,
|
||||
NvU64 increment,
|
||||
UvmCslIv *iv);
|
||||
|
||||
/*******************************************************************************
|
||||
nvUvmInterfaceCslLogEncryption
|
||||
|
||||
Checks and logs information about encryptions associated with the given
|
||||
CSL context.
|
||||
|
||||
For contexts associated with channels, this function does not modify elements of
|
||||
the UvmCslContext, and must be called for every CPU/GPU encryption.
|
||||
|
||||
For the context associated with fault buffers, bufferSize can encompass multiple
|
||||
encryption invocations, and the UvmCslContext will be updated following a key
|
||||
rotation event.
|
||||
|
||||
In either case the IV remains unmodified after this function is called.
|
||||
|
||||
Locking: This function does not acquire an API or GPU lock.
|
||||
Memory : This function does not dynamically allocate memory.
|
||||
The caller must guarantee that no CSL function, including this one,
|
||||
is invoked concurrently with the same CSL context.
|
||||
|
||||
Arguments:
|
||||
uvmCslContext[IN/OUT] - The CSL context.
|
||||
operation[IN] - If the CSL context is associated with a fault
|
||||
buffer, this argument is ignored. If it is
|
||||
associated with a channel, it must be either
|
||||
- UVM_CSL_OPERATION_ENCRYPT
|
||||
- UVM_CSL_OPERATION_DECRYPT
|
||||
bufferSize[IN] - The size of the buffer(s) encrypted by the
|
||||
external entity in units of bytes.
|
||||
|
||||
Error codes:
|
||||
NV_ERR_INSUFFICIENT_RESOURCES - The encryption would cause a counter
|
||||
to overflow.
|
||||
*/
|
||||
NV_STATUS nvUvmInterfaceCslLogEncryption(UvmCslContext *uvmCslContext,
|
||||
UvmCslOperation operation,
|
||||
NvU32 bufferSize);
|
||||
#endif // _NV_UVM_INTERFACE_H_
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -22,7 +22,8 @@
|
||||
*/
|
||||
|
||||
//
|
||||
// This file provides common types for both UVM driver and RM's UVM interface.
|
||||
// This file provides common types for both the UVM kernel driver and RM's UVM
|
||||
// interface.
|
||||
//
|
||||
|
||||
#ifndef _NV_UVM_TYPES_H_
|
||||
@@ -32,20 +33,9 @@
|
||||
#include "nvstatus.h"
|
||||
#include "nvgputypes.h"
|
||||
#include "nvCpuUuid.h"
|
||||
#include "nv_uvm_user_types.h" // For UvmGpuCachingType, UvmGpuMappingType, etc
|
||||
|
||||
|
||||
//
|
||||
// Default Page Size if left "0" because in RM BIG page size is default & there
|
||||
// are multiple BIG page sizes in RM. These defines are used as flags to "0"
|
||||
// should be OK when user is not sure which pagesize allocation it wants
|
||||
//
|
||||
#define UVM_PAGE_SIZE_DEFAULT 0x0
|
||||
#define UVM_PAGE_SIZE_4K 0x1000
|
||||
#define UVM_PAGE_SIZE_64K 0x10000
|
||||
#define UVM_PAGE_SIZE_128K 0x20000
|
||||
#define UVM_PAGE_SIZE_2M 0x200000
|
||||
#define UVM_PAGE_SIZE_512M 0x20000000
|
||||
|
||||
//
|
||||
// When modifying flags, make sure they are compatible with the mirrored
|
||||
// PMA_* flags in phys_mem_allocator.h.
|
||||
@@ -80,9 +70,6 @@
|
||||
//
|
||||
#define UVM_PMA_CALLED_FROM_PMA_EVICTION 16384
|
||||
|
||||
#define UVM_UUID_LEN 16
|
||||
#define UVM_SW_OBJ_SUBCHANNEL 5
|
||||
|
||||
typedef unsigned long long UvmGpuPointer;
|
||||
|
||||
//
|
||||
@@ -104,6 +91,10 @@ typedef struct UvmGpuMemoryInfo_tag
|
||||
// Out: Set to TRUE, if the allocation is in sysmem.
|
||||
NvBool sysmem;
|
||||
|
||||
// Out: Set to TRUE, if this allocation is treated as EGM.
|
||||
// sysmem is also TRUE when egm is TRUE.
|
||||
NvBool egm;
|
||||
|
||||
// Out: Set to TRUE, if the allocation is a constructed
|
||||
// under a Device or Subdevice.
|
||||
// All permutations of sysmem and deviceDescendant are valid.
|
||||
@@ -125,6 +116,10 @@ typedef struct UvmGpuMemoryInfo_tag
|
||||
|
||||
// Out: Uuid of the GPU to which the allocation belongs.
|
||||
// This is only valid if deviceDescendant is NV_TRUE.
|
||||
// When egm is NV_TRUE, this is also the UUID of the GPU
|
||||
// for which EGM is local.
|
||||
// If the GPU has SMC enabled, the UUID is the GI UUID.
|
||||
// Otherwise, it is the UUID for the physical GPU.
|
||||
// Note: If the allocation is owned by a device in
|
||||
// an SLI group and the allocation is broadcast
|
||||
// across the SLI group, this UUID will be any one
|
||||
@@ -226,9 +221,11 @@ typedef struct UvmGpuChannelInstanceInfo_tag
|
||||
// Ampere+ GPUs
|
||||
volatile NvU32 *pChramChannelRegister;
|
||||
|
||||
// Out: Address of the Runlist PRI Base Register required to ring the
|
||||
// doorbell after clearing the faulted bit.
|
||||
volatile NvU32 *pRunlistPRIBaseRegister;
|
||||
// Out: Address of the doorbell.
|
||||
volatile NvU32 *workSubmissionOffset;
|
||||
|
||||
// Out: channel handle required to ring the doorbell.
|
||||
NvU32 workSubmissionToken;
|
||||
|
||||
// Out: SMC engine id to which the GR channel is bound, or zero if the GPU
|
||||
// does not support SMC or it is a CE channel
|
||||
@@ -260,6 +257,8 @@ typedef struct UvmGpuChannelInfo_tag
|
||||
// The errorNotifier is filled out when the channel hits an RC error.
|
||||
NvNotification *errorNotifier;
|
||||
|
||||
NvNotification *keyRotationNotifier;
|
||||
|
||||
NvU32 hwRunlistId;
|
||||
NvU32 hwChannelId;
|
||||
|
||||
@@ -284,13 +283,14 @@ typedef struct UvmGpuChannelInfo_tag
|
||||
|
||||
// GPU VAs of both GPFIFO and GPPUT are needed in Confidential Computing
|
||||
// so a channel can be controlled via another channel (SEC2 or WLC/LCIC)
|
||||
NvU64 gpFifoGpuVa;
|
||||
NvU64 gpPutGpuVa;
|
||||
NvU64 gpGetGpuVa;
|
||||
NvU64 gpFifoGpuVa;
|
||||
NvU64 gpPutGpuVa;
|
||||
NvU64 gpGetGpuVa;
|
||||
|
||||
// GPU VA of work submission offset is needed in Confidential Computing
|
||||
// so CE channels can ring doorbell of other channels as required for
|
||||
// WLC/LCIC work submission
|
||||
NvU64 workSubmissionOffsetGpuVa;
|
||||
NvU64 workSubmissionOffsetGpuVa;
|
||||
} UvmGpuChannelInfo;
|
||||
|
||||
typedef enum
|
||||
@@ -321,10 +321,6 @@ typedef struct UvmGpuChannelAllocParams_tag
|
||||
// The next two fields store UVM_BUFFER_LOCATION values
|
||||
NvU32 gpFifoLoc;
|
||||
NvU32 gpPutLoc;
|
||||
|
||||
// Allocate the channel as secure. This flag should only be set when
|
||||
// Confidential Compute is enabled.
|
||||
NvBool secure;
|
||||
} UvmGpuChannelAllocParams;
|
||||
|
||||
typedef struct UvmGpuPagingChannelAllocParams_tag
|
||||
@@ -371,6 +367,9 @@ typedef struct
|
||||
// True if the CE supports encryption
|
||||
NvBool secure:1;
|
||||
|
||||
// True if the CE can be used for fast scrub
|
||||
NvBool scrub:1;
|
||||
|
||||
// Mask of physical CEs assigned to this LCE
|
||||
//
|
||||
// The value returned by RM for this field may change when a GPU is
|
||||
@@ -393,6 +392,8 @@ typedef enum
|
||||
UVM_LINK_TYPE_NVLINK_2,
|
||||
UVM_LINK_TYPE_NVLINK_3,
|
||||
UVM_LINK_TYPE_NVLINK_4,
|
||||
UVM_LINK_TYPE_NVLINK_5,
|
||||
UVM_LINK_TYPE_C2C,
|
||||
} UVM_LINK_TYPE;
|
||||
|
||||
typedef struct UvmGpuCaps_tag
|
||||
@@ -437,80 +438,22 @@ typedef struct UvmGpuAllocInfo_tag
|
||||
// SEV or GPU CC modes are enabled. Ignored otherwise
|
||||
} UvmGpuAllocInfo;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
UVM_VIRT_MODE_NONE = 0, // Baremetal or passthrough virtualization
|
||||
UVM_VIRT_MODE_LEGACY = 1, // Virtualization without SRIOV support
|
||||
UVM_VIRT_MODE_SRIOV_HEAVY = 2, // Virtualization with SRIOV Heavy configured
|
||||
UVM_VIRT_MODE_SRIOV_STANDARD = 3, // Virtualization with SRIOV Standard configured
|
||||
UVM_VIRT_MODE_COUNT = 4,
|
||||
} UVM_VIRT_MODE;
|
||||
|
||||
// !!! The following enums (with UvmRm prefix) are defined and documented in
|
||||
// mm/uvm/interface/uvm_types.h and must be mirrored. Please refer to that file
|
||||
// for more details.
|
||||
|
||||
// UVM GPU mapping types
|
||||
typedef enum
|
||||
{
|
||||
UvmRmGpuMappingTypeDefault = 0,
|
||||
UvmRmGpuMappingTypeReadWriteAtomic = 1,
|
||||
UvmRmGpuMappingTypeReadWrite = 2,
|
||||
UvmRmGpuMappingTypeReadOnly = 3,
|
||||
UvmRmGpuMappingTypeCount = 4
|
||||
} UvmRmGpuMappingType;
|
||||
|
||||
// UVM GPU caching types
|
||||
typedef enum
|
||||
{
|
||||
UvmRmGpuCachingTypeDefault = 0,
|
||||
UvmRmGpuCachingTypeForceUncached = 1,
|
||||
UvmRmGpuCachingTypeForceCached = 2,
|
||||
UvmRmGpuCachingTypeCount = 3
|
||||
} UvmRmGpuCachingType;
|
||||
|
||||
// UVM GPU format types
|
||||
typedef enum {
|
||||
UvmRmGpuFormatTypeDefault = 0,
|
||||
UvmRmGpuFormatTypeBlockLinear = 1,
|
||||
UvmRmGpuFormatTypeCount = 2
|
||||
} UvmRmGpuFormatType;
|
||||
|
||||
// UVM GPU Element bits types
|
||||
typedef enum {
|
||||
UvmRmGpuFormatElementBitsDefault = 0,
|
||||
UvmRmGpuFormatElementBits8 = 1,
|
||||
UvmRmGpuFormatElementBits16 = 2,
|
||||
// Cuda does not support 24-bit width
|
||||
UvmRmGpuFormatElementBits32 = 4,
|
||||
UvmRmGpuFormatElementBits64 = 5,
|
||||
UvmRmGpuFormatElementBits128 = 6,
|
||||
UvmRmGpuFormatElementBitsCount = 7
|
||||
} UvmRmGpuFormatElementBits;
|
||||
|
||||
// UVM GPU Compression types
|
||||
typedef enum {
|
||||
UvmRmGpuCompressionTypeDefault = 0,
|
||||
UvmRmGpuCompressionTypeEnabledNoPlc = 1,
|
||||
UvmRmGpuCompressionTypeCount = 2
|
||||
} UvmRmGpuCompressionType;
|
||||
|
||||
typedef struct UvmGpuExternalMappingInfo_tag
|
||||
{
|
||||
// In: GPU caching ability.
|
||||
UvmRmGpuCachingType cachingType;
|
||||
UvmGpuCachingType cachingType;
|
||||
|
||||
// In: Virtual permissions.
|
||||
UvmRmGpuMappingType mappingType;
|
||||
UvmGpuMappingType mappingType;
|
||||
|
||||
// In: RM virtual mapping memory format
|
||||
UvmRmGpuFormatType formatType;
|
||||
UvmGpuFormatType formatType;
|
||||
|
||||
// In: RM virtual mapping element bits
|
||||
UvmRmGpuFormatElementBits elementBits;
|
||||
UvmGpuFormatElementBits elementBits;
|
||||
|
||||
// In: RM virtual compression type
|
||||
UvmRmGpuCompressionType compressionType;
|
||||
UvmGpuCompressionType compressionType;
|
||||
|
||||
// In: Size of the buffer to store PTEs (in bytes).
|
||||
NvU64 pteBufferSize;
|
||||
@@ -536,14 +479,51 @@ typedef struct UvmGpuExternalMappingInfo_tag
|
||||
|
||||
// Out: PTE size (in bytes)
|
||||
NvU32 pteSize;
|
||||
|
||||
// Out: UVM needs to invalidate L2 at unmap
|
||||
NvBool bNeedL2InvalidateAtUnmap;
|
||||
} UvmGpuExternalMappingInfo;
|
||||
|
||||
typedef struct UvmGpuExternalPhysAddrInfo_tag
|
||||
{
|
||||
// In: Virtual permissions. Returns
|
||||
// NV_ERR_INVALID_ACCESS_TYPE if input is
|
||||
// inaccurate
|
||||
UvmGpuMappingType mappingType;
|
||||
|
||||
// In: Size of the buffer to store PhysAddrs (in bytes).
|
||||
NvU64 physAddrBufferSize;
|
||||
|
||||
// In: Page size for mapping
|
||||
// If this field is passed as 0, the page size
|
||||
// of the allocation is used for mapping.
|
||||
// nvUvmInterfaceGetExternalAllocPtes must pass
|
||||
// this field as zero.
|
||||
NvU64 mappingPageSize;
|
||||
|
||||
// In: Pointer to a buffer to store PhysAddrs.
|
||||
// Out: The interface will fill the buffer with PhysAddrs
|
||||
NvU64 *physAddrBuffer;
|
||||
|
||||
// Out: Number of PhysAddrs filled in to the buffer.
|
||||
NvU64 numWrittenPhysAddrs;
|
||||
|
||||
// Out: Number of PhysAddrs remaining to be filled
|
||||
// if the buffer is not sufficient to accommodate
|
||||
// requested PhysAddrs.
|
||||
NvU64 numRemainingPhysAddrs;
|
||||
} UvmGpuExternalPhysAddrInfo;
|
||||
|
||||
typedef struct UvmGpuP2PCapsParams_tag
|
||||
{
|
||||
// Out: peerId[i] contains gpu[i]'s peer id of gpu[1 - i]. Only defined if
|
||||
// the GPUs are direct peers.
|
||||
NvU32 peerIds[2];
|
||||
|
||||
// Out: peerId[i] contains gpu[i]'s EGM peer id of gpu[1 - i]. Only defined
|
||||
// if the GPUs are direct peers and EGM enabled in the system.
|
||||
NvU32 egmPeerIds[2];
|
||||
|
||||
// Out: UVM_LINK_TYPE
|
||||
NvU32 p2pLink;
|
||||
|
||||
@@ -560,10 +540,16 @@ typedef struct UvmGpuP2PCapsParams_tag
|
||||
// bandwidth for indirect peers is zero.
|
||||
NvU32 totalLinkLineRateMBps;
|
||||
|
||||
// Out: True if the peers have a indirect link to communicate. On P9
|
||||
// systems, this is true if peers are connected to different NPUs that
|
||||
// forward the requests between them.
|
||||
NvU32 indirectAccess : 1;
|
||||
// Out: IOMMU/DMA mappings of bar1 of the respective peer vidmem.
|
||||
// Size is 0 if bar1 p2p is not supported.
|
||||
NvU64 bar1DmaAddress[2];
|
||||
NvU64 bar1DmaSize[2];
|
||||
|
||||
// True if GPU i can use PCIe atomics on locations in GPU[i-1]
|
||||
// BAR1. This implies that GPU[i] can issue PCIe atomics,
|
||||
// GPU[i-1] can accept PCIe atomics, and the bus interconnect
|
||||
// between the two GPUs can correctly route PCIe atomics.
|
||||
NvBool bar1PcieAtomics[2];
|
||||
} UvmGpuP2PCapsParams;
|
||||
|
||||
// Platform-wide information
|
||||
@@ -572,8 +558,11 @@ typedef struct UvmPlatformInfo_tag
|
||||
// Out: ATS (Address Translation Services) is supported
|
||||
NvBool atsSupported;
|
||||
|
||||
// Out: AMD SEV (Secure Encrypted Virtualization) is enabled
|
||||
NvBool sevEnabled;
|
||||
// Out: True if HW trusted execution, such as AMD's SEV-SNP or Intel's TDX,
|
||||
// is enabled in the VM, indicating that Confidential Computing must be
|
||||
// also enabled in the GPU(s); these two security features are either both
|
||||
// enabled, or both disabled.
|
||||
NvBool confComputingEnabled;
|
||||
} UvmPlatformInfo;
|
||||
|
||||
typedef struct UvmGpuClientInfo_tag
|
||||
@@ -583,18 +572,13 @@ typedef struct UvmGpuClientInfo_tag
|
||||
NvHandle hSmcPartRef;
|
||||
} UvmGpuClientInfo;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
UVM_GPU_CONF_COMPUTE_MODE_NONE,
|
||||
UVM_GPU_CONF_COMPUTE_MODE_APM,
|
||||
UVM_GPU_CONF_COMPUTE_MODE_HCC,
|
||||
UVM_GPU_CONF_COMPUTE_MODE_COUNT
|
||||
} UvmGpuConfComputeMode;
|
||||
|
||||
typedef struct UvmGpuConfComputeCaps_tag
|
||||
{
|
||||
// Out: GPU's confidential compute mode
|
||||
UvmGpuConfComputeMode mode;
|
||||
// Out: true if Confidential Computing is enabled on the GPU
|
||||
NvBool bConfComputingEnabled;
|
||||
|
||||
// Out: true if key rotation is enabled (for UVM keys) on the GPU
|
||||
NvBool bKeyRotationEnabled;
|
||||
} UvmGpuConfComputeCaps;
|
||||
|
||||
#define UVM_GPU_NAME_LENGTH 0x40
|
||||
@@ -604,7 +588,8 @@ typedef struct UvmGpuInfo_tag
|
||||
// Printable gpu name
|
||||
char name[UVM_GPU_NAME_LENGTH];
|
||||
|
||||
// Uuid of this gpu
|
||||
// Uuid of the physical GPU or GI UUID if nvUvmInterfaceGetGpuInfo()
|
||||
// requested information for a valid SMC partition.
|
||||
NvProcessorUuid uuid;
|
||||
|
||||
// Gpu architecture; NV2080_CTRL_MC_ARCH_INFO_ARCHITECTURE_*
|
||||
@@ -650,6 +635,9 @@ typedef struct UvmGpuInfo_tag
|
||||
// Maximum number of TPCs per GPC
|
||||
NvU32 maxTpcPerGpcCount;
|
||||
|
||||
// Number of access counter buffers.
|
||||
NvU32 accessCntrBufferCount;
|
||||
|
||||
// NV_TRUE if SMC is enabled on this GPU.
|
||||
NvBool smcEnabled;
|
||||
|
||||
@@ -686,6 +674,28 @@ typedef struct UvmGpuInfo_tag
|
||||
// to NVSwitch peers.
|
||||
NvBool connectedToSwitch;
|
||||
NvU64 nvswitchMemoryWindowStart;
|
||||
|
||||
// local EGM properties
|
||||
// NV_TRUE if EGM is enabled
|
||||
NvBool egmEnabled;
|
||||
|
||||
// Peer ID to reach local EGM when EGM is enabled
|
||||
NvU8 egmPeerId;
|
||||
|
||||
// EGM base address to offset in the GMMU PTE entry for EGM mappings
|
||||
NvU64 egmBaseAddr;
|
||||
|
||||
// If connectedToSwitch is NV_TRUE,
|
||||
// nvswitchEgmMemoryWindowStart tells the base address for the GPU's EGM memory in the
|
||||
// NVSwitch address space. It is used when creating PTEs of GPU memory mappings
|
||||
// to NVSwitch peers.
|
||||
NvU64 nvswitchEgmMemoryWindowStart;
|
||||
|
||||
// GPU supports ATS capability
|
||||
NvBool atsSupport;
|
||||
|
||||
// GPU supports Non-PASID ATS capability
|
||||
NvBool nonPasidAtsSupport;
|
||||
} UvmGpuInfo;
|
||||
|
||||
typedef struct UvmGpuFbInfo_tag
|
||||
@@ -694,9 +704,16 @@ typedef struct UvmGpuFbInfo_tag
|
||||
// RM regions that are not registered with PMA either.
|
||||
NvU64 maxAllocatableAddress;
|
||||
|
||||
NvU32 heapSize; // RAM in KB available for user allocations
|
||||
NvU32 reservedHeapSize; // RAM in KB reserved for internal RM allocation
|
||||
NvBool bZeroFb; // Zero FB mode enabled.
|
||||
NvU32 heapSize; // RAM in KB available for user allocations
|
||||
NvU32 reservedHeapSize; // RAM in KB reserved for internal RM allocation
|
||||
NvBool bZeroFb; // Zero FB mode enabled.
|
||||
NvU64 maxVidmemPageSize; // Largest GPU page size to access vidmem.
|
||||
NvBool bStaticBar1Enabled; // Static BAR1 mode is enabled
|
||||
NvBool bStaticBar1WriteCombined; // Write combined is enabled
|
||||
NvU64 staticBar1StartOffset; // The start offset of the the static mapping
|
||||
NvU64 staticBar1Size; // The size of the static mapping
|
||||
NvU32 heapStart; // The start offset of heap in KB, helpful for MIG
|
||||
// systems
|
||||
} UvmGpuFbInfo;
|
||||
|
||||
typedef struct UvmGpuEccInfo_tag
|
||||
@@ -708,6 +725,15 @@ typedef struct UvmGpuEccInfo_tag
|
||||
NvBool bEccEnabled;
|
||||
} UvmGpuEccInfo;
|
||||
|
||||
typedef struct UvmGpuNvlinkInfo_tag
|
||||
{
|
||||
unsigned nvlinkMask;
|
||||
unsigned nvlinkOffset;
|
||||
void *nvlinkReadLocation;
|
||||
NvBool *nvlinkErrorNotifier;
|
||||
NvBool bNvlinkRecoveryEnabled;
|
||||
} UvmGpuNvlinkInfo;
|
||||
|
||||
typedef struct UvmPmaAllocationOptions_tag
|
||||
{
|
||||
NvU32 flags;
|
||||
@@ -720,19 +746,6 @@ typedef struct UvmPmaAllocationOptions_tag
|
||||
NvU32 resultFlags; // valid if the allocation function returns NV_OK
|
||||
} UvmPmaAllocationOptions;
|
||||
|
||||
//
|
||||
// Mirrored in PMA (PMA_STATS)
|
||||
//
|
||||
typedef struct UvmPmaStatistics_tag
|
||||
{
|
||||
volatile NvU64 numPages2m; // PMA-wide 2MB pages count across all regions
|
||||
volatile NvU64 numFreePages64k; // PMA-wide free 64KB page count across all regions
|
||||
volatile NvU64 numFreePages2m; // PMA-wide free 2MB pages count across all regions
|
||||
volatile NvU64 numPages2mProtected; // PMA-wide 2MB pages count in protected memory
|
||||
volatile NvU64 numFreePages64kProtected; // PMA-wide free 64KB page count in protected memory
|
||||
volatile NvU64 numFreePages2mProtected; // PMA-wide free 2MB pages count in protected memory
|
||||
} UvmPmaStatistics;
|
||||
|
||||
/*******************************************************************************
|
||||
uvmEventSuspend
|
||||
This function will be called by the GPU driver to signal to UVM that the
|
||||
@@ -774,14 +787,14 @@ typedef NV_STATUS (*uvmEventResume_t) (void);
|
||||
/*******************************************************************************
|
||||
uvmEventStartDevice
|
||||
This function will be called by the GPU driver once it has finished its
|
||||
initialization to tell the UVM driver that this GPU has come up.
|
||||
initialization to tell the UVM driver that this physical GPU has come up.
|
||||
*/
|
||||
typedef NV_STATUS (*uvmEventStartDevice_t) (const NvProcessorUuid *pGpuUuidStruct);
|
||||
|
||||
/*******************************************************************************
|
||||
uvmEventStopDevice
|
||||
This function will be called by the GPU driver to let UVM know that a GPU
|
||||
is going down.
|
||||
This function will be called by the GPU driver to let UVM know that a
|
||||
physical GPU is going down.
|
||||
*/
|
||||
typedef NV_STATUS (*uvmEventStopDevice_t) (const NvProcessorUuid *pGpuUuidStruct);
|
||||
|
||||
@@ -812,25 +825,62 @@ typedef NV_STATUS (*uvmEventServiceInterrupt_t) (void *pDeviceObject,
|
||||
/*******************************************************************************
|
||||
uvmEventIsrTopHalf_t
|
||||
This function will be called by the GPU driver to let UVM know
|
||||
that an interrupt has occurred.
|
||||
that an interrupt has occurred on the given physical GPU.
|
||||
|
||||
Returns:
|
||||
NV_OK if the UVM driver handled the interrupt
|
||||
NV_ERR_NO_INTR_PENDING if the interrupt is not for the UVM driver
|
||||
*/
|
||||
#if defined (__linux__)
|
||||
typedef NV_STATUS (*uvmEventIsrTopHalf_t) (const NvProcessorUuid *pGpuUuidStruct);
|
||||
#else
|
||||
typedef void (*uvmEventIsrTopHalf_t) (void);
|
||||
#endif
|
||||
|
||||
struct UvmOpsUvmEvents
|
||||
/*******************************************************************************
|
||||
uvmEventDrainP2P
|
||||
This function will be called by the GPU driver to signal to UVM that the
|
||||
GPU has encountered an uncontained error, and all peer work must be drained
|
||||
to recover. When it is called, the following assumptions/guarantees are
|
||||
valid/made:
|
||||
|
||||
* Impacted user channels have been preempted and disabled
|
||||
* UVM channels are still running normally and will continue to do
|
||||
so unless an unrecoverable error is hit on said channels
|
||||
* UVM must not return from this function until all enqueued work on
|
||||
* peer channels has drained
|
||||
* In the context of this function call, RM will still service faults
|
||||
* UVM must prevent new peer work from being enqueued until the
|
||||
uvmEventResumeP2P callback is issued
|
||||
|
||||
Returns:
|
||||
NV_OK if UVM has idled peer work and will prevent new peer workloads.
|
||||
NV_ERR_TIMEOUT if peer work was unable to be drained within a timeout
|
||||
XXX NV_ERR_* for any other failure (TBD)
|
||||
|
||||
*/
|
||||
typedef NV_STATUS (*uvmEventDrainP2P_t) (const NvProcessorUuid *pGpuUuidStruct);
|
||||
|
||||
/*******************************************************************************
|
||||
uvmEventResumeP2P
|
||||
This function will be called by the GPU driver to signal to UVM that the
|
||||
GPU has recovered from the previously reported uncontained NVLINK error.
|
||||
When it is called, the following assumptions/guarantees are valid/made:
|
||||
|
||||
* UVM is again allowed to enqueue peer work
|
||||
* UVM channels are still running normally
|
||||
*/
|
||||
typedef NV_STATUS (*uvmEventResumeP2P_t) (const NvProcessorUuid *pGpuUuidStruct);
|
||||
|
||||
struct UvmEventsLinux
|
||||
{
|
||||
uvmEventIsrTopHalf_t isrTopHalf;
|
||||
uvmEventSuspend_t suspend;
|
||||
uvmEventResume_t resume;
|
||||
uvmEventDrainP2P_t drainP2P;
|
||||
uvmEventResumeP2P_t resumeP2P;
|
||||
};
|
||||
|
||||
struct UvmEventsWindows
|
||||
{
|
||||
uvmEventSuspend_t suspend;
|
||||
uvmEventResume_t resume;
|
||||
uvmEventStartDevice_t startDevice;
|
||||
uvmEventStopDevice_t stopDevice;
|
||||
uvmEventIsrTopHalf_t isrTopHalf;
|
||||
uvmEventStopDevice_t stopDevice;
|
||||
#if defined (_WIN32)
|
||||
uvmEventWddmResetDuringTimeout_t wddmResetDuringTimeout;
|
||||
uvmEventWddmRestartAfterTimeout_t wddmRestartAfterTimeout;
|
||||
@@ -851,6 +901,14 @@ typedef union UvmFaultMetadataPacket_tag
|
||||
NvU8 _padding[32];
|
||||
} UvmFaultMetadataPacket;
|
||||
|
||||
// This struct shall not be accessed nor modified directly by UVM as it is
|
||||
// entirely managed by the RM layer
|
||||
typedef struct UvmCslContext_tag
|
||||
{
|
||||
struct ccslContext_t *ctx;
|
||||
void *nvidia_stack;
|
||||
} UvmCslContext;
|
||||
|
||||
typedef struct UvmGpuFaultInfo_tag
|
||||
{
|
||||
struct
|
||||
@@ -892,26 +950,25 @@ typedef struct UvmGpuFaultInfo_tag
|
||||
NvU32 replayableFaultMask;
|
||||
|
||||
// Fault buffer CPU mapping
|
||||
void* bufferAddress;
|
||||
//
|
||||
// When Confidential Computing is disabled, the mapping points to the
|
||||
// actual HW fault buffer.
|
||||
//
|
||||
// When Confidential Computing is enabled, the mapping points to a
|
||||
// copy of the HW fault buffer. This "shadow buffer" is maintained
|
||||
// by GSP-RM.
|
||||
void* bufferAddress;
|
||||
|
||||
// Size, in bytes, of the fault buffer pointed by bufferAddress.
|
||||
NvU32 bufferSize;
|
||||
|
||||
// Mapping pointing to the start of the fault buffer metadata containing
|
||||
// a 16Byte authentication tag and a valid byte. Always NULL when
|
||||
// Confidential Computing is disabled.
|
||||
UvmFaultMetadataPacket *bufferMetadata;
|
||||
|
||||
// Indicates whether UVM owns the replayable fault buffer.
|
||||
// The value of this field is always NV_TRUE When Confidential Computing
|
||||
// is disabled.
|
||||
NvBool bUvmOwnsHwFaultBuffer;
|
||||
// CSL context used for performing decryption of replayable faults when
|
||||
// Confidential Computing is enabled.
|
||||
UvmCslContext cslCtx;
|
||||
} replayable;
|
||||
struct
|
||||
{
|
||||
@@ -981,32 +1038,9 @@ typedef struct UvmGpuAccessCntrInfo_tag
|
||||
NvHandle accessCntrBufferHandle;
|
||||
} UvmGpuAccessCntrInfo;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
UVM_ACCESS_COUNTER_GRANULARITY_64K = 1,
|
||||
UVM_ACCESS_COUNTER_GRANULARITY_2M = 2,
|
||||
UVM_ACCESS_COUNTER_GRANULARITY_16M = 3,
|
||||
UVM_ACCESS_COUNTER_GRANULARITY_16G = 4,
|
||||
} UVM_ACCESS_COUNTER_GRANULARITY;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
UVM_ACCESS_COUNTER_USE_LIMIT_NONE = 1,
|
||||
UVM_ACCESS_COUNTER_USE_LIMIT_QTR = 2,
|
||||
UVM_ACCESS_COUNTER_USE_LIMIT_HALF = 3,
|
||||
UVM_ACCESS_COUNTER_USE_LIMIT_FULL = 4,
|
||||
} UVM_ACCESS_COUNTER_USE_LIMIT;
|
||||
|
||||
typedef struct UvmGpuAccessCntrConfig_tag
|
||||
{
|
||||
NvU32 mimcGranularity;
|
||||
|
||||
NvU32 momcGranularity;
|
||||
|
||||
NvU32 mimcUseLimit;
|
||||
|
||||
NvU32 momcUseLimit;
|
||||
|
||||
NvU32 granularity;
|
||||
NvU32 threshold;
|
||||
} UvmGpuAccessCntrConfig;
|
||||
|
||||
@@ -1036,24 +1070,18 @@ typedef UvmGpuAccessCntrConfig gpuAccessCntrConfig;
|
||||
typedef UvmGpuFaultInfo gpuFaultInfo;
|
||||
typedef UvmGpuMemoryInfo gpuMemoryInfo;
|
||||
typedef UvmGpuExternalMappingInfo gpuExternalMappingInfo;
|
||||
typedef UvmGpuExternalPhysAddrInfo gpuExternalPhysAddrInfo;
|
||||
typedef UvmGpuChannelResourceInfo gpuChannelResourceInfo;
|
||||
typedef UvmGpuChannelInstanceInfo gpuChannelInstanceInfo;
|
||||
typedef UvmGpuChannelResourceBindParams gpuChannelResourceBindParams;
|
||||
typedef UvmGpuFbInfo gpuFbInfo;
|
||||
typedef UvmGpuEccInfo gpuEccInfo;
|
||||
typedef UvmGpuNvlinkInfo gpuNvlinkInfo;
|
||||
typedef UvmGpuPagingChannel *gpuPagingChannelHandle;
|
||||
typedef UvmGpuPagingChannelInfo gpuPagingChannelInfo;
|
||||
typedef UvmGpuPagingChannelAllocParams gpuPagingChannelAllocParams;
|
||||
typedef UvmPmaAllocationOptions gpuPmaAllocationOptions;
|
||||
|
||||
// This struct shall not be accessed nor modified directly by UVM as it is
|
||||
// entirely managed by the RM layer
|
||||
typedef struct UvmCslContext_tag
|
||||
{
|
||||
struct ccslContext_t *ctx;
|
||||
void *nvidia_stack;
|
||||
} UvmCslContext;
|
||||
|
||||
typedef struct UvmCslIv
|
||||
{
|
||||
NvU8 iv[12];
|
||||
@@ -1066,4 +1094,21 @@ typedef enum UvmCslOperation
|
||||
UVM_CSL_OPERATION_DECRYPT
|
||||
} UvmCslOperation;
|
||||
|
||||
typedef enum UVM_KEY_ROTATION_STATUS {
|
||||
// Key rotation complete/not in progress
|
||||
UVM_KEY_ROTATION_STATUS_IDLE = 0,
|
||||
// RM is waiting for clients to report their channels are idle for key rotation
|
||||
UVM_KEY_ROTATION_STATUS_PENDING = 1,
|
||||
// Key rotation is in progress
|
||||
UVM_KEY_ROTATION_STATUS_IN_PROGRESS = 2,
|
||||
// Key rotation timeout failure, RM will RC non-idle channels.
|
||||
// UVM should never see this status value.
|
||||
UVM_KEY_ROTATION_STATUS_FAILED_TIMEOUT = 3,
|
||||
// Key rotation failed because upper threshold was crossed, RM will RC non-idle channels
|
||||
UVM_KEY_ROTATION_STATUS_FAILED_THRESHOLD = 4,
|
||||
// Internal RM failure while rotating keys for a certain channel, RM will RC the channel.
|
||||
UVM_KEY_ROTATION_STATUS_FAILED_ROTATION = 5,
|
||||
UVM_KEY_ROTATION_STATUS_MAX_COUNT = 6,
|
||||
} UVM_KEY_ROTATION_STATUS;
|
||||
|
||||
#endif // _NV_UVM_TYPES_H_
|
||||
166
kernel-open/common/inc/nv_uvm_user_types.h
Normal file
166
kernel-open/common/inc/nv_uvm_user_types.h
Normal file
@@ -0,0 +1,166 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
//
|
||||
// This file provides common types for the UVM kernel driver, UVM user layer,
|
||||
// and RM's UVM interface.
|
||||
//
|
||||
|
||||
#ifndef _NV_UVM_USER_TYPES_H_
|
||||
#define _NV_UVM_USER_TYPES_H_
|
||||
|
||||
#include "nvtypes.h"
|
||||
|
||||
//
|
||||
// Default Page Size if left "0" because in RM BIG page size is default & there
|
||||
// are multiple BIG page sizes in RM. These defines are used as flags to "0"
|
||||
// should be OK when user is not sure which pagesize allocation it wants
|
||||
//
|
||||
#define UVM_PAGE_SIZE_DEFAULT 0x0ULL
|
||||
#define UVM_PAGE_SIZE_4K 0x1000ULL
|
||||
#define UVM_PAGE_SIZE_64K 0x10000ULL
|
||||
#define UVM_PAGE_SIZE_128K 0x20000ULL
|
||||
#define UVM_PAGE_SIZE_2M 0x200000ULL
|
||||
#define UVM_PAGE_SIZE_512M 0x20000000ULL
|
||||
#define UVM_PAGE_SIZE_256G 0x4000000000ULL
|
||||
|
||||
typedef enum
|
||||
{
|
||||
UVM_VIRT_MODE_NONE = 0, // Baremetal or passthrough virtualization
|
||||
UVM_VIRT_MODE_LEGACY = 1, // Virtualization without SRIOV support
|
||||
UVM_VIRT_MODE_SRIOV_HEAVY = 2, // Virtualization with SRIOV Heavy configured
|
||||
UVM_VIRT_MODE_SRIOV_STANDARD = 3, // Virtualization with SRIOV Standard configured
|
||||
UVM_VIRT_MODE_COUNT = 4,
|
||||
} UVM_VIRT_MODE;
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// UVM GPU mapping types
|
||||
//
|
||||
// These types indicate the kinds of accesses allowed from a given GPU at the
|
||||
// specified virtual address range. There are 3 basic kinds of accesses: read,
|
||||
// write and atomics. Each type indicates what kinds of accesses are allowed.
|
||||
// Accesses of any disallowed kind are fatal. The "Default" type specifies that
|
||||
// the UVM driver should decide on the types of accesses allowed.
|
||||
//------------------------------------------------------------------------------
|
||||
typedef enum
|
||||
{
|
||||
UvmGpuMappingTypeDefault = 0,
|
||||
UvmGpuMappingTypeReadWriteAtomic = 1,
|
||||
UvmGpuMappingTypeReadWrite = 2,
|
||||
UvmGpuMappingTypeReadOnly = 3,
|
||||
UvmGpuMappingTypeCount = 4
|
||||
} UvmGpuMappingType;
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// UVM GPU caching types
|
||||
//
|
||||
// These types indicate the cacheability of the specified virtual address range
|
||||
// from a given GPU. The "Default" type specifies that the UVM driver should
|
||||
// set caching on or off as required to follow the UVM coherence model. The
|
||||
// "ForceUncached" and "ForceCached" types will always turn caching off or on
|
||||
// respectively. These two types override the cacheability specified by the UVM
|
||||
// coherence model.
|
||||
//------------------------------------------------------------------------------
|
||||
typedef enum
|
||||
{
|
||||
UvmGpuCachingTypeDefault = 0,
|
||||
UvmGpuCachingTypeForceUncached = 1,
|
||||
UvmGpuCachingTypeForceCached = 2,
|
||||
UvmGpuCachingTypeCount = 3
|
||||
} UvmGpuCachingType;
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// UVM GPU format types
|
||||
//
|
||||
// These types indicate the memory format of the specified virtual address
|
||||
// range for a given GPU. The "Default" type specifies that the UVM driver will
|
||||
// detect the format based on the allocation and is mutually inclusive with
|
||||
// UvmGpuFormatElementBitsDefault.
|
||||
//------------------------------------------------------------------------------
|
||||
typedef enum {
|
||||
UvmGpuFormatTypeDefault = 0,
|
||||
UvmGpuFormatTypeBlockLinear = 1,
|
||||
UvmGpuFormatTypeCount = 2
|
||||
} UvmGpuFormatType;
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// UVM GPU Element bits types
|
||||
//
|
||||
// These types indicate the element size of the specified virtual address range
|
||||
// for a given GPU. The "Default" type specifies that the UVM driver will
|
||||
// detect the element size based on the allocation and is mutually inclusive
|
||||
// with UvmGpuFormatTypeDefault. The element size is specified in bits:
|
||||
// UvmGpuFormatElementBits8 uses the 8-bits format.
|
||||
//------------------------------------------------------------------------------
|
||||
typedef enum {
|
||||
UvmGpuFormatElementBitsDefault = 0,
|
||||
UvmGpuFormatElementBits8 = 1,
|
||||
UvmGpuFormatElementBits16 = 2,
|
||||
// Cuda does not support 24-bit width
|
||||
UvmGpuFormatElementBits32 = 4,
|
||||
UvmGpuFormatElementBits64 = 5,
|
||||
UvmGpuFormatElementBits128 = 6,
|
||||
UvmGpuFormatElementBitsCount = 7
|
||||
} UvmGpuFormatElementBits;
|
||||
|
||||
//------------------------------------------------------------------------------
|
||||
// UVM GPU Compression types
|
||||
//
|
||||
// These types indicate the compression type of the specified virtual address
|
||||
// range for a given GPU. The "Default" type specifies that the UVM driver will
|
||||
// detect the compression attributes based on the allocation. Any type other
|
||||
// than the default will override the compression behavior of the physical
|
||||
// allocation. UvmGpuCompressionTypeEnabledNoPlc will disable PLC but enables
|
||||
// generic compression. UvmGpuCompressionTypeEnabledNoPlc type is only supported
|
||||
// on Turing plus GPUs. Since UvmGpuCompressionTypeEnabledNoPlc type enables
|
||||
// generic compression, it can only be used when the compression attribute of
|
||||
// the underlying physical allocation is enabled.
|
||||
//------------------------------------------------------------------------------
|
||||
typedef enum {
|
||||
UvmGpuCompressionTypeDefault = 0,
|
||||
UvmGpuCompressionTypeEnabledNoPlc = 1,
|
||||
UvmGpuCompressionTypeCount = 2
|
||||
} UvmGpuCompressionType;
|
||||
|
||||
//
|
||||
// Mirrored in PMA (PMA_STATS)
|
||||
//
|
||||
typedef struct UvmPmaStatistics_tag
|
||||
{
|
||||
volatile NvU64 numPages2m; // PMA-wide 2MB pages count across all regions
|
||||
volatile NvU64 numFreePages64k; // PMA-wide free 64KB page count across all regions
|
||||
volatile NvU64 numFreePages2m; // PMA-wide free 2MB pages count across all regions
|
||||
volatile NvU64 numPages2mProtected; // PMA-wide 2MB pages count in protected memory
|
||||
volatile NvU64 numFreePages64kProtected; // PMA-wide free 64KB page count in protected memory
|
||||
volatile NvU64 numFreePages2mProtected; // PMA-wide free 2MB pages count in protected memory
|
||||
} UvmPmaStatistics;
|
||||
|
||||
typedef enum
|
||||
{
|
||||
UVM_ACCESS_COUNTER_GRANULARITY_64K = 1,
|
||||
UVM_ACCESS_COUNTER_GRANULARITY_2M = 2,
|
||||
UVM_ACCESS_COUNTER_GRANULARITY_16M = 3,
|
||||
UVM_ACCESS_COUNTER_GRANULARITY_16G = 4,
|
||||
} UVM_ACCESS_COUNTER_GRANULARITY;
|
||||
|
||||
#endif // _NV_UVM_USER_TYPES_H_
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2021 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -69,10 +69,6 @@ typedef struct DRAM_CLK_INSTANCE {
|
||||
// This table is used to collect information from other modules that is needed
|
||||
// for RM IMP calculations. (Used on Tegra only.)
|
||||
//
|
||||
#define TEGRA_IMP_IMPORT_DATA_DRAM_TYPE_UNKNOWN 0U
|
||||
#define TEGRA_IMP_IMPORT_DATA_DRAM_TYPE_LPDDR4 1U
|
||||
#define TEGRA_IMP_IMPORT_DATA_DRAM_TYPE_LPDDR5 2U
|
||||
|
||||
typedef struct TEGRA_IMP_IMPORT_DATA {
|
||||
//
|
||||
// max_iso_bw_kbps stores the maximum possible ISO bandwidth available to
|
||||
@@ -82,7 +78,6 @@ typedef struct TEGRA_IMP_IMPORT_DATA {
|
||||
//
|
||||
NvU32 max_iso_bw_kbps;
|
||||
|
||||
NvU32 dram_type;
|
||||
// On Orin, each dram channel is 16 bits wide.
|
||||
NvU32 num_dram_channels;
|
||||
|
||||
@@ -47,6 +47,11 @@
|
||||
|
||||
#define NVKMS_MAX_SUPERFRAME_VIEWS 4
|
||||
|
||||
#define NVKMS_LOG2_LUT_ARRAY_SIZE 10
|
||||
#define NVKMS_LUT_ARRAY_SIZE (1 << NVKMS_LOG2_LUT_ARRAY_SIZE)
|
||||
|
||||
#define NVKMS_OLUT_FP_NORM_SCALE_DEFAULT 0xffffffff
|
||||
|
||||
typedef NvU32 NvKmsDeviceHandle;
|
||||
typedef NvU32 NvKmsDispHandle;
|
||||
typedef NvU32 NvKmsConnectorHandle;
|
||||
@@ -55,6 +60,7 @@ typedef NvU32 NvKmsFrameLockHandle;
|
||||
typedef NvU32 NvKmsDeferredRequestFifoHandle;
|
||||
typedef NvU32 NvKmsSwapGroupHandle;
|
||||
typedef NvU32 NvKmsVblankSyncObjectHandle;
|
||||
typedef NvU32 NvKmsVblankSemControlHandle;
|
||||
|
||||
struct NvKmsSize {
|
||||
NvU16 width;
|
||||
@@ -181,6 +187,14 @@ enum NvKmsEventType {
|
||||
NVKMS_EVENT_TYPE_FLIP_OCCURRED,
|
||||
};
|
||||
|
||||
enum NvKmsFlipResult {
|
||||
NV_KMS_FLIP_RESULT_SUCCESS = 0, /* Success */
|
||||
NV_KMS_FLIP_RESULT_INVALID_PARAMS, /* Parameter validation failed */
|
||||
NV_KMS_FLIP_RESULT_IN_PROGRESS, /* Flip would fail because an outstanding
|
||||
flip containing changes that cannot be
|
||||
queued is in progress */
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
NV_EVO_SCALER_1TAP = 0,
|
||||
NV_EVO_SCALER_2TAPS = 1,
|
||||
@@ -223,6 +237,90 @@ struct NvKmsUsageBounds {
|
||||
} layer[NVKMS_MAX_LAYERS_PER_HEAD];
|
||||
};
|
||||
|
||||
/*!
|
||||
* Per-component arrays of NvU16s describing the LUT; used for both the input
|
||||
* LUT and output LUT.
|
||||
*/
|
||||
struct NvKmsLutRamps {
|
||||
NvU16 red[NVKMS_LUT_ARRAY_SIZE]; /*! in */
|
||||
NvU16 green[NVKMS_LUT_ARRAY_SIZE]; /*! in */
|
||||
NvU16 blue[NVKMS_LUT_ARRAY_SIZE]; /*! in */
|
||||
};
|
||||
|
||||
/* Datatypes for LUT capabilities */
|
||||
enum NvKmsLUTFormat {
|
||||
/*
|
||||
* Normalized fixed-point format mapping [0, 1] to [0x0, 0xFFFF].
|
||||
*/
|
||||
NVKMS_LUT_FORMAT_UNORM16,
|
||||
|
||||
/*
|
||||
* Half-precision floating point.
|
||||
*/
|
||||
NVKMS_LUT_FORMAT_FP16,
|
||||
|
||||
/*
|
||||
* 14-bit fixed-point format required to work around hardware bug 813188.
|
||||
*
|
||||
* To convert from UNORM16 to UNORM14_WAR_813188:
|
||||
* unorm14_war_813188 = ((unorm16 >> 2) & ~7) + 0x6000
|
||||
*/
|
||||
NVKMS_LUT_FORMAT_UNORM14_WAR_813188
|
||||
};
|
||||
|
||||
enum NvKmsLUTVssSupport {
|
||||
NVKMS_LUT_VSS_NOT_SUPPORTED,
|
||||
NVKMS_LUT_VSS_SUPPORTED,
|
||||
NVKMS_LUT_VSS_REQUIRED,
|
||||
};
|
||||
|
||||
enum NvKmsLUTVssType {
|
||||
NVKMS_LUT_VSS_TYPE_NONE,
|
||||
NVKMS_LUT_VSS_TYPE_LINEAR,
|
||||
NVKMS_LUT_VSS_TYPE_LOGARITHMIC,
|
||||
};
|
||||
|
||||
struct NvKmsLUTCaps {
|
||||
/*! Whether this layer or head on this device supports this LUT stage. */
|
||||
NvBool supported;
|
||||
|
||||
/*! Whether this LUT supports VSS. */
|
||||
enum NvKmsLUTVssSupport vssSupport;
|
||||
|
||||
/*!
|
||||
* The type of VSS segmenting this LUT uses.
|
||||
*/
|
||||
enum NvKmsLUTVssType vssType;
|
||||
|
||||
/*!
|
||||
* Expected number of VSS segments.
|
||||
*/
|
||||
NvU32 vssSegments;
|
||||
|
||||
/*!
|
||||
* Expected number of LUT entries.
|
||||
*/
|
||||
NvU32 lutEntries;
|
||||
|
||||
/*!
|
||||
* Format for each of the LUT entries.
|
||||
*/
|
||||
enum NvKmsLUTFormat entryFormat;
|
||||
};
|
||||
|
||||
/* each LUT entry uses this many bytes */
|
||||
#define NVKMS_LUT_CAPS_LUT_ENTRY_SIZE (4 * sizeof(NvU16))
|
||||
|
||||
/* if the LUT surface uses VSS, size of the VSS header */
|
||||
#define NVKMS_LUT_VSS_HEADER_SIZE (4 * NVKMS_LUT_CAPS_LUT_ENTRY_SIZE)
|
||||
|
||||
struct NvKmsLUTSurfaceParams {
|
||||
NvKmsSurfaceHandle surfaceHandle;
|
||||
NvU64 offset NV_ALIGN_BYTES(8);
|
||||
NvU32 vssSegments;
|
||||
NvU32 lutEntries;
|
||||
};
|
||||
|
||||
/*
|
||||
* A 3x4 row-major colorspace conversion matrix.
|
||||
*
|
||||
@@ -418,9 +516,9 @@ struct NvKmsLayerCapabilities {
|
||||
NvBool supportsWindowMode :1;
|
||||
|
||||
/*!
|
||||
* Whether layer supports HDR pipe.
|
||||
* Whether layer supports ICtCp pipe.
|
||||
*/
|
||||
NvBool supportsHDR :1;
|
||||
NvBool supportsICtCp :1;
|
||||
|
||||
|
||||
/*!
|
||||
@@ -441,6 +539,10 @@ struct NvKmsLayerCapabilities {
|
||||
* still expected to honor the NvKmsUsageBounds for each head.
|
||||
*/
|
||||
NvU64 supportedSurfaceMemoryFormats NV_ALIGN_BYTES(8);
|
||||
|
||||
/* Capabilities for each LUT stage in the EVO3 precomp pipeline. */
|
||||
struct NvKmsLUTCaps ilut;
|
||||
struct NvKmsLUTCaps tmo;
|
||||
};
|
||||
|
||||
/*!
|
||||
@@ -538,22 +640,34 @@ enum NvKmsInputColorRange {
|
||||
* If DEFAULT is provided, driver will assume full range for RGB formats
|
||||
* and limited range for YUV formats.
|
||||
*/
|
||||
NVKMS_INPUT_COLORRANGE_DEFAULT = 0,
|
||||
NVKMS_INPUT_COLOR_RANGE_DEFAULT = 0,
|
||||
|
||||
NVKMS_INPUT_COLORRANGE_LIMITED = 1,
|
||||
NVKMS_INPUT_COLOR_RANGE_LIMITED = 1,
|
||||
|
||||
NVKMS_INPUT_COLORRANGE_FULL = 2,
|
||||
NVKMS_INPUT_COLOR_RANGE_FULL = 2,
|
||||
};
|
||||
|
||||
enum NvKmsInputColorSpace {
|
||||
/* Unknown colorspace; no de-gamma will be applied */
|
||||
NVKMS_INPUT_COLORSPACE_NONE = 0,
|
||||
/* Unknown colorspace */
|
||||
NVKMS_INPUT_COLOR_SPACE_NONE = 0,
|
||||
|
||||
/* Linear, Rec.709 [-0.5, 7.5) */
|
||||
NVKMS_INPUT_COLORSPACE_SCRGB_LINEAR = 1,
|
||||
NVKMS_INPUT_COLOR_SPACE_BT601 = 1,
|
||||
NVKMS_INPUT_COLOR_SPACE_BT709 = 2,
|
||||
NVKMS_INPUT_COLOR_SPACE_BT2020 = 3,
|
||||
NVKMS_INPUT_COLOR_SPACE_BT2100 = NVKMS_INPUT_COLOR_SPACE_BT2020,
|
||||
|
||||
/* PQ, Rec.2020 unity */
|
||||
NVKMS_INPUT_COLORSPACE_BT2100_PQ = 2,
|
||||
NVKMS_INPUT_COLOR_SPACE_SCRGB = 4
|
||||
};
|
||||
|
||||
enum NvKmsInputTf {
|
||||
NVKMS_INPUT_TF_LINEAR = 0,
|
||||
NVKMS_INPUT_TF_PQ = 1
|
||||
};
|
||||
|
||||
enum NvKmsOutputColorimetry {
|
||||
NVKMS_OUTPUT_COLORIMETRY_DEFAULT = 0,
|
||||
|
||||
NVKMS_OUTPUT_COLORIMETRY_BT2100 = 1,
|
||||
};
|
||||
|
||||
enum NvKmsOutputTf {
|
||||
@@ -566,6 +680,17 @@ enum NvKmsOutputTf {
|
||||
NVKMS_OUTPUT_TF_PQ = 2,
|
||||
};
|
||||
|
||||
/*!
|
||||
* EOTF Data Byte 1 as per CTA-861-G spec.
|
||||
* This is expected to match exactly with the spec.
|
||||
*/
|
||||
enum NvKmsInfoFrameEOTF {
|
||||
NVKMS_INFOFRAME_EOTF_SDR_GAMMA = 0,
|
||||
NVKMS_INFOFRAME_EOTF_HDR_GAMMA = 1,
|
||||
NVKMS_INFOFRAME_EOTF_ST2084 = 2,
|
||||
NVKMS_INFOFRAME_EOTF_HLG = 3,
|
||||
};
|
||||
|
||||
/*!
|
||||
* HDR Static Metadata Type1 Descriptor as per CEA-861.3 spec.
|
||||
* This is expected to match exactly with the spec.
|
||||
@@ -644,4 +769,20 @@ struct NvKmsSuperframeInfo {
|
||||
} view[NVKMS_MAX_SUPERFRAME_VIEWS];
|
||||
};
|
||||
|
||||
/* Fields within NvKmsVblankSemControlDataOneHead::flags */
|
||||
#define NVKMS_VBLANK_SEM_CONTROL_SWAP_INTERVAL 15:0
|
||||
|
||||
struct NvKmsVblankSemControlDataOneHead {
|
||||
NvU32 requestCounterAccel;
|
||||
NvU32 requestCounter;
|
||||
NvU32 flags;
|
||||
|
||||
NvU32 semaphore;
|
||||
NvU64 vblankCount NV_ALIGN_BYTES(8);
|
||||
};
|
||||
|
||||
struct NvKmsVblankSemControlData {
|
||||
struct NvKmsVblankSemControlDataOneHead head[NV_MAX_HEADS];
|
||||
};
|
||||
|
||||
#endif /* NVKMS_API_TYPES_H */
|
||||
@@ -24,8 +24,10 @@
|
||||
#if !defined(__NVKMS_KAPI_H__)
|
||||
|
||||
#include "nvtypes.h"
|
||||
#include "nv_mig_types.h"
|
||||
|
||||
#include "nv-gpu-info.h"
|
||||
#include "nv_dpy_id.h"
|
||||
#include "nvkms-api-types.h"
|
||||
#include "nvkms-format.h"
|
||||
|
||||
@@ -124,6 +126,14 @@ struct NvKmsKapiDisplayMode {
|
||||
#define NVKMS_KAPI_LAYER_INVALID_IDX 0xff
|
||||
#define NVKMS_KAPI_LAYER_PRIMARY_IDX 0
|
||||
|
||||
struct NvKmsKapiLutCaps {
|
||||
struct {
|
||||
struct NvKmsLUTCaps ilut;
|
||||
struct NvKmsLUTCaps tmo;
|
||||
} layer[NVKMS_KAPI_LAYER_MAX];
|
||||
struct NvKmsLUTCaps olut;
|
||||
};
|
||||
|
||||
struct NvKmsKapiDeviceResourcesInfo {
|
||||
|
||||
NvU32 numHeads;
|
||||
@@ -158,13 +168,25 @@ struct NvKmsKapiDeviceResourcesInfo {
|
||||
|
||||
NvU32 hasVideoMemory;
|
||||
|
||||
NvU32 numDisplaySemaphores;
|
||||
|
||||
NvU8 genericPageKind;
|
||||
|
||||
NvBool supportsSyncpts;
|
||||
|
||||
NvBool requiresVrrSemaphores;
|
||||
|
||||
NvBool supportsInputColorRange;
|
||||
NvBool supportsInputColorSpace;
|
||||
} caps;
|
||||
|
||||
NvU64 supportedSurfaceMemoryFormats[NVKMS_KAPI_LAYER_MAX];
|
||||
NvBool supportsHDR[NVKMS_KAPI_LAYER_MAX];
|
||||
NvBool supportsICtCp[NVKMS_KAPI_LAYER_MAX];
|
||||
|
||||
struct NvKmsKapiLutCaps lutCaps;
|
||||
|
||||
NvU64 vtFbBaseAddress;
|
||||
NvU64 vtFbSize;
|
||||
};
|
||||
|
||||
#define NVKMS_KAPI_LAYER_MASK(layerType) (1 << (layerType))
|
||||
@@ -190,6 +212,7 @@ struct NvKmsKapiConnectorInfo {
|
||||
NvU32 numIncompatibleConnectors;
|
||||
NvKmsKapiConnector incompatibleConnectorHandles[NVKMS_KAPI_MAX_CONNECTORS];
|
||||
|
||||
NVDpyIdList dynamicDpyIdList;
|
||||
};
|
||||
|
||||
struct NvKmsKapiStaticDisplayInfo {
|
||||
@@ -208,20 +231,30 @@ struct NvKmsKapiStaticDisplayInfo {
|
||||
NvKmsKapiDisplay possibleCloneHandles[NVKMS_KAPI_MAX_CLONE_DISPLAYS];
|
||||
|
||||
NvU32 headMask;
|
||||
|
||||
NvBool isDpMST;
|
||||
};
|
||||
|
||||
struct NvKmsKapiSyncpt {
|
||||
struct NvKmsKapiSyncParams {
|
||||
union {
|
||||
struct {
|
||||
/*!
|
||||
* Possible syncpt use case in kapi.
|
||||
* For pre-syncpt, use only id and value
|
||||
* and for post-syncpt, use only fd.
|
||||
*/
|
||||
NvU32 preSyncptId;
|
||||
NvU32 preSyncptValue;
|
||||
} syncpt;
|
||||
|
||||
/*!
|
||||
* Possible syncpt use case in kapi.
|
||||
* For pre-syncpt, use only id and value
|
||||
* and for post-syncpt, use only fd.
|
||||
*/
|
||||
NvBool preSyncptSpecified;
|
||||
NvU32 preSyncptId;
|
||||
NvU32 preSyncptValue;
|
||||
struct {
|
||||
NvU32 index;
|
||||
} semaphore;
|
||||
} u;
|
||||
|
||||
NvBool postSyncptRequested;
|
||||
NvBool preSyncptSpecified;
|
||||
NvBool postSyncptRequested;
|
||||
NvBool semaphoreSpecified;
|
||||
};
|
||||
|
||||
struct NvKmsKapiLayerConfig {
|
||||
@@ -231,12 +264,15 @@ struct NvKmsKapiLayerConfig {
|
||||
NvU8 surfaceAlpha;
|
||||
} compParams;
|
||||
struct NvKmsRRParams rrParams;
|
||||
struct NvKmsKapiSyncpt syncptParams;
|
||||
struct NvKmsKapiSyncParams syncParams;
|
||||
|
||||
struct NvKmsHDRStaticMetadata hdrMetadata;
|
||||
NvBool hdrMetadataSpecified;
|
||||
struct {
|
||||
struct NvKmsHDRStaticMetadata val;
|
||||
NvBool enabled;
|
||||
} hdrMetadata;
|
||||
|
||||
enum NvKmsOutputTf tf;
|
||||
enum NvKmsInputTf inputTf;
|
||||
enum NvKmsOutputTf outputTf;
|
||||
|
||||
NvU8 minPresentInterval;
|
||||
NvBool tearing;
|
||||
@@ -248,16 +284,58 @@ struct NvKmsKapiLayerConfig {
|
||||
NvU16 dstWidth, dstHeight;
|
||||
|
||||
enum NvKmsInputColorSpace inputColorSpace;
|
||||
enum NvKmsInputColorRange inputColorRange;
|
||||
|
||||
struct {
|
||||
NvBool enabled;
|
||||
struct NvKmsKapiSurface *lutSurface;
|
||||
NvU64 offset;
|
||||
NvU32 vssSegments;
|
||||
NvU32 lutEntries;
|
||||
} ilut;
|
||||
|
||||
struct {
|
||||
NvBool enabled;
|
||||
struct NvKmsKapiSurface *lutSurface;
|
||||
NvU64 offset;
|
||||
NvU32 vssSegments;
|
||||
NvU32 lutEntries;
|
||||
} tmo;
|
||||
|
||||
struct NvKmsCscMatrix csc;
|
||||
NvBool cscUseMain;
|
||||
|
||||
struct {
|
||||
struct NvKmsCscMatrix lmsCtm;
|
||||
struct NvKmsCscMatrix lmsToItpCtm;
|
||||
struct NvKmsCscMatrix itpToLmsCtm;
|
||||
struct NvKmsCscMatrix blendCtm;
|
||||
struct {
|
||||
NvBool lmsCtm : 1;
|
||||
NvBool lmsToItpCtm : 1;
|
||||
NvBool itpToLmsCtm : 1;
|
||||
NvBool blendCtm : 1;
|
||||
} enabled;
|
||||
} matrixOverrides;
|
||||
};
|
||||
|
||||
struct NvKmsKapiLayerRequestedConfig {
|
||||
struct NvKmsKapiLayerConfig config;
|
||||
struct {
|
||||
NvBool surfaceChanged : 1;
|
||||
NvBool srcXYChanged : 1;
|
||||
NvBool srcWHChanged : 1;
|
||||
NvBool dstXYChanged : 1;
|
||||
NvBool dstWHChanged : 1;
|
||||
NvBool surfaceChanged : 1;
|
||||
NvBool srcXYChanged : 1;
|
||||
NvBool srcWHChanged : 1;
|
||||
NvBool dstXYChanged : 1;
|
||||
NvBool dstWHChanged : 1;
|
||||
NvBool cscChanged : 1;
|
||||
NvBool inputTfChanged : 1;
|
||||
NvBool outputTfChanged : 1;
|
||||
NvBool inputColorSpaceChanged : 1;
|
||||
NvBool inputColorRangeChanged : 1;
|
||||
NvBool hdrMetadataChanged : 1;
|
||||
NvBool matrixOverridesChanged : 1;
|
||||
NvBool ilutChanged : 1;
|
||||
NvBool tmoChanged : 1;
|
||||
} flags;
|
||||
};
|
||||
|
||||
@@ -301,14 +379,52 @@ struct NvKmsKapiHeadModeSetConfig {
|
||||
struct NvKmsKapiDisplayMode mode;
|
||||
|
||||
NvBool vrrEnabled;
|
||||
|
||||
struct {
|
||||
NvBool enabled;
|
||||
enum NvKmsInfoFrameEOTF eotf;
|
||||
struct NvKmsHDRStaticMetadata staticMetadata;
|
||||
} hdrInfoFrame;
|
||||
|
||||
enum NvKmsOutputColorimetry colorimetry;
|
||||
|
||||
struct {
|
||||
struct {
|
||||
NvU32 depth;
|
||||
NvU32 start;
|
||||
NvU32 end;
|
||||
struct NvKmsLutRamps *pRamps;
|
||||
} input;
|
||||
|
||||
struct {
|
||||
NvBool enabled;
|
||||
struct NvKmsLutRamps *pRamps;
|
||||
} output;
|
||||
} lut;
|
||||
|
||||
struct {
|
||||
NvBool enabled;
|
||||
struct NvKmsKapiSurface *lutSurface;
|
||||
NvU64 offset;
|
||||
NvU32 vssSegments;
|
||||
NvU32 lutEntries;
|
||||
} olut;
|
||||
|
||||
NvU32 olutFpNormScale;
|
||||
};
|
||||
|
||||
struct NvKmsKapiHeadRequestedConfig {
|
||||
struct NvKmsKapiHeadModeSetConfig modeSetConfig;
|
||||
struct {
|
||||
NvBool activeChanged : 1;
|
||||
NvBool displaysChanged : 1;
|
||||
NvBool modeChanged : 1;
|
||||
NvBool activeChanged : 1;
|
||||
NvBool displaysChanged : 1;
|
||||
NvBool modeChanged : 1;
|
||||
NvBool hdrInfoFrameChanged : 1;
|
||||
NvBool colorimetryChanged : 1;
|
||||
NvBool legacyIlutChanged : 1;
|
||||
NvBool legacyOlutChanged : 1;
|
||||
NvBool olutChanged : 1;
|
||||
NvBool olutFpNormScaleChanged : 1;
|
||||
} flags;
|
||||
|
||||
struct NvKmsKapiCursorRequestedConfig cursorRequestedConfig;
|
||||
@@ -333,6 +449,9 @@ struct NvKmsKapiHeadReplyConfig {
|
||||
};
|
||||
|
||||
struct NvKmsKapiModeSetReplyConfig {
|
||||
enum NvKmsFlipResult flipResult;
|
||||
NvBool vrrFlip;
|
||||
NvS32 vrrSemaphoreIndex;
|
||||
struct NvKmsKapiHeadReplyConfig
|
||||
headReplyConfig[NVKMS_KAPI_MAX_HEADS];
|
||||
};
|
||||
@@ -378,6 +497,8 @@ struct NvKmsKapiEvent {
|
||||
struct NvKmsKapiAllocateDeviceParams {
|
||||
/* [IN] GPU ID obtained from enumerateGpus() */
|
||||
NvU32 gpuId;
|
||||
/* [IN] MIG device if requested */
|
||||
MIGDeviceId migDevice;
|
||||
|
||||
/* [IN] Private data of device allocator */
|
||||
void *privateData;
|
||||
@@ -449,12 +570,45 @@ enum NvKmsKapiAllocationType {
|
||||
NVKMS_KAPI_ALLOCATION_TYPE_OFFSCREEN = 2,
|
||||
};
|
||||
|
||||
struct NvKmsKapiAllocateMemoryParams {
|
||||
/* [IN] BlockLinear or Pitch */
|
||||
enum NvKmsSurfaceMemoryLayout layout;
|
||||
|
||||
/* [IN] Allocation type */
|
||||
enum NvKmsKapiAllocationType type;
|
||||
|
||||
/* [IN] Size, in bytes, of the memory to allocate */
|
||||
NvU64 size;
|
||||
|
||||
/* [IN] Whether memory can be updated directly on the screen */
|
||||
NvBool noDisplayCaching;
|
||||
|
||||
/* [IN] Whether to allocate memory from video memory or system memory */
|
||||
NvBool useVideoMemory;
|
||||
|
||||
/* [IN/OUT] For input, non-zero if compression backing store should be
|
||||
* allocated for the memory, for output, non-zero if compression backing
|
||||
* store was allocated for the memory */
|
||||
NvU8 *compressible;
|
||||
};
|
||||
|
||||
typedef enum NvKmsKapiRegisterWaiterResultRec {
|
||||
NVKMS_KAPI_REG_WAITER_FAILED,
|
||||
NVKMS_KAPI_REG_WAITER_SUCCESS,
|
||||
NVKMS_KAPI_REG_WAITER_ALREADY_SIGNALLED,
|
||||
} NvKmsKapiRegisterWaiterResult;
|
||||
|
||||
struct NvKmsKapiGpuInfo {
|
||||
nv_gpu_info_t gpuInfo;
|
||||
MIGDeviceId migDevice;
|
||||
};
|
||||
|
||||
struct NvKmsKapiCallbacks {
|
||||
void (*suspendResume)(NvBool suspend);
|
||||
void (*remove)(NvU32 gpuId);
|
||||
void (*probe)(const struct NvKmsKapiGpuInfo *gpu_info);
|
||||
};
|
||||
|
||||
struct NvKmsKapiFunctionsTable {
|
||||
|
||||
/*!
|
||||
@@ -471,14 +625,19 @@ struct NvKmsKapiFunctionsTable {
|
||||
} systemInfo;
|
||||
|
||||
/*!
|
||||
* Enumerate the available physical GPUs that can be used with NVKMS.
|
||||
* Enumerate the available GPUs that can be used with NVKMS.
|
||||
*
|
||||
* \param [out] gpuInfo The information of the enumerated GPUs.
|
||||
* It is an array of NVIDIA_MAX_GPUS elements.
|
||||
* The gpuCallback will be called with a NvKmsKapiGpuInfo for each
|
||||
* physical and MIG GPU currently available in the system.
|
||||
*
|
||||
* \param [in] gpuCallback Client function to handle each GPU.
|
||||
*
|
||||
* \return Count of enumerated gpus.
|
||||
*/
|
||||
NvU32 (*enumerateGpus)(nv_gpu_info_t *gpuInfo);
|
||||
NvU32 (*enumerateGpus)
|
||||
(
|
||||
void (*gpuCallback)(const struct NvKmsKapiGpuInfo *info)
|
||||
);
|
||||
|
||||
/*!
|
||||
* Allocate an NVK device using which you can query/allocate resources on
|
||||
@@ -540,8 +699,8 @@ struct NvKmsKapiFunctionsTable {
|
||||
);
|
||||
|
||||
/*!
|
||||
* Revoke permissions previously granted. Only one (dispIndex, head,
|
||||
* display) is currently supported.
|
||||
* Revoke modeset permissions previously granted. Only one (dispIndex,
|
||||
* head, display) is currently supported.
|
||||
*
|
||||
* \param [in] device A device returned by allocateDevice().
|
||||
*
|
||||
@@ -558,6 +717,34 @@ struct NvKmsKapiFunctionsTable {
|
||||
NvKmsKapiDisplay display
|
||||
);
|
||||
|
||||
/*!
|
||||
* Grant modeset sub-owner permissions to fd. This is used by clients to
|
||||
* convert drm 'master' permissions into nvkms sub-owner permission.
|
||||
*
|
||||
* \param [in] fd fd from opening /dev/nvidia-modeset.
|
||||
*
|
||||
* \param [in] device A device returned by allocateDevice().
|
||||
*
|
||||
* \return NV_TRUE on success, NV_FALSE on failure.
|
||||
*/
|
||||
NvBool (*grantSubOwnership)
|
||||
(
|
||||
NvS32 fd,
|
||||
struct NvKmsKapiDevice *device
|
||||
);
|
||||
|
||||
/*!
|
||||
* Revoke sub-owner permissions previously granted.
|
||||
*
|
||||
* \param [in] device A device returned by allocateDevice().
|
||||
*
|
||||
* \return NV_TRUE on success, NV_FALSE on failure.
|
||||
*/
|
||||
NvBool (*revokeSubOwnership)
|
||||
(
|
||||
struct NvKmsKapiDevice *device
|
||||
);
|
||||
|
||||
/*!
|
||||
* Registers for notification, via
|
||||
* NvKmsKapiAllocateDeviceParams::eventCallback, of the events specified
|
||||
@@ -680,66 +867,22 @@ struct NvKmsKapiFunctionsTable {
|
||||
);
|
||||
|
||||
/*!
|
||||
* Allocate some unformatted video memory of the specified size.
|
||||
* Allocate some unformatted video or system memory of the specified size.
|
||||
*
|
||||
* This function allocates video memory on the specified GPU.
|
||||
* It should be suitable for mapping on the CPU as a pitch
|
||||
* linear or block-linear surface.
|
||||
* This function allocates video or system memory on the specified GPU. It
|
||||
* should be suitable for mapping on the CPU as a pitch linear or
|
||||
* block-linear surface.
|
||||
*
|
||||
* \param [in] device A device allocated using allocateDevice().
|
||||
* \param [in] device A device allocated using allocateDevice().
|
||||
*
|
||||
* \param [in] layout BlockLinear or Pitch.
|
||||
*
|
||||
* \param [in] type Allocation type.
|
||||
*
|
||||
* \param [in] size Size, in bytes, of the memory to allocate.
|
||||
*
|
||||
* \param [in/out] compressible For input, non-zero if compression
|
||||
* backing store should be allocated for
|
||||
* the memory, for output, non-zero if
|
||||
* compression backing store was
|
||||
* allocated for the memory.
|
||||
* \param [in/out] params Parameters required for memory allocation.
|
||||
*
|
||||
* \return An valid memory handle on success, NULL on failure.
|
||||
*/
|
||||
struct NvKmsKapiMemory* (*allocateVideoMemory)
|
||||
struct NvKmsKapiMemory* (*allocateMemory)
|
||||
(
|
||||
struct NvKmsKapiDevice *device,
|
||||
enum NvKmsSurfaceMemoryLayout layout,
|
||||
enum NvKmsKapiAllocationType type,
|
||||
NvU64 size,
|
||||
NvU8 *compressible
|
||||
);
|
||||
|
||||
/*!
|
||||
* Allocate some unformatted system memory of the specified size.
|
||||
*
|
||||
* This function allocates system memory . It should be suitable
|
||||
* for mapping on the CPU as a pitch linear or block-linear surface.
|
||||
*
|
||||
* \param [in] device A device allocated using allocateDevice().
|
||||
*
|
||||
* \param [in] layout BlockLinear or Pitch.
|
||||
*
|
||||
* \param [in] type Allocation type.
|
||||
*
|
||||
* \param [in] size Size, in bytes, of the memory to allocate.
|
||||
*
|
||||
* \param [in/out] compressible For input, non-zero if compression
|
||||
* backing store should be allocated for
|
||||
* the memory, for output, non-zero if
|
||||
* compression backing store was
|
||||
* allocated for the memory.
|
||||
*
|
||||
* \return An valid memory handle on success, NULL on failure.
|
||||
*/
|
||||
struct NvKmsKapiMemory* (*allocateSystemMemory)
|
||||
(
|
||||
struct NvKmsKapiDevice *device,
|
||||
enum NvKmsSurfaceMemoryLayout layout,
|
||||
enum NvKmsKapiAllocationType type,
|
||||
NvU64 size,
|
||||
NvU8 *compressible
|
||||
struct NvKmsKapiAllocateMemoryParams *params
|
||||
);
|
||||
|
||||
/*!
|
||||
@@ -878,6 +1021,17 @@ struct NvKmsKapiFunctionsTable {
|
||||
const void *pLinearAddress
|
||||
);
|
||||
|
||||
/*!
|
||||
* Check if memory object allocated is video memory.
|
||||
*
|
||||
* \param [in] memory Memory allocated using allocateMemory()
|
||||
*
|
||||
* \return NV_TRUE if memory is vidmem, NV_FALSE otherwise.
|
||||
*/
|
||||
NvBool (*isVidmem)(
|
||||
const struct NvKmsKapiMemory *memory
|
||||
);
|
||||
|
||||
/*!
|
||||
* Create a formatted surface from an NvKmsKapiMemory object.
|
||||
*
|
||||
@@ -1094,21 +1248,6 @@ struct NvKmsKapiFunctionsTable {
|
||||
NvU64 *pPages
|
||||
);
|
||||
|
||||
/*!
|
||||
* Check if this memory object can be scanned out for display.
|
||||
*
|
||||
* \param [in] device A device allocated using allocateDevice().
|
||||
*
|
||||
* \param [in] memory The memory object to check for display support.
|
||||
*
|
||||
* \return NV_TRUE if this memory can be displayed, NV_FALSE if not.
|
||||
*/
|
||||
NvBool (*isMemoryValidForDisplay)
|
||||
(
|
||||
const struct NvKmsKapiDevice *device,
|
||||
const struct NvKmsKapiMemory *memory
|
||||
);
|
||||
|
||||
/*
|
||||
* Import SGT as a memory handle.
|
||||
*
|
||||
@@ -1336,6 +1475,126 @@ struct NvKmsKapiFunctionsTable {
|
||||
NvU64 index,
|
||||
NvU64 new_value
|
||||
);
|
||||
|
||||
/*!
|
||||
* Set the pointer to the callback function table.
|
||||
*/
|
||||
void
|
||||
(*setCallbacks)
|
||||
(
|
||||
const struct NvKmsKapiCallbacks *callbacks
|
||||
);
|
||||
|
||||
/*!
|
||||
* Immediately initialize the specified display semaphore to the pending state.
|
||||
*
|
||||
* Must be called prior to applying a mode set that utilizes the specified
|
||||
* display semaphore for synchronization.
|
||||
*
|
||||
* \param [in] device The device which will utilize the semaphore.
|
||||
*
|
||||
* \param [in] semaphoreIndex Index of the desired semaphore within the
|
||||
* NVKMS semaphore pool. Must be less than
|
||||
* NvKmsKapiDeviceResourcesInfo::caps::numDisplaySemaphores
|
||||
* for the specified device.
|
||||
*/
|
||||
NvBool
|
||||
(*tryInitDisplaySemaphore)
|
||||
(
|
||||
struct NvKmsKapiDevice *device,
|
||||
NvU32 semaphoreIndex
|
||||
);
|
||||
|
||||
/*!
|
||||
* Immediately set the specified display semaphore to the displayable state.
|
||||
*
|
||||
* Must be called after \ref tryInitDisplaySemaphore to indicate a mode
|
||||
* configuration change that utilizes the specified display semaphore for
|
||||
* synchronization may proceed.
|
||||
*
|
||||
* \param [in] device The device which will utilize the semaphore.
|
||||
*
|
||||
* \param [in] semaphoreIndex Index of the desired semaphore within the
|
||||
* NVKMS semaphore pool. Must be less than
|
||||
* NvKmsKapiDeviceResourcesInfo::caps::numDisplaySemaphores
|
||||
* for the specified device.
|
||||
*/
|
||||
void
|
||||
(*signalDisplaySemaphore)
|
||||
(
|
||||
struct NvKmsKapiDevice *device,
|
||||
NvU32 semaphoreIndex
|
||||
);
|
||||
|
||||
/*!
|
||||
* Immediately cancel use of a display semaphore by resetting its value to
|
||||
* its initial state.
|
||||
*
|
||||
* This can be used by clients to restore a semaphore to a consistent state
|
||||
* when they have prepared it for use by previously calling
|
||||
* \ref tryInitDisplaySemaphore() on it, but are then prevented from
|
||||
* submitting the associated hardware operations to consume it due to the
|
||||
* subsequent failure of some software or hardware operation.
|
||||
*
|
||||
* \param [in] device The device which will utilize the semaphore.
|
||||
*
|
||||
* \param [in] semaphoreIndex Index of the desired semaphore within the
|
||||
* NVKMS semaphore pool. Must be less than
|
||||
* NvKmsKapiDeviceResourcesInfo::caps::numDisplaySemaphores
|
||||
* for the specified device.
|
||||
*/
|
||||
void
|
||||
(*cancelDisplaySemaphore)
|
||||
(
|
||||
struct NvKmsKapiDevice *device,
|
||||
NvU32 semaphoreIndex
|
||||
);
|
||||
|
||||
/*!
|
||||
* Signal the VRR semaphore at the specified index from the CPU.
|
||||
* If device does not support VRR semaphores, this is a no-op.
|
||||
* Returns true if signal is success or no-op, otherwise returns false.
|
||||
*
|
||||
* \param [in] device A device allocated using allocateDevice().
|
||||
*
|
||||
* \param [in] index The VRR semaphore index to be signalled.
|
||||
*/
|
||||
NvBool
|
||||
(*signalVrrSemaphore)
|
||||
(
|
||||
struct NvKmsKapiDevice *device,
|
||||
NvS32 index
|
||||
);
|
||||
|
||||
/*!
|
||||
* Check or wait on a head's LUT notifier.
|
||||
*
|
||||
* \param [in] device A device allocated using allocateDevice().
|
||||
*
|
||||
* \param [in] head The head to check for LUT completion.
|
||||
*
|
||||
* \param [in] waitForCompletion If true, wait for the notifier in NvKms
|
||||
* before returning.
|
||||
*
|
||||
* \param [out] complete Returns whether the notifier has completed.
|
||||
*/
|
||||
NvBool
|
||||
(*checkLutNotifier)
|
||||
(
|
||||
struct NvKmsKapiDevice *device,
|
||||
NvU32 head,
|
||||
NvBool waitForCompletion
|
||||
);
|
||||
|
||||
/*
|
||||
* Notify NVKMS that the system's framebuffer console has been disabled and
|
||||
* the reserved allocation for the old framebuffer console can be unmapped.
|
||||
*/
|
||||
void
|
||||
(*framebufferConsoleDisabled)
|
||||
(
|
||||
struct NvKmsKapiDevice *device
|
||||
);
|
||||
};
|
||||
|
||||
/** @} */
|
||||
@@ -1350,6 +1609,20 @@ NvBool nvKmsKapiGetFunctionsTable
|
||||
struct NvKmsKapiFunctionsTable *funcsTable
|
||||
);
|
||||
|
||||
NvU32 nvKmsKapiF16ToF32(NvU16 a);
|
||||
|
||||
NvU16 nvKmsKapiF32ToF16(NvU32 a);
|
||||
|
||||
NvU32 nvKmsKapiF32Mul(NvU32 a, NvU32 b);
|
||||
|
||||
NvU32 nvKmsKapiF32Div(NvU32 a, NvU32 b);
|
||||
|
||||
NvU32 nvKmsKapiF32Add(NvU32 a, NvU32 b);
|
||||
|
||||
NvU32 nvKmsKapiF32ToUI32RMinMag(NvU32 a, NvBool exact);
|
||||
|
||||
NvU32 nvKmsKapiUI32ToF32(NvU32 a);
|
||||
|
||||
/** @} */
|
||||
|
||||
#endif /* defined(__NVKMS_KAPI_H__) */
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2017 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2017-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -34,19 +34,25 @@
|
||||
/*
|
||||
* This is the maximum number of GPUs supported in a single system.
|
||||
*/
|
||||
#define NV_MAX_DEVICES 32
|
||||
#define NV_MAX_DEVICES 32
|
||||
|
||||
/*
|
||||
* This is the maximum number of subdevices within a single device.
|
||||
*/
|
||||
#define NV_MAX_SUBDEVICES 8
|
||||
#define NV_MAX_SUBDEVICES 8
|
||||
|
||||
/*
|
||||
* This is the maximum length of the process name string.
|
||||
*/
|
||||
#define NV_PROC_NAME_MAX_LENGTH 100U
|
||||
#define NV_PROC_NAME_MAX_LENGTH 100U
|
||||
|
||||
/*
|
||||
* This is the maximum number of heads per GPU.
|
||||
*/
|
||||
#define NV_MAX_HEADS 4
|
||||
#define NV_MAX_HEADS 4
|
||||
|
||||
/*
|
||||
* Maximum length of a MIG device UUID. It is a 36-byte UUID string plus a
|
||||
* 4-byte prefix and NUL terminator: 'M' 'I' 'G' '-' UUID '\0x0'
|
||||
*/
|
||||
#define NV_MIG_DEVICE_UUID_STR_LENGTH 41U
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -33,43 +33,26 @@ extern "C" {
|
||||
|
||||
#include "nvtypes.h"
|
||||
|
||||
#if !defined(NVIDIA_UNDEF_LEGACY_BIT_MACROS)
|
||||
//
|
||||
// Miscellaneous macros useful for bit field manipulations
|
||||
//
|
||||
// STUPID HACK FOR CL 19434692. Will revert when fix CL is delivered bfm -> chips_a.
|
||||
#ifndef BIT
|
||||
#define BIT(b) (1U<<(b))
|
||||
#endif
|
||||
#ifndef BIT32
|
||||
#define BIT32(b) ((NvU32)1U<<(b))
|
||||
#endif
|
||||
#ifndef BIT64
|
||||
#define BIT64(b) ((NvU64)1U<<(b))
|
||||
#endif
|
||||
|
||||
#endif
|
||||
|
||||
//
|
||||
// It is recommended to use the following bit macros to avoid macro name
|
||||
// collisions with other src code bases.
|
||||
//
|
||||
// Miscellaneous macros useful for bit field manipulations.
|
||||
#ifndef NVBIT
|
||||
#define NVBIT(b) (1U<<(b))
|
||||
#define NVBIT(b) (1U<<(b))
|
||||
#endif
|
||||
#ifndef NVBIT_TYPE
|
||||
#define NVBIT_TYPE(b, t) (((t)1U)<<(b))
|
||||
#define NVBIT_TYPE(b, t) (((t)1U)<<(b))
|
||||
#endif
|
||||
#ifndef NVBIT32
|
||||
#define NVBIT32(b) NVBIT_TYPE(b, NvU32)
|
||||
#define NVBIT32(b) NVBIT_TYPE(b, NvU32)
|
||||
#endif
|
||||
#ifndef NVBIT64
|
||||
#define NVBIT64(b) NVBIT_TYPE(b, NvU64)
|
||||
#define NVBIT64(b) NVBIT_TYPE(b, NvU64)
|
||||
#endif
|
||||
|
||||
//Concatenate 2 32bit values to a 64bit value
|
||||
#define NV_CONCAT_32_TO_64(hi, lo) ((((NvU64)hi) << 32) | ((NvU64)lo))
|
||||
|
||||
// Helper macro's for 32 bit bitmasks
|
||||
#define NV_BITMASK32_ELEMENT_SIZE (sizeof(NvU32) << 3)
|
||||
#define NV_BITMASK32_IDX(chId) (((chId) & ~(0x1F)) >> 5)
|
||||
#define NV_BITMASK32_IDX(chId) (((chId) & ~(0x1F)) >> 5)
|
||||
#define NV_BITMASK32_OFFSET(chId) ((chId) & (0x1F))
|
||||
#define NV_BITMASK32_SET(pChannelMask, chId) \
|
||||
(pChannelMask)[NV_BITMASK32_IDX(chId)] |= NVBIT(NV_BITMASK32_OFFSET(chId))
|
||||
@@ -494,6 +477,23 @@ do \
|
||||
//
|
||||
#define NV_TWO_N_MINUS_ONE(n) (((1ULL<<(n/2))<<((n+1)/2))-1)
|
||||
|
||||
//
|
||||
// Create a 64b bitmask with n bits set
|
||||
// This is the same as ((1ULL<<n) - 1), but it doesn't overflow for n=64
|
||||
//
|
||||
// ...
|
||||
// n=-1, 0x0000000000000000
|
||||
// n=0, 0x0000000000000000
|
||||
// n=1, 0x0000000000000001
|
||||
// ...
|
||||
// n=63, 0x7FFFFFFFFFFFFFFF
|
||||
// n=64, 0xFFFFFFFFFFFFFFFF
|
||||
// n=65, 0xFFFFFFFFFFFFFFFF
|
||||
// n=66, 0xFFFFFFFFFFFFFFFF
|
||||
// ...
|
||||
//
|
||||
#define NV_BITMASK64(n) ((n<1) ? 0ULL : (NV_U64_MAX>>((n>64) ? 0 : (64-n))))
|
||||
|
||||
#define DRF_READ_1WORD_BS(d,r,f,v) \
|
||||
((DRF_EXTENT_MW(NV##d##r##f)<8)?DRF_READ_1BYTE_BS(NV##d##r##f,(v)): \
|
||||
((DRF_EXTENT_MW(NV##d##r##f)<16)?DRF_READ_2BYTE_BS(NV##d##r##f,(v)): \
|
||||
@@ -574,6 +574,12 @@ nvMaskPos32(const NvU32 mask, const NvU32 bitIdx)
|
||||
n32 = BIT_IDX_32(LOWESTBIT(n32));\
|
||||
}
|
||||
|
||||
// Destructive operation on n64
|
||||
#define LOWESTBITIDX_64(n64) \
|
||||
{ \
|
||||
n64 = BIT_IDX_64(LOWESTBIT(n64));\
|
||||
}
|
||||
|
||||
// Destructive operation on n32
|
||||
#define HIGHESTBITIDX_32(n32) \
|
||||
{ \
|
||||
@@ -585,6 +591,17 @@ nvMaskPos32(const NvU32 mask, const NvU32 bitIdx)
|
||||
n32 = count; \
|
||||
}
|
||||
|
||||
// Destructive operation on n64
|
||||
#define HIGHESTBITIDX_64(n64) \
|
||||
{ \
|
||||
NvU64 count = 0; \
|
||||
while (n64 >>= 1) \
|
||||
{ \
|
||||
count++; \
|
||||
} \
|
||||
n64 = count; \
|
||||
}
|
||||
|
||||
// Destructive operation on n32
|
||||
#define ROUNDUP_POW2(n32) \
|
||||
{ \
|
||||
@@ -694,6 +711,35 @@ nvPrevPow2_U64(const NvU64 x )
|
||||
} \
|
||||
}
|
||||
|
||||
/*!
|
||||
* Returns the position of nth set bit in the given mask.
|
||||
*
|
||||
* Returns -1 if mask has fewer than n bits set.
|
||||
*
|
||||
* n is 0 indexed and has valid values 0..31 inclusive, so "zeroth" set bit is
|
||||
* the first set LSB.
|
||||
*
|
||||
* Example, if mask = 0x000000F0u and n = 1, the return value will be 5.
|
||||
* Example, if mask = 0x000000F0u and n = 4, the return value will be -1.
|
||||
*/
|
||||
static NV_FORCEINLINE NvS32
|
||||
nvGetNthSetBitIndex32(NvU32 mask, NvU32 n)
|
||||
{
|
||||
NvU32 seenSetBitsCount = 0;
|
||||
NvS32 index;
|
||||
FOR_EACH_INDEX_IN_MASK(32, index, mask)
|
||||
{
|
||||
if (seenSetBitsCount == n)
|
||||
{
|
||||
return index;
|
||||
}
|
||||
++seenSetBitsCount;
|
||||
}
|
||||
FOR_EACH_INDEX_IN_MASK_END;
|
||||
|
||||
return -1;
|
||||
}
|
||||
|
||||
//
|
||||
// Size to use when declaring variable-sized arrays
|
||||
//
|
||||
@@ -737,12 +783,15 @@ nvPrevPow2_U64(const NvU64 x )
|
||||
// Returns the offset (in bytes) of 'member' in struct 'type'.
|
||||
#ifndef NV_OFFSETOF
|
||||
#if defined(__GNUC__) && (__GNUC__ > 3)
|
||||
#define NV_OFFSETOF(type, member) ((NvU32)__builtin_offsetof(type, member))
|
||||
#define NV_OFFSETOF(type, member) ((NvUPtr) __builtin_offsetof(type, member))
|
||||
#else
|
||||
#define NV_OFFSETOF(type, member) ((NvU32)(NvU64)&(((type *)0)->member)) // shouldn't we use PtrToUlong? But will need to include windows header.
|
||||
#define NV_OFFSETOF(type, member) ((NvUPtr) &(((type *)0)->member))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
// Given a pointer and the member it is of the parent struct, return a pointer to the parent struct
|
||||
#define NV_CONTAINEROF(ptr, type, member) ((type *) (((NvUPtr) ptr) - NV_OFFSETOF(type, member)))
|
||||
|
||||
//
|
||||
// Performs a rounded division of b into a (unsigned). For SIGNED version of
|
||||
// NV_ROUNDED_DIV() macro check the comments in bug 769777.
|
||||
@@ -918,6 +967,30 @@ static NV_FORCEINLINE void *NV_NVUPTR_TO_PTR(NvUPtr address)
|
||||
// Use (lo) if (b) is less than 64, and (hi) if >= 64.
|
||||
//
|
||||
#define NV_BIT_SET_128(b, lo, hi) { nvAssert( (b) < 128 ); if ( (b) < 64 ) (lo) |= NVBIT64(b); else (hi) |= NVBIT64( b & 0x3F ); }
|
||||
//
|
||||
// Clear the bit at pos (b) for U64 which is < 128.
|
||||
// Use (lo) if (b) is less than 64, and (hi) if >= 64.
|
||||
//
|
||||
#define NV_BIT_CLEAR_128(b, lo, hi) { nvAssert( (b) < 128 ); if ( (b) < 64 ) (lo) &= ~NVBIT64(b); else (hi) &= ~NVBIT64( b & 0x3F ); }
|
||||
|
||||
// Get the number of elements the specified fixed-size array
|
||||
#define NV_ARRAY_ELEMENTS(x) ((sizeof(x)/sizeof((x)[0])))
|
||||
|
||||
#if !defined(NVIDIA_UNDEF_LEGACY_BIT_MACROS)
|
||||
//
|
||||
// Deprecated macros whose definition can be removed once the code base no longer references them.
|
||||
// Use the NVBIT* macros instead of these macros.
|
||||
//
|
||||
#ifndef BIT
|
||||
#define BIT(b) (1U<<(b))
|
||||
#endif
|
||||
#ifndef BIT32
|
||||
#define BIT32(b) ((NvU32)1U<<(b))
|
||||
#endif
|
||||
#ifndef BIT64
|
||||
#define BIT64(b) ((NvU64)1U<<(b))
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -150,6 +150,21 @@ NV_STATUS_CODE(NV_ERR_NVLINK_CONFIGURATION_ERROR, 0x00000078, "Nvlink Confi
|
||||
NV_STATUS_CODE(NV_ERR_RISCV_ERROR, 0x00000079, "Generic RISC-V assert or halt")
|
||||
NV_STATUS_CODE(NV_ERR_FABRIC_MANAGER_NOT_PRESENT, 0x0000007A, "Fabric Manager is not loaded")
|
||||
NV_STATUS_CODE(NV_ERR_ALREADY_SIGNALLED, 0x0000007B, "Semaphore Surface value already >= requested wait value")
|
||||
NV_STATUS_CODE(NV_ERR_QUEUE_TASK_SLOT_NOT_AVAILABLE, 0x0000007C, "PMU RPC error due to no queue slot available for this event")
|
||||
NV_STATUS_CODE(NV_ERR_KEY_ROTATION_IN_PROGRESS, 0x0000007D, "Operation not allowed as key rotation is in progress")
|
||||
NV_STATUS_CODE(NV_ERR_TEST_ONLY_CODE_NOT_ENABLED, 0x0000007E, "Test-only code path not enabled")
|
||||
NV_STATUS_CODE(NV_ERR_SECURE_BOOT_FAILED, 0x0000007F, "GFW secure boot failed")
|
||||
NV_STATUS_CODE(NV_ERR_INSUFFICIENT_ZBC_ENTRY, 0x00000080, "No more ZBC entry for the client")
|
||||
NV_STATUS_CODE(NV_ERR_NVLINK_FABRIC_NOT_READY, 0x00000081, "Nvlink Fabric Status or Fabric Probe is not yet complete, caller needs to retry")
|
||||
NV_STATUS_CODE(NV_ERR_NVLINK_FABRIC_FAILURE, 0x00000082, "Nvlink Fabric Probe failed")
|
||||
NV_STATUS_CODE(NV_ERR_GPU_MEMORY_ONLINING_FAILURE, 0x00000083, "GPU Memory Onlining failed")
|
||||
NV_STATUS_CODE(NV_ERR_REDUCTION_MANAGER_NOT_AVAILABLE, 0x00000084, "Reduction Manager is not available")
|
||||
NV_STATUS_CODE(NV_ERR_THRESHOLD_CROSSED, 0x00000085, "A fatal threshold has been crossed")
|
||||
NV_STATUS_CODE(NV_ERR_RESOURCE_RETIREMENT_ERROR, 0x00000086, "An error occurred while trying to retire a resource")
|
||||
NV_STATUS_CODE(NV_ERR_FABRIC_STATE_OUT_OF_SYNC, 0x00000087, "NVLink fabric state cached by the driver is out of sync")
|
||||
NV_STATUS_CODE(NV_ERR_BUFFER_FULL, 0x00000088, "Buffer is full")
|
||||
NV_STATUS_CODE(NV_ERR_BUFFER_EMPTY, 0x00000089, "Buffer is empty")
|
||||
NV_STATUS_CODE(NV_ERR_MC_FLA_OFFSET_TABLE_FULL, 0x0000008A, "Multicast FLA offset table has no available slots")
|
||||
|
||||
// Warnings:
|
||||
NV_STATUS_CODE(NV_WARN_HOT_SWITCH, 0x00010001, "WARNING Hot switch")
|
||||
@@ -160,5 +175,6 @@ NV_STATUS_CODE(NV_WARN_MORE_PROCESSING_REQUIRED, 0x00010005, "WARNING More
|
||||
NV_STATUS_CODE(NV_WARN_NOTHING_TO_DO, 0x00010006, "WARNING Nothing to do")
|
||||
NV_STATUS_CODE(NV_WARN_NULL_OBJECT, 0x00010007, "WARNING NULL object found")
|
||||
NV_STATUS_CODE(NV_WARN_OUT_OF_RANGE, 0x00010008, "WARNING value out of range")
|
||||
NV_STATUS_CODE(NV_WARN_THRESHOLD_CROSSED, 0x00010009, "WARNING Threshold has been crossed")
|
||||
|
||||
#endif /* SDK_NVSTATUSCODES_H */
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -24,10 +24,6 @@
|
||||
#ifndef NVTYPES_INCLUDED
|
||||
#define NVTYPES_INCLUDED
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#include "cpuopsys.h"
|
||||
|
||||
#ifndef NVTYPES_USE_STDINT
|
||||
@@ -55,6 +51,10 @@ extern "C" {
|
||||
#endif
|
||||
#endif // __cplusplus
|
||||
|
||||
#ifdef __cplusplus
|
||||
extern "C" {
|
||||
#endif
|
||||
|
||||
#if defined(MAKE_NV64TYPES_8BYTES_ALIGNED) && defined(__i386__)
|
||||
// ensure or force 8-bytes alignment of NV 64-bit types
|
||||
#define OPTIONAL_ALIGN8_ATTR __attribute__((aligned(8)))
|
||||
@@ -145,7 +145,18 @@ typedef signed short NvS16; /* -32768 to 32767 */
|
||||
#endif
|
||||
|
||||
// Macro to build an NvU32 from four bytes, listed from msb to lsb
|
||||
#define NvU32_BUILD(a, b, c, d) (((a) << 24) | ((b) << 16) | ((c) << 8) | (d))
|
||||
#define NvU32_BUILD(a, b, c, d) \
|
||||
((NvU32)( \
|
||||
(((NvU32)(a) & 0xff) << 24) | \
|
||||
(((NvU32)(b) & 0xff) << 16) | \
|
||||
(((NvU32)(c) & 0xff) << 8) | \
|
||||
(((NvU32)(d) & 0xff))))
|
||||
|
||||
// Macro to build an NvU64 from two DWORDS, listed from msb to lsb
|
||||
#define NvU64_BUILD(a, b) \
|
||||
((NvU64)( \
|
||||
(((NvU64)(a) & ~0U) << 32) | \
|
||||
(((NvU64)(b) & ~0U))))
|
||||
|
||||
#if NVTYPES_USE_STDINT
|
||||
typedef uint32_t NvV32; /* "void": enumerated or multiple fields */
|
||||
279
kernel-open/common/inc/os-interface.h
Normal file
279
kernel-open/common/inc/os-interface.h
Normal file
@@ -0,0 +1,279 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
|
||||
/*
|
||||
* Os interface definitions needed by os-interface.c
|
||||
*/
|
||||
|
||||
#ifndef OS_INTERFACE_H
|
||||
#define OS_INTERFACE_H
|
||||
|
||||
/******************* Operating System Interface Routines *******************\
|
||||
* *
|
||||
* Operating system wrapper functions used to abstract the OS. *
|
||||
* *
|
||||
\***************************************************************************/
|
||||
|
||||
#include <nvtypes.h>
|
||||
#include <nvstatus.h>
|
||||
#include "nv_stdarg.h"
|
||||
#include <nv-kernel-interface-api.h>
|
||||
#include <os/nv_memory_type.h>
|
||||
#include <os/nv_memory_area.h>
|
||||
#include <nv-caps.h>
|
||||
|
||||
#include "rs_access.h"
|
||||
|
||||
|
||||
|
||||
typedef struct
|
||||
{
|
||||
NvU32 os_major_version;
|
||||
NvU32 os_minor_version;
|
||||
NvU32 os_build_number;
|
||||
const char * os_build_version_str;
|
||||
const char * os_build_date_plus_str;
|
||||
}os_version_info;
|
||||
|
||||
/* Each OS defines its own version of this opaque type */
|
||||
struct os_work_queue;
|
||||
|
||||
/* Each OS defines its own version of this opaque type */
|
||||
typedef struct os_wait_queue os_wait_queue;
|
||||
|
||||
/*
|
||||
* ---------------------------------------------------------------------------
|
||||
*
|
||||
* Function prototypes for OS interface.
|
||||
*
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
NV_STATUS NV_API_CALL os_alloc_mem (void **, NvU64);
|
||||
void NV_API_CALL os_free_mem (void *);
|
||||
NV_STATUS NV_API_CALL os_get_system_time (NvU32 *, NvU32 *);
|
||||
NvU64 NV_API_CALL os_get_monotonic_time_ns (void);
|
||||
NvU64 NV_API_CALL os_get_monotonic_time_ns_hr (void);
|
||||
NvU64 NV_API_CALL os_get_monotonic_tick_resolution_ns (void);
|
||||
NV_STATUS NV_API_CALL os_delay (NvU32);
|
||||
NV_STATUS NV_API_CALL os_delay_us (NvU32);
|
||||
NvU64 NV_API_CALL os_get_cpu_frequency (void);
|
||||
NvU32 NV_API_CALL os_get_current_process (void);
|
||||
void NV_API_CALL os_get_current_process_name (char *, NvU32);
|
||||
NV_STATUS NV_API_CALL os_get_current_thread (NvU64 *);
|
||||
char* NV_API_CALL os_string_copy (char *, const char *);
|
||||
NvU32 NV_API_CALL os_string_length (const char *);
|
||||
NvU32 NV_API_CALL os_strtoul (const char *, char **, NvU32);
|
||||
NvS32 NV_API_CALL os_string_compare (const char *, const char *);
|
||||
NvS32 NV_API_CALL os_snprintf (char *, NvU32, const char *, ...);
|
||||
NvS32 NV_API_CALL os_vsnprintf (char *, NvU32, const char *, va_list);
|
||||
void NV_API_CALL os_log_error (const char *, va_list);
|
||||
void* NV_API_CALL os_mem_copy (void *, const void *, NvU32);
|
||||
NV_STATUS NV_API_CALL os_memcpy_from_user (void *, const void *, NvU32);
|
||||
NV_STATUS NV_API_CALL os_memcpy_to_user (void *, const void *, NvU32);
|
||||
void* NV_API_CALL os_mem_set (void *, NvU8, NvU32);
|
||||
NvS32 NV_API_CALL os_mem_cmp (const NvU8 *, const NvU8 *, NvU32);
|
||||
void* NV_API_CALL os_pci_init_handle (NvU32, NvU8, NvU8, NvU8, NvU16 *, NvU16 *);
|
||||
NV_STATUS NV_API_CALL os_pci_read_byte (void *, NvU32, NvU8 *);
|
||||
NV_STATUS NV_API_CALL os_pci_read_word (void *, NvU32, NvU16 *);
|
||||
NV_STATUS NV_API_CALL os_pci_read_dword (void *, NvU32, NvU32 *);
|
||||
NV_STATUS NV_API_CALL os_pci_write_byte (void *, NvU32, NvU8);
|
||||
NV_STATUS NV_API_CALL os_pci_write_word (void *, NvU32, NvU16);
|
||||
NV_STATUS NV_API_CALL os_pci_write_dword (void *, NvU32, NvU32);
|
||||
NvBool NV_API_CALL os_pci_remove_supported (void);
|
||||
void NV_API_CALL os_pci_remove (void *);
|
||||
void* NV_API_CALL os_map_kernel_space (NvU64, NvU64, NvU32);
|
||||
void NV_API_CALL os_unmap_kernel_space (void *, NvU64);
|
||||
#if defined(NV_VMWARE)
|
||||
void* NV_API_CALL os_map_user_space (MemoryArea *, NvU32, NvU32, void **);
|
||||
void NV_API_CALL os_unmap_user_space (void *, NvU64, void *);
|
||||
#endif
|
||||
NV_STATUS NV_API_CALL os_flush_cpu_cache_all (void);
|
||||
NV_STATUS NV_API_CALL os_flush_user_cache (void);
|
||||
void NV_API_CALL os_flush_cpu_write_combine_buffer(void);
|
||||
NvU8 NV_API_CALL os_io_read_byte (NvU32);
|
||||
NvU16 NV_API_CALL os_io_read_word (NvU32);
|
||||
NvU32 NV_API_CALL os_io_read_dword (NvU32);
|
||||
void NV_API_CALL os_io_write_byte (NvU32, NvU8);
|
||||
void NV_API_CALL os_io_write_word (NvU32, NvU16);
|
||||
void NV_API_CALL os_io_write_dword (NvU32, NvU32);
|
||||
NvBool NV_API_CALL os_is_administrator (void);
|
||||
NvBool NV_API_CALL os_check_access (RsAccessRight accessRight);
|
||||
void NV_API_CALL os_dbg_init (void);
|
||||
void NV_API_CALL os_dbg_breakpoint (void);
|
||||
void NV_API_CALL os_dbg_set_level (NvU32);
|
||||
NvU32 NV_API_CALL os_get_cpu_count (void);
|
||||
NvU32 NV_API_CALL os_get_cpu_number (void);
|
||||
void NV_API_CALL os_disable_console_access (void);
|
||||
void NV_API_CALL os_enable_console_access (void);
|
||||
NV_STATUS NV_API_CALL os_registry_init (void);
|
||||
NvU64 NV_API_CALL os_get_max_user_va (void);
|
||||
NV_STATUS NV_API_CALL os_schedule (void);
|
||||
NV_STATUS NV_API_CALL os_alloc_spinlock (void **);
|
||||
void NV_API_CALL os_free_spinlock (void *);
|
||||
NvU64 NV_API_CALL os_acquire_spinlock (void *);
|
||||
void NV_API_CALL os_release_spinlock (void *, NvU64);
|
||||
NV_STATUS NV_API_CALL os_queue_work_item (struct os_work_queue *, void *);
|
||||
NV_STATUS NV_API_CALL os_flush_work_queue (struct os_work_queue *, NvBool);
|
||||
NvBool NV_API_CALL os_is_queue_flush_ongoing (struct os_work_queue *);
|
||||
NV_STATUS NV_API_CALL os_alloc_mutex (void **);
|
||||
void NV_API_CALL os_free_mutex (void *);
|
||||
NV_STATUS NV_API_CALL os_acquire_mutex (void *);
|
||||
NV_STATUS NV_API_CALL os_cond_acquire_mutex (void *);
|
||||
void NV_API_CALL os_release_mutex (void *);
|
||||
void* NV_API_CALL os_alloc_semaphore (NvU32);
|
||||
void NV_API_CALL os_free_semaphore (void *);
|
||||
NV_STATUS NV_API_CALL os_acquire_semaphore (void *);
|
||||
NV_STATUS NV_API_CALL os_cond_acquire_semaphore (void *);
|
||||
NV_STATUS NV_API_CALL os_release_semaphore (void *);
|
||||
void* NV_API_CALL os_alloc_rwlock (void);
|
||||
void NV_API_CALL os_free_rwlock (void *);
|
||||
NV_STATUS NV_API_CALL os_acquire_rwlock_read (void *);
|
||||
NV_STATUS NV_API_CALL os_acquire_rwlock_write (void *);
|
||||
NV_STATUS NV_API_CALL os_cond_acquire_rwlock_read (void *);
|
||||
NV_STATUS NV_API_CALL os_cond_acquire_rwlock_write (void *);
|
||||
void NV_API_CALL os_release_rwlock_read (void *);
|
||||
void NV_API_CALL os_release_rwlock_write (void *);
|
||||
NvBool NV_API_CALL os_semaphore_may_sleep (void);
|
||||
NV_STATUS NV_API_CALL os_get_version_info (os_version_info*);
|
||||
NV_STATUS NV_API_CALL os_get_is_openrm (NvBool *);
|
||||
NvBool NV_API_CALL os_is_isr (void);
|
||||
NvBool NV_API_CALL os_pat_supported (void);
|
||||
void NV_API_CALL os_dump_stack (void);
|
||||
NvBool NV_API_CALL os_is_efi_enabled (void);
|
||||
NvBool NV_API_CALL os_is_xen_dom0 (void);
|
||||
NvBool NV_API_CALL os_is_vgx_hyper (void);
|
||||
NV_STATUS NV_API_CALL os_inject_vgx_msi (NvU16, NvU64, NvU32);
|
||||
NvBool NV_API_CALL os_is_grid_supported (void);
|
||||
NvU32 NV_API_CALL os_get_grid_csp_support (void);
|
||||
void NV_API_CALL os_bug_check (NvU32, const char *);
|
||||
NV_STATUS NV_API_CALL os_lock_user_pages (void *, NvU64, void **, NvU32);
|
||||
NV_STATUS NV_API_CALL os_lookup_user_io_memory (void *, NvU64, NvU64 **);
|
||||
NV_STATUS NV_API_CALL os_unlock_user_pages (NvU64, void *, NvU32);
|
||||
NV_STATUS NV_API_CALL os_match_mmap_offset (void *, NvU64, NvU64 *);
|
||||
NV_STATUS NV_API_CALL os_get_euid (NvU32 *);
|
||||
NV_STATUS NV_API_CALL os_get_smbios_header (NvU64 *pSmbsAddr);
|
||||
NV_STATUS NV_API_CALL os_get_acpi_rsdp_from_uefi (NvU32 *);
|
||||
void NV_API_CALL os_add_record_for_crashLog (void *, NvU32);
|
||||
void NV_API_CALL os_delete_record_for_crashLog (void *);
|
||||
NV_STATUS NV_API_CALL os_call_vgpu_vfio (void *, NvU32);
|
||||
NV_STATUS NV_API_CALL os_device_vm_present (void);
|
||||
NV_STATUS NV_API_CALL os_numa_memblock_size (NvU64 *);
|
||||
NV_STATUS NV_API_CALL os_alloc_pages_node (NvS32, NvU32, NvU32, NvU64 *);
|
||||
NV_STATUS NV_API_CALL os_get_page (NvU64 address);
|
||||
NV_STATUS NV_API_CALL os_put_page (NvU64 address);
|
||||
NvU32 NV_API_CALL os_get_page_refcount (NvU64 address);
|
||||
NvU32 NV_API_CALL os_count_tail_pages (NvU64 address);
|
||||
void NV_API_CALL os_free_pages_phys (NvU64, NvU32);
|
||||
NV_STATUS NV_API_CALL os_open_temporary_file (void **);
|
||||
void NV_API_CALL os_close_file (void *);
|
||||
NV_STATUS NV_API_CALL os_write_file (void *, NvU8 *, NvU64, NvU64);
|
||||
NV_STATUS NV_API_CALL os_read_file (void *, NvU8 *, NvU64, NvU64);
|
||||
NV_STATUS NV_API_CALL os_open_readonly_file (const char *, void **);
|
||||
NV_STATUS NV_API_CALL os_open_and_read_file (const char *, NvU8 *, NvU64);
|
||||
NvBool NV_API_CALL os_is_nvswitch_present (void);
|
||||
NV_STATUS NV_API_CALL os_get_random_bytes (NvU8 *, NvU16);
|
||||
NV_STATUS NV_API_CALL os_alloc_wait_queue (os_wait_queue **);
|
||||
void NV_API_CALL os_free_wait_queue (os_wait_queue *);
|
||||
void NV_API_CALL os_wait_uninterruptible (os_wait_queue *);
|
||||
void NV_API_CALL os_wait_interruptible (os_wait_queue *);
|
||||
void NV_API_CALL os_wake_up (os_wait_queue *);
|
||||
nv_cap_t* NV_API_CALL os_nv_cap_init (const char *);
|
||||
nv_cap_t* NV_API_CALL os_nv_cap_create_dir_entry (nv_cap_t *, const char *, int);
|
||||
nv_cap_t* NV_API_CALL os_nv_cap_create_file_entry (nv_cap_t *, const char *, int);
|
||||
void NV_API_CALL os_nv_cap_destroy_entry (nv_cap_t *);
|
||||
int NV_API_CALL os_nv_cap_validate_and_dup_fd (const nv_cap_t *, int);
|
||||
void NV_API_CALL os_nv_cap_close_fd (int);
|
||||
NvS32 NV_API_CALL os_imex_channel_get (NvU64);
|
||||
NvS32 NV_API_CALL os_imex_channel_count (void);
|
||||
NV_STATUS NV_API_CALL os_tegra_igpu_perf_boost (void *, NvBool, NvU32);
|
||||
|
||||
NV_STATUS NV_API_CALL os_get_tegra_platform (NvU32 *);
|
||||
enum os_pci_req_atomics_type {
|
||||
OS_INTF_PCIE_REQ_ATOMICS_32BIT,
|
||||
OS_INTF_PCIE_REQ_ATOMICS_64BIT,
|
||||
OS_INTF_PCIE_REQ_ATOMICS_128BIT
|
||||
};
|
||||
NV_STATUS NV_API_CALL os_enable_pci_req_atomics (void *, enum os_pci_req_atomics_type);
|
||||
void NV_API_CALL os_pci_trigger_flr(void *handle);
|
||||
NV_STATUS NV_API_CALL os_get_numa_node_memory_usage (NvS32, NvU64 *, NvU64 *);
|
||||
NV_STATUS NV_API_CALL os_numa_add_gpu_memory (void *, NvU64, NvU64, NvU32 *);
|
||||
NV_STATUS NV_API_CALL os_numa_remove_gpu_memory (void *, NvU64, NvU64, NvU32);
|
||||
NV_STATUS NV_API_CALL os_offline_page_at_address(NvU64 address);
|
||||
void* NV_API_CALL os_get_pid_info(void);
|
||||
void NV_API_CALL os_put_pid_info(void *pid_info);
|
||||
NV_STATUS NV_API_CALL os_find_ns_pid(void *pid_info, NvU32 *ns_pid);
|
||||
NvBool NV_API_CALL os_is_init_ns(void);
|
||||
NV_STATUS NV_API_CALL os_iommu_sva_bind(void *arg, void **handle, NvU32 *pasid);
|
||||
void NV_API_CALL os_iommu_sva_unbind(void *handle);
|
||||
|
||||
extern NvU64 os_page_size;
|
||||
extern NvU64 os_max_page_size;
|
||||
extern NvU64 os_page_mask;
|
||||
extern NvU8 os_page_shift;
|
||||
extern NvBool os_cc_enabled;
|
||||
extern NvBool os_cc_sev_snp_enabled;
|
||||
extern NvBool os_cc_sme_enabled;
|
||||
extern NvBool os_cc_snp_vtom_enabled;
|
||||
extern NvBool os_cc_tdx_enabled;
|
||||
extern NvBool os_dma_buf_enabled;
|
||||
extern NvBool os_imex_channel_is_supported;
|
||||
|
||||
/*
|
||||
* ---------------------------------------------------------------------------
|
||||
*
|
||||
* Debug macros.
|
||||
*
|
||||
* ---------------------------------------------------------------------------
|
||||
*/
|
||||
|
||||
#define NV_DBG_INFO 0x0
|
||||
#define NV_DBG_SETUP 0x1
|
||||
#define NV_DBG_USERERRORS 0x2
|
||||
#define NV_DBG_WARNINGS 0x3
|
||||
#define NV_DBG_ERRORS 0x4
|
||||
|
||||
|
||||
void NV_API_CALL out_string(const char *str);
|
||||
int NV_API_CALL nv_printf(NvU32 debuglevel, const char *printf_format, ...);
|
||||
|
||||
#define NV_DEV_PRINTF(debuglevel, nv, format, ... ) \
|
||||
nv_printf(debuglevel, "NVRM: GPU " NV_PCI_DEV_FMT ": " format, NV_PCI_DEV_FMT_ARGS(nv), ## __VA_ARGS__)
|
||||
|
||||
#define NV_DEV_PRINTF_STATUS(debuglevel, nv, status, format, ... ) \
|
||||
nv_printf(debuglevel, "NVRM: GPU " NV_PCI_DEV_FMT ": " format " (0x%x)\n", NV_PCI_DEV_FMT_ARGS(nv), ## __VA_ARGS__, status)
|
||||
|
||||
/*
|
||||
* Fields for os_lock_user_pages flags parameter
|
||||
*/
|
||||
#define NV_LOCK_USER_PAGES_FLAGS_WRITE 0:0
|
||||
#define NV_LOCK_USER_PAGES_FLAGS_WRITE_NO 0x00000000
|
||||
#define NV_LOCK_USER_PAGES_FLAGS_WRITE_YES 0x00000001
|
||||
|
||||
// NV OS Tegra platform type defines
|
||||
#define NV_OS_TEGRA_PLATFORM_SIM 0
|
||||
#define NV_OS_TEGRA_PLATFORM_FPGA 1
|
||||
#define NV_OS_TEGRA_PLATFORM_SILICON 2
|
||||
|
||||
#endif /* OS_INTERFACE_H */
|
||||
104
kernel-open/common/inc/os/nv_memory_area.h
Normal file
104
kernel-open/common/inc/os/nv_memory_area.h
Normal file
@@ -0,0 +1,104 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef NV_MEMORY_AREA_H
|
||||
#define NV_MEMORY_AREA_H
|
||||
|
||||
typedef struct MemoryRange
|
||||
{
|
||||
NvU64 start;
|
||||
NvU64 size;
|
||||
} MemoryRange;
|
||||
|
||||
typedef struct MemoryArea
|
||||
{
|
||||
MemoryRange *pRanges;
|
||||
NvU64 numRanges;
|
||||
} MemoryArea;
|
||||
|
||||
static inline NvU64 memareaSize(MemoryArea memArea)
|
||||
{
|
||||
NvU64 size = 0;
|
||||
NvU64 idx = 0;
|
||||
for (idx = 0; idx < memArea.numRanges; idx++)
|
||||
{
|
||||
size += memArea.pRanges[idx].size;
|
||||
}
|
||||
return size;
|
||||
}
|
||||
|
||||
static inline MemoryRange
|
||||
mrangeMake
|
||||
(
|
||||
NvU64 start,
|
||||
NvU64 size
|
||||
)
|
||||
{
|
||||
MemoryRange range;
|
||||
range.start = start;
|
||||
range.size = size;
|
||||
return range;
|
||||
}
|
||||
|
||||
static inline NvU64
|
||||
mrangeLimit
|
||||
(
|
||||
MemoryRange a
|
||||
)
|
||||
{
|
||||
return a.start + a.size;
|
||||
}
|
||||
|
||||
static inline NvBool
|
||||
mrangeIntersects
|
||||
(
|
||||
MemoryRange a,
|
||||
MemoryRange b
|
||||
)
|
||||
{
|
||||
return ((a.start >= b.start) && (a.start < mrangeLimit(b))) ||
|
||||
((b.start >= a.start) && (b.start < mrangeLimit(a)));
|
||||
}
|
||||
|
||||
static inline NvBool
|
||||
mrangeContains
|
||||
(
|
||||
MemoryRange outer,
|
||||
MemoryRange inner
|
||||
)
|
||||
{
|
||||
return (inner.start >= outer.start) && (mrangeLimit(inner) <= mrangeLimit(outer));
|
||||
}
|
||||
|
||||
static inline MemoryRange
|
||||
mrangeOffset
|
||||
(
|
||||
MemoryRange range,
|
||||
NvU64 amt
|
||||
)
|
||||
{
|
||||
range.start += amt;
|
||||
return range;
|
||||
}
|
||||
|
||||
#endif /* NV_MEMORY_AREA_H */
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2020 - 2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -27,6 +27,8 @@ typedef enum
|
||||
{
|
||||
NV_OS_GPIO_FUNC_HOTPLUG_A,
|
||||
NV_OS_GPIO_FUNC_HOTPLUG_B,
|
||||
NV_OS_GPIO_FUNC_HOTPLUG_C,
|
||||
NV_OS_GPIO_FUNC_HOTPLUG_D,
|
||||
} NV_OS_GPIO_FUNC_NAMES;
|
||||
|
||||
#endif
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1999-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -37,7 +37,7 @@ NV_STATUS NV_API_CALL rm_gpu_ops_create_session (nvidia_stack_t *, nvgpuSessio
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_destroy_session (nvidia_stack_t *, nvgpuSessionHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_device_create (nvidia_stack_t *, nvgpuSessionHandle_t, const nvgpuInfo_t *, const NvProcessorUuid *, nvgpuDeviceHandle_t *, NvBool);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_device_destroy (nvidia_stack_t *, nvgpuDeviceHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_address_space_create(nvidia_stack_t *, nvgpuDeviceHandle_t, unsigned long long, unsigned long long, nvgpuAddressSpaceHandle_t *, nvgpuAddressSpaceInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_address_space_create(nvidia_stack_t *, nvgpuDeviceHandle_t, unsigned long long, unsigned long long, NvBool, nvgpuAddressSpaceHandle_t *, nvgpuAddressSpaceInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_dup_address_space(nvidia_stack_t *, nvgpuDeviceHandle_t, NvHandle, NvHandle, nvgpuAddressSpaceHandle_t *, nvgpuAddressSpaceInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_address_space_destroy(nvidia_stack_t *, nvgpuAddressSpaceHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_memory_alloc_fb(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvLength, NvU64 *, nvgpuAllocInfo_t);
|
||||
@@ -45,7 +45,6 @@ NV_STATUS NV_API_CALL rm_gpu_ops_memory_alloc_fb(nvidia_stack_t *, nvgpuAddres
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_pma_alloc_pages(nvidia_stack_t *, void *, NvLength, NvU32 , nvgpuPmaAllocationOptions_t, NvU64 *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_pma_free_pages(nvidia_stack_t *, void *, NvU64 *, NvLength , NvU32, NvU32);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_pma_pin_pages(nvidia_stack_t *, void *, NvU64 *, NvLength , NvU32, NvU32);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_pma_unpin_pages(nvidia_stack_t *, void *, NvU64 *, NvLength , NvU32);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_get_pma_object(nvidia_stack_t *, nvgpuDeviceHandle_t, void **, const nvgpuPmaStatistics_t *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_pma_register_callbacks(nvidia_stack_t *sp, void *, nvPmaEvictPagesCallback, nvPmaEvictRangeCallback, void *);
|
||||
void NV_API_CALL rm_gpu_ops_pma_unregister_callbacks(nvidia_stack_t *sp, void *);
|
||||
@@ -76,18 +75,21 @@ NV_STATUS NV_API_CALL rm_gpu_ops_own_page_fault_intr(nvidia_stack_t *, nvgpuDevi
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_init_fault_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuFaultInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_destroy_fault_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuFaultInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_get_non_replayable_faults(nvidia_stack_t *, nvgpuFaultInfo_t, void *, NvU32 *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_flush_replayable_fault_buffer(nvidia_stack_t *, nvgpuDeviceHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_flush_replayable_fault_buffer(nvidia_stack_t *, nvgpuFaultInfo_t, NvBool);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_toggle_prefetch_faults(nvidia_stack_t *, nvgpuFaultInfo_t, NvBool);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_has_pending_non_replayable_faults(nvidia_stack_t *, nvgpuFaultInfo_t, NvBool *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_init_access_cntr_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t, NvU32);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_destroy_access_cntr_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_own_access_cntr_intr(nvidia_stack_t *, nvgpuSessionHandle_t, nvgpuAccessCntrInfo_t, NvBool);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_enable_access_cntr(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t, nvgpuAccessCntrConfig_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_enable_access_cntr(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t, const nvgpuAccessCntrConfig_t *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_disable_access_cntr(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuAccessCntrInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_set_page_directory (nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, unsigned, NvBool, NvU32);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_set_page_directory (nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, unsigned, NvBool, NvU32, NvU64 *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_unset_page_directory (nvidia_stack_t *, nvgpuAddressSpaceHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_get_nvlink_info(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuNvlinkInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_p2p_object_create(nvidia_stack_t *, nvgpuDeviceHandle_t, nvgpuDeviceHandle_t, NvHandle *);
|
||||
void NV_API_CALL rm_gpu_ops_p2p_object_destroy(nvidia_stack_t *, nvgpuSessionHandle_t, NvHandle);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_get_external_alloc_ptes(nvidia_stack_t*, nvgpuAddressSpaceHandle_t, NvHandle, NvU64, NvU64, nvgpuExternalMappingInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_get_external_alloc_phys_addrs(nvidia_stack_t*, nvgpuAddressSpaceHandle_t, NvHandle, NvU64, NvU64, nvgpuExternalPhysAddrInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_retain_channel(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvHandle, NvHandle, void **, nvgpuChannelInstanceInfo_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_bind_channel_resources(nvidia_stack_t *, void *, nvgpuChannelResourceBindParams_t);
|
||||
void NV_API_CALL rm_gpu_ops_release_channel(nvidia_stack_t *, void *);
|
||||
@@ -100,15 +102,18 @@ void NV_API_CALL rm_gpu_ops_paging_channel_destroy(nvidia_stack_t *, nvgpu
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_paging_channels_map(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, nvgpuDeviceHandle_t, NvU64 *);
|
||||
void NV_API_CALL rm_gpu_ops_paging_channels_unmap(nvidia_stack_t *, nvgpuAddressSpaceHandle_t, NvU64, nvgpuDeviceHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_paging_channel_push_stream(nvidia_stack_t *, nvgpuPagingChannelHandle_t, char *, NvU32);
|
||||
void NV_API_CALL rm_gpu_ops_report_fatal_error(nvidia_stack_t *, NV_STATUS error);
|
||||
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_init(nvidia_stack_t *, struct ccslContext_t **, nvgpuChannelHandle_t);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_context_clear(nvidia_stack_t *, struct ccslContext_t *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_rotate_key(nvidia_stack_t *, UvmCslContext *[], NvU32);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_rotate_iv(nvidia_stack_t *, struct ccslContext_t *, NvU8);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_encrypt(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8 *, NvU8 *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_encrypt_with_iv(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8*, NvU8 *, NvU8 *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_decrypt(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8 const *, NvU8 *, NvU8 const *, NvU32, NvU8 const *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_decrypt(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8 const *, NvU32, NvU8 *, NvU8 const *, NvU32, NvU8 const *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_sign(nvidia_stack_t *, struct ccslContext_t *, NvU32, NvU8 const *, NvU8 *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_query_message_pool(nvidia_stack_t *, struct ccslContext_t *, NvU8, NvU64 *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_increment_iv(nvidia_stack_t *, struct ccslContext_t *, NvU8, NvU64, NvU8 *);
|
||||
NV_STATUS NV_API_CALL rm_gpu_ops_ccsl_log_encryption(nvidia_stack_t *, struct ccslContext_t *, NvU8, NvU32);
|
||||
|
||||
#endif
|
||||
276
kernel-open/common/inc/rs_access.h
Normal file
276
kernel-open/common/inc/rs_access.h
Normal file
@@ -0,0 +1,276 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2019-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
#pragma once
|
||||
|
||||
#include <nvtypes.h>
|
||||
#if defined(_MSC_VER)
|
||||
#pragma warning(disable:4324)
|
||||
#endif
|
||||
|
||||
//
|
||||
// This file was generated with FINN, an NVIDIA coding tool.
|
||||
// Source file: rs_access.finn
|
||||
//
|
||||
|
||||
|
||||
|
||||
|
||||
#include "nvtypes.h"
|
||||
#include "nvmisc.h"
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
/* Access right definitions */
|
||||
/****************************************************************************/
|
||||
|
||||
//
|
||||
// The meaning of each access right is documented in
|
||||
// resman/docs/rmapi/resource_server/rm_capabilities.adoc
|
||||
//
|
||||
// RS_ACCESS_COUNT is the number of access rights that have been defined
|
||||
// and are in use. All integers in the range [0, RS_ACCESS_COUNT) should
|
||||
// represent valid access rights.
|
||||
//
|
||||
// When adding a new access right, don't forget to update
|
||||
// 1) The descriptions in the resman/docs/rmapi/resource_server/rm_capabilities.adoc
|
||||
// 2) RS_ACCESS_COUNT, defined below
|
||||
// 3) The declaration of g_rsAccessMetadata in rs_access_rights.c
|
||||
// 4) The list of access rights in drivers/common/chip-config/Chipcontrols.pm
|
||||
// 5) Any relevant access right callbacks
|
||||
//
|
||||
|
||||
#define RS_ACCESS_DUP_OBJECT 0U
|
||||
#define RS_ACCESS_NICE 1U
|
||||
#define RS_ACCESS_DEBUG 2U
|
||||
#define RS_ACCESS_PERFMON 3U
|
||||
#define RS_ACCESS_COUNT 4U
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
/* Access right data structures */
|
||||
/****************************************************************************/
|
||||
|
||||
/*!
|
||||
* @brief A type that can be used to represent any access right.
|
||||
*/
|
||||
typedef NvU16 RsAccessRight;
|
||||
|
||||
/*!
|
||||
* @brief An internal type used to represent one limb in an access right mask.
|
||||
*/
|
||||
typedef NvU32 RsAccessLimb;
|
||||
#define SDK_RS_ACCESS_LIMB_BITS 32
|
||||
|
||||
/*!
|
||||
* @brief The number of limbs in the RS_ACCESS_MASK struct.
|
||||
*/
|
||||
#define SDK_RS_ACCESS_MAX_LIMBS 1
|
||||
|
||||
/*!
|
||||
* @brief The maximum number of possible access rights supported by the
|
||||
* current data structure definition.
|
||||
*
|
||||
* You probably want RS_ACCESS_COUNT instead, which is the number of actual
|
||||
* access rights defined.
|
||||
*/
|
||||
#define SDK_RS_ACCESS_MAX_COUNT (0x20) /* finn: Evaluated from "(SDK_RS_ACCESS_LIMB_BITS * SDK_RS_ACCESS_MAX_LIMBS)" */
|
||||
|
||||
/**
|
||||
* @brief A struct representing a set of access rights.
|
||||
*
|
||||
* Note that the values of bit positions larger than RS_ACCESS_COUNT is
|
||||
* undefined, and should not be assumed to be 0 (see RS_ACCESS_MASK_FILL).
|
||||
*/
|
||||
typedef struct RS_ACCESS_MASK {
|
||||
RsAccessLimb limbs[SDK_RS_ACCESS_MAX_LIMBS];
|
||||
} RS_ACCESS_MASK;
|
||||
|
||||
/**
|
||||
* @brief A struct representing auxiliary information about each access right.
|
||||
*/
|
||||
typedef struct RS_ACCESS_INFO {
|
||||
NvU32 flags;
|
||||
} RS_ACCESS_INFO;
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
/* Access right macros */
|
||||
/****************************************************************************/
|
||||
|
||||
#define SDK_RS_ACCESS_LIMB_INDEX(index) ((index) / SDK_RS_ACCESS_LIMB_BITS)
|
||||
#define SDK_RS_ACCESS_LIMB_POS(index) ((index) % SDK_RS_ACCESS_LIMB_BITS)
|
||||
|
||||
#define SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) \
|
||||
((pAccessMask)->limbs[SDK_RS_ACCESS_LIMB_INDEX(index)])
|
||||
#define SDK_RS_ACCESS_OFFSET_MASK(index) \
|
||||
NVBIT_TYPE(SDK_RS_ACCESS_LIMB_POS(index), RsAccessLimb)
|
||||
|
||||
/*!
|
||||
* @brief Checks that accessRight represents a valid access right.
|
||||
*
|
||||
* The valid range of access rights is [0, RS_ACCESS_COUNT).
|
||||
*
|
||||
* @param[in] accessRight The access right value to check
|
||||
*
|
||||
* @return true if accessRight is valid
|
||||
* @return false otherwise
|
||||
*/
|
||||
#define RS_ACCESS_BOUNDS_CHECK(accessRight) \
|
||||
(accessRight < RS_ACCESS_COUNT)
|
||||
|
||||
/*!
|
||||
* @brief Test whether an access right is present in a set
|
||||
*
|
||||
* @param[in] pAccessMask The set of access rights to read
|
||||
* @param[in] index The access right to examine
|
||||
*
|
||||
* @return NV_TRUE if the access right specified by index was present in the set,
|
||||
* and NV_FALSE otherwise
|
||||
*/
|
||||
#define RS_ACCESS_MASK_TEST(pAccessMask, index) \
|
||||
(RS_ACCESS_BOUNDS_CHECK(index) && \
|
||||
(SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) & SDK_RS_ACCESS_OFFSET_MASK(index)) != 0)
|
||||
|
||||
/*!
|
||||
* @brief Add an access right to a mask
|
||||
*
|
||||
* @param[in] pAccessMask The set of access rights to modify
|
||||
* @param[in] index The access right to set
|
||||
*/
|
||||
#define RS_ACCESS_MASK_ADD(pAccessMask, index) \
|
||||
do \
|
||||
{ \
|
||||
if (RS_ACCESS_BOUNDS_CHECK(index)) { \
|
||||
SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) |= SDK_RS_ACCESS_OFFSET_MASK(index); \
|
||||
} \
|
||||
} while (NV_FALSE)
|
||||
|
||||
/*!
|
||||
* @brief Remove an access right from a mask
|
||||
*
|
||||
* @param[in] pAccessMask The set of access rights to modify
|
||||
* @param[in] index The access right to unset
|
||||
*/
|
||||
#define RS_ACCESS_MASK_REMOVE(pAccessMask, index) \
|
||||
do \
|
||||
{ \
|
||||
if (RS_ACCESS_BOUNDS_CHECK(index)) { \
|
||||
SDK_RS_ACCESS_LIMB_ELT(pAccessMask, index) &= ~SDK_RS_ACCESS_OFFSET_MASK(index); \
|
||||
} \
|
||||
} while (NV_FALSE)
|
||||
|
||||
/*!
|
||||
* @brief Performs an in-place union between two access right masks
|
||||
*
|
||||
* @param[in,out] pMaskOut The access rights mask to be updated
|
||||
* @param[in] pMaskIn The set of access rights to be added to pMaskOut
|
||||
*/
|
||||
#define RS_ACCESS_MASK_UNION(pMaskOut, pMaskIn) \
|
||||
do \
|
||||
{ \
|
||||
NvLength limb; \
|
||||
for (limb = 0; limb < SDK_RS_ACCESS_MAX_LIMBS; limb++) \
|
||||
{ \
|
||||
SDK_RS_ACCESS_LIMB_ELT(pMaskOut, limb) |= SDK_RS_ACCESS_LIMB_ELT(pMaskIn, limb); \
|
||||
} \
|
||||
} while (NV_FALSE)
|
||||
|
||||
/*!
|
||||
* @brief Performs an in-place subtract of one mask's rights from another
|
||||
*
|
||||
* @param[in,out] pMaskOut The access rights mask to be updated
|
||||
* @param[in] pMaskIn The set of access rights to be removed from pMaskOut
|
||||
*/
|
||||
#define RS_ACCESS_MASK_SUBTRACT(pMaskOut, pMaskIn) \
|
||||
do \
|
||||
{ \
|
||||
NvLength limb; \
|
||||
for (limb = 0; limb < SDK_RS_ACCESS_MAX_LIMBS; limb++) \
|
||||
{ \
|
||||
SDK_RS_ACCESS_LIMB_ELT(pMaskOut, limb) &= ~SDK_RS_ACCESS_LIMB_ELT(pMaskIn, limb); \
|
||||
} \
|
||||
} while (NV_FALSE)
|
||||
|
||||
/*!
|
||||
* @brief Removes all rights from an access rights mask
|
||||
*
|
||||
* @param[in,out] pAccessMask The access rights mask to be updated
|
||||
*/
|
||||
#define RS_ACCESS_MASK_CLEAR(pAccessMask) \
|
||||
do \
|
||||
{ \
|
||||
portMemSet(pAccessMask, 0, sizeof(*pAccessMask)); \
|
||||
} while (NV_FALSE)
|
||||
|
||||
/*!
|
||||
* @brief Adds all rights to an access rights mask
|
||||
*
|
||||
* @param[in,out] pAccessMask The access rights mask to be updated
|
||||
*/
|
||||
#define RS_ACCESS_MASK_FILL(pAccessMask) \
|
||||
do \
|
||||
{ \
|
||||
portMemSet(pAccessMask, 0xff, sizeof(*pAccessMask)); \
|
||||
} while (NV_FALSE)
|
||||
|
||||
|
||||
/****************************************************************************/
|
||||
/* Share definitions */
|
||||
/****************************************************************************/
|
||||
|
||||
//
|
||||
// The usage of Share Policy and the meaning of each share type is documented in
|
||||
// resman/docs/rmapi/resource_server/rm_capabilities.adoc
|
||||
//
|
||||
#define RS_SHARE_TYPE_NONE (0U)
|
||||
#define RS_SHARE_TYPE_ALL (1U)
|
||||
#define RS_SHARE_TYPE_OS_SECURITY_TOKEN (2U)
|
||||
#define RS_SHARE_TYPE_CLIENT (3U)
|
||||
#define RS_SHARE_TYPE_PID (4U)
|
||||
#define RS_SHARE_TYPE_SMC_PARTITION (5U)
|
||||
#define RS_SHARE_TYPE_GPU (6U)
|
||||
#define RS_SHARE_TYPE_FM_CLIENT (7U)
|
||||
// Must be last. Update when a new SHARE_TYPE is added
|
||||
#define RS_SHARE_TYPE_MAX (8U)
|
||||
|
||||
|
||||
//
|
||||
// Use Revoke to remove an existing policy from the list.
|
||||
// Allow is based on OR logic, Require is based on AND logic.
|
||||
// To share a right, at least one Allow (non-Require) must match, and all Require must pass.
|
||||
// If Compose is specified, policies will be added to the list. Otherwise, they will replace the list.
|
||||
//
|
||||
#define RS_SHARE_ACTION_FLAG_REVOKE NVBIT(0)
|
||||
#define RS_SHARE_ACTION_FLAG_REQUIRE NVBIT(1)
|
||||
#define RS_SHARE_ACTION_FLAG_COMPOSE NVBIT(2)
|
||||
|
||||
/****************************************************************************/
|
||||
/* Share flag data structures */
|
||||
/****************************************************************************/
|
||||
|
||||
typedef struct RS_SHARE_POLICY {
|
||||
NvU32 target;
|
||||
RS_ACCESS_MASK accessMask;
|
||||
NvU16 type; ///< RS_SHARE_TYPE_
|
||||
NvU8 action; ///< RS_SHARE_ACTION_
|
||||
} RS_SHARE_POLICY;
|
||||
File diff suppressed because it is too large
Load Diff
45
kernel-open/header-presence-tests.mk
Normal file
45
kernel-open/header-presence-tests.mk
Normal file
@@ -0,0 +1,45 @@
|
||||
# Each of these headers is checked for presence with a test #include; a
|
||||
# corresponding #define will be generated in conftest/headers.h.
|
||||
NV_HEADER_PRESENCE_TESTS = \
|
||||
asm/system.h \
|
||||
drm/drm_hdcp.h \
|
||||
drm/display/drm_hdcp.h \
|
||||
drm/display/drm_hdcp_helper.h \
|
||||
drm/drmP.h \
|
||||
drm/drm_aperture.h \
|
||||
drm/drm_atomic_state_helper.h \
|
||||
drm/drm_atomic_uapi.h \
|
||||
drm/drm_fbdev_generic.h \
|
||||
drm/drm_fbdev_ttm.h \
|
||||
drm/drm_client_setup.h \
|
||||
drm/drm_probe_helper.h \
|
||||
drm/clients/drm_client_setup.h \
|
||||
dt-bindings/interconnect/tegra_icc_id.h \
|
||||
generated/autoconf.h \
|
||||
generated/compile.h \
|
||||
generated/utsrelease.h \
|
||||
linux/aperture.h \
|
||||
linux/dma-direct.h \
|
||||
linux/platform/tegra/mc_utils.h \
|
||||
xen/ioemu.h \
|
||||
linux/fence.h \
|
||||
linux/dma-resv.h \
|
||||
soc/tegra/tegra_bpmp.h \
|
||||
linux/platform/tegra/dce/dce-client-ipc.h \
|
||||
linux/nvhost.h \
|
||||
linux/nvhost_t194.h \
|
||||
linux/host1x-next.h \
|
||||
asm/set_memory.h \
|
||||
asm/pgtable_types.h \
|
||||
linux/dma-map-ops.h \
|
||||
sound/hda_codec.h \
|
||||
linux/interconnect.h \
|
||||
linux/ioasid.h \
|
||||
linux/stdarg.h \
|
||||
linux/iosys-map.h \
|
||||
linux/vfio_pci_core.h \
|
||||
linux/cc_platform.h \
|
||||
linux/slub_def.h \
|
||||
asm/mshyperv.h \
|
||||
crypto/sig.h
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2016 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2016-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -29,12 +29,7 @@
|
||||
#include <linux/completion.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/mm.h>
|
||||
|
||||
#if defined(NV_LINUX_BUG_H_PRESENT)
|
||||
#include <linux/bug.h>
|
||||
#else
|
||||
#include <asm/bug.h>
|
||||
#endif
|
||||
#include <linux/bug.h>
|
||||
|
||||
// Today's implementation is a little simpler and more limited than the
|
||||
// API description allows for in nv-kthread-q.h. Details include:
|
||||
@@ -176,7 +171,7 @@ static struct task_struct *thread_create_on_node(int (*threadfn)(void *data),
|
||||
{
|
||||
|
||||
unsigned i, j;
|
||||
const static unsigned attempts = 3;
|
||||
static const unsigned attempts = 3;
|
||||
struct task_struct *thread[3];
|
||||
|
||||
for (i = 0;; i++) {
|
||||
@@ -201,7 +196,7 @@ static struct task_struct *thread_create_on_node(int (*threadfn)(void *data),
|
||||
|
||||
// Ran out of attempts - return thread even if its stack may not be
|
||||
// allocated on the preferred node
|
||||
if ((i == (attempts - 1)))
|
||||
if (i == (attempts - 1))
|
||||
break;
|
||||
|
||||
// Get the NUMA node where the first page of the stack is resident. If
|
||||
@@ -247,6 +242,11 @@ int nv_kthread_q_init_on_node(nv_kthread_q_t *q, const char *q_name, int preferr
|
||||
return 0;
|
||||
}
|
||||
|
||||
int nv_kthread_q_init(nv_kthread_q_t *q, const char *qname)
|
||||
{
|
||||
return nv_kthread_q_init_on_node(q, qname, NV_KTHREAD_NO_NODE);
|
||||
}
|
||||
|
||||
// Returns true (non-zero) if the item was actually scheduled, and false if the
|
||||
// item was already pending in a queue.
|
||||
static int _raw_q_schedule(nv_kthread_q_t *q, nv_kthread_q_item_t *q_item)
|
||||
@@ -25,6 +25,15 @@
|
||||
#include <linux/module.h>
|
||||
|
||||
#include "nv-pci-table.h"
|
||||
#include "cpuopsys.h"
|
||||
|
||||
#if defined(NV_BSD)
|
||||
/* Define PCI classes that FreeBSD's linuxkpi is missing */
|
||||
#define PCI_VENDOR_ID_NVIDIA 0x10de
|
||||
#define PCI_CLASS_DISPLAY_VGA 0x0300
|
||||
#define PCI_CLASS_DISPLAY_3D 0x0302
|
||||
#define PCI_CLASS_BRIDGE_OTHER 0x0680
|
||||
#endif
|
||||
|
||||
/* Devices supported by RM */
|
||||
struct pci_device_id nv_pci_table[] = {
|
||||
@@ -48,7 +57,7 @@ struct pci_device_id nv_pci_table[] = {
|
||||
};
|
||||
|
||||
/* Devices supported by all drivers in nvidia.ko */
|
||||
struct pci_device_id nv_module_device_table[] = {
|
||||
struct pci_device_id nv_module_device_table[4] = {
|
||||
{
|
||||
.vendor = PCI_VENDOR_ID_NVIDIA,
|
||||
.device = PCI_ANY_ID,
|
||||
@@ -76,4 +85,6 @@ struct pci_device_id nv_module_device_table[] = {
|
||||
{ }
|
||||
};
|
||||
|
||||
#if defined(NV_LINUX)
|
||||
MODULE_DEVICE_TABLE(pci, nv_module_device_table);
|
||||
#endif
|
||||
@@ -27,5 +27,6 @@
|
||||
#include <linux/pci.h>
|
||||
|
||||
extern struct pci_device_id nv_pci_table[];
|
||||
extern struct pci_device_id nv_module_device_table[4];
|
||||
|
||||
#endif /* _NV_PCI_TABLE_H_ */
|
||||
120
kernel-open/nvidia-drm/nv_common_utils.h
Normal file
120
kernel-open/nvidia-drm/nv_common_utils.h
Normal file
@@ -0,0 +1,120 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __NV_COMMON_UTILS_H__
|
||||
#define __NV_COMMON_UTILS_H__
|
||||
|
||||
#include "nvtypes.h"
|
||||
#include "nvmisc.h"
|
||||
|
||||
#if !defined(TRUE)
|
||||
#define TRUE NV_TRUE
|
||||
#endif
|
||||
|
||||
#if !defined(FALSE)
|
||||
#define FALSE NV_FALSE
|
||||
#endif
|
||||
|
||||
#define NV_IS_UNSIGNED(x) ((__typeof__(x))-1 > 0)
|
||||
|
||||
/* Get the length of a statically-sized array. */
|
||||
#define ARRAY_LEN(_arr) (sizeof(_arr) / sizeof(_arr[0]))
|
||||
|
||||
#define NV_INVALID_HEAD 0xFFFFFFFF
|
||||
|
||||
#define NV_INVALID_CONNECTOR_PHYSICAL_INFORMATION (~0)
|
||||
|
||||
#if !defined(NV_MIN)
|
||||
# define NV_MIN(a,b) (((a)<(b))?(a):(b))
|
||||
#endif
|
||||
|
||||
#define NV_MIN3(a,b,c) NV_MIN(NV_MIN(a, b), c)
|
||||
#define NV_MIN4(a,b,c,d) NV_MIN3(NV_MIN(a,b),c,d)
|
||||
|
||||
#if !defined(NV_MAX)
|
||||
# define NV_MAX(a,b) (((a)>(b))?(a):(b))
|
||||
#endif
|
||||
|
||||
#define NV_MAX3(a,b,c) NV_MAX(NV_MAX(a, b), c)
|
||||
#define NV_MAX4(a,b,c,d) NV_MAX3(NV_MAX(a,b),c,d)
|
||||
|
||||
static inline int NV_LIMIT_VAL_TO_MIN_MAX(int val, int min, int max)
|
||||
{
|
||||
if (val < min) {
|
||||
return min;
|
||||
}
|
||||
if (val > max) {
|
||||
return max;
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
#define NV_ROUNDUP_DIV(x,y) ((x) / (y) + (((x) % (y)) ? 1 : 0))
|
||||
|
||||
/*
|
||||
* Macros used for computing palette entries:
|
||||
*
|
||||
* NV_UNDER_REPLICATE(val, source_size, result_size) expands a value
|
||||
* of source_size bits into a value of target_size bits by shifting
|
||||
* the source value into the high bits and replicating the high bits
|
||||
* of the value into the low bits of the result.
|
||||
*
|
||||
* PALETTE_DEPTH_SHIFT(val, w) maps a colormap entry for a component
|
||||
* that has w bits to an appropriate entry in a LUT of 256 entries.
|
||||
*/
|
||||
static inline unsigned int NV_UNDER_REPLICATE(unsigned short val,
|
||||
int source_size,
|
||||
int result_size)
|
||||
{
|
||||
return (val << (result_size - source_size)) |
|
||||
(val >> ((source_size << 1) - result_size));
|
||||
}
|
||||
|
||||
|
||||
static inline unsigned short PALETTE_DEPTH_SHIFT(unsigned short val, int depth)
|
||||
{
|
||||
return NV_UNDER_REPLICATE(val, depth, 8);
|
||||
}
|
||||
|
||||
/*
|
||||
* Use __builtin_ffs where it is supported, or provide an equivalent
|
||||
* implementation for platforms like riscv where it is not.
|
||||
*/
|
||||
#if defined(__GNUC__) && !NVCPU_IS_RISCV64
|
||||
static inline int nv_ffs(int x)
|
||||
{
|
||||
return __builtin_ffs(x);
|
||||
}
|
||||
#else
|
||||
static inline int nv_ffs(int x)
|
||||
{
|
||||
if (x == 0)
|
||||
return 0;
|
||||
|
||||
LOWESTBITIDX_32(x);
|
||||
|
||||
return 1 + x;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __NV_COMMON_UTILS_H__ */
|
||||
@@ -25,8 +25,6 @@
|
||||
|
||||
#include "nvidia-drm-conftest.h"
|
||||
|
||||
#if defined(NV_DRM_FENCE_AVAILABLE)
|
||||
|
||||
/*
|
||||
* linux/reservation.h is renamed to linux/dma-resv.h, by commit
|
||||
* 52791eeec1d9 (dma-buf: rename reservation_object to dma_resv)
|
||||
@@ -39,7 +37,7 @@
|
||||
#include <linux/reservation.h>
|
||||
#endif
|
||||
|
||||
#include <nvidia-dma-fence-helper.h>
|
||||
#include <linux/dma-fence.h>
|
||||
|
||||
#if defined(NV_LINUX_DMA_RESV_H_PRESENT)
|
||||
typedef struct dma_resv nv_dma_resv_t;
|
||||
@@ -108,7 +106,7 @@ static inline int nv_dma_resv_reserve_fences(nv_dma_resv_t *obj,
|
||||
}
|
||||
|
||||
static inline void nv_dma_resv_add_excl_fence(nv_dma_resv_t *obj,
|
||||
nv_dma_fence_t *fence)
|
||||
struct dma_fence *fence)
|
||||
{
|
||||
#if defined(NV_LINUX_DMA_RESV_H_PRESENT)
|
||||
#if defined(NV_DMA_RESV_ADD_FENCE_PRESENT)
|
||||
@@ -121,6 +119,18 @@ static inline void nv_dma_resv_add_excl_fence(nv_dma_resv_t *obj,
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* defined(NV_DRM_FENCE_AVAILABLE) */
|
||||
static inline void nv_dma_resv_add_shared_fence(nv_dma_resv_t *obj,
|
||||
struct dma_fence *fence)
|
||||
{
|
||||
#if defined(NV_LINUX_DMA_RESV_H_PRESENT)
|
||||
#if defined(NV_DMA_RESV_ADD_FENCE_PRESENT)
|
||||
dma_resv_add_fence(obj, fence, DMA_RESV_USAGE_READ);
|
||||
#else
|
||||
dma_resv_add_shared_fence(obj, fence);
|
||||
#endif
|
||||
#else
|
||||
reservation_object_add_shared_fence(obj, fence);
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif /* __NVIDIA_DMA_RESV_HELPER_H__ */
|
||||
204
kernel-open/nvidia-drm/nvidia-drm-conftest.h
Normal file
204
kernel-open/nvidia-drm/nvidia-drm-conftest.h
Normal file
@@ -0,0 +1,204 @@
|
||||
/*
|
||||
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __NVIDIA_DRM_CONFTEST_H__
|
||||
#define __NVIDIA_DRM_CONFTEST_H__
|
||||
|
||||
#include "conftest.h"
|
||||
#include "nvtypes.h"
|
||||
|
||||
/*
|
||||
* NOTE: This file is expected to get included at the top before including any
|
||||
* of linux/drm headers.
|
||||
*
|
||||
* The goal is to redefine refcount_dec_and_test and refcount_inc before
|
||||
* including drm header files, so that the drm macro/inline calls to
|
||||
* refcount_dec_and_test* and refcount_inc get redirected to
|
||||
* alternate implementation in this file.
|
||||
*/
|
||||
|
||||
#if NV_IS_EXPORT_SYMBOL_GPL_refcount_inc
|
||||
|
||||
#include <linux/refcount.h>
|
||||
|
||||
#define refcount_inc(__ptr) \
|
||||
do { \
|
||||
atomic_inc(&(__ptr)->refs); \
|
||||
} while(0)
|
||||
|
||||
#endif
|
||||
|
||||
#if NV_IS_EXPORT_SYMBOL_GPL_refcount_dec_and_test
|
||||
|
||||
#include <linux/refcount.h>
|
||||
|
||||
#define refcount_dec_and_test(__ptr) atomic_dec_and_test(&(__ptr)->refs)
|
||||
|
||||
#endif
|
||||
|
||||
#if defined(NV_DRM_FBDEV_GENERIC_SETUP_PRESENT) && \
|
||||
defined(NV_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PRESENT)
|
||||
#define NV_DRM_FBDEV_AVAILABLE
|
||||
#define NV_DRM_FBDEV_GENERIC_AVAILABLE
|
||||
#endif
|
||||
|
||||
#if defined(NV_DRM_FBDEV_TTM_SETUP_PRESENT) && \
|
||||
defined(NV_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PRESENT)
|
||||
#if IS_ENABLED(CONFIG_DRM_TTM_HELPER)
|
||||
#define NV_DRM_FBDEV_AVAILABLE
|
||||
#define NV_DRM_FBDEV_TTM_AVAILABLE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#if defined(NV_DRM_CLIENT_SETUP_PRESENT) && \
|
||||
(defined(NV_DRM_APERTURE_REMOVE_CONFLICTING_PCI_FRAMEBUFFERS_PRESENT) || \
|
||||
defined(NV_APERTURE_REMOVE_CONFLICTING_PCI_DEVICES_PRESENT))
|
||||
// XXX remove dependency on DRM_TTM_HELPER by implementing nvidia-drm's own
|
||||
// .fbdev_probe callback that uses NVKMS kapi
|
||||
#if IS_ENABLED(CONFIG_DRM_TTM_HELPER)
|
||||
#define NV_DRM_FBDEV_AVAILABLE
|
||||
#define NV_DRM_CLIENT_AVAILABLE
|
||||
#endif
|
||||
#endif
|
||||
|
||||
/*
|
||||
* Adapt to quirks in FreeBSD's Linux kernel compatibility layer.
|
||||
*/
|
||||
#if defined(NV_BSD)
|
||||
|
||||
#include <linux/rwsem.h>
|
||||
#include <sys/param.h>
|
||||
#include <sys/lock.h>
|
||||
#include <sys/sx.h>
|
||||
|
||||
/* For nv_drm_gem_prime_force_fence_signal */
|
||||
#ifndef spin_is_locked
|
||||
#if ((__FreeBSD_version >= 1500000) && (__FreeBSD_version < 1500018)) || (__FreeBSD_version < 1401501)
|
||||
#define spin_is_locked(lock) mtx_owned(lock.m)
|
||||
#else
|
||||
#define spin_is_locked(lock) mtx_owned(lock)
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#ifndef rwsem_is_locked
|
||||
#define rwsem_is_locked(sem) (((sem)->sx.sx_lock & (SX_LOCK_SHARED)) \
|
||||
|| ((sem)->sx.sx_lock & ~(SX_LOCK_FLAGMASK & ~SX_LOCK_SHARED)))
|
||||
#endif
|
||||
|
||||
/*
|
||||
* FreeBSD does not define vm_flags_t in its linuxkpi, since there is already
|
||||
* a FreeBSD vm_flags_t (of a different size) and they don't want the names to
|
||||
* collide. Temporarily redefine it when including nv-mm.h
|
||||
*/
|
||||
#define vm_flags_t unsigned long
|
||||
#include "nv-mm.h"
|
||||
#undef vm_flags_t
|
||||
|
||||
/*
|
||||
* sys/nv.h and nvidia/nv.h have the same header guard
|
||||
* we need to clear it for nvlist_t to get loaded
|
||||
*/
|
||||
#undef _NV_H_
|
||||
#include <sys/nv.h>
|
||||
|
||||
/*
|
||||
* For now just use set_page_dirty as the lock variant
|
||||
* is not ported for FreeBSD. (in progress). This calls
|
||||
* vm_page_dirty. Used in nv-mm.h
|
||||
*/
|
||||
#define set_page_dirty_lock set_page_dirty
|
||||
|
||||
/*
|
||||
* FreeBSD does not implement drm_atomic_state_free, simply
|
||||
* default to drm_atomic_state_put
|
||||
*/
|
||||
#define drm_atomic_state_free drm_atomic_state_put
|
||||
|
||||
#if __FreeBSD_version < 1300000
|
||||
/* redefine LIST_HEAD_INIT to the linux version */
|
||||
#include <linux/list.h>
|
||||
#define LIST_HEAD_INIT(name) LINUX_LIST_HEAD_INIT(name)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* FreeBSD currently has only vmf_insert_pfn_prot defined, and it has a
|
||||
* static assert warning not to use it since all of DRM's usages are in
|
||||
* loops with the vm obj lock(s) held. Instead we should use the lkpi
|
||||
* function itself directly. For us none of this applies so we can just
|
||||
* wrap it in our own definition of vmf_insert_pfn
|
||||
*/
|
||||
#ifndef NV_VMF_INSERT_PFN_PRESENT
|
||||
#define NV_VMF_INSERT_PFN_PRESENT 1
|
||||
|
||||
#if __FreeBSD_version < 1300000
|
||||
#define VM_SHARED (1 << 17)
|
||||
|
||||
/* Not present in 12.2 */
|
||||
static inline vm_fault_t
|
||||
lkpi_vmf_insert_pfn_prot_locked(struct vm_area_struct *vma, unsigned long addr,
|
||||
unsigned long pfn, pgprot_t prot)
|
||||
{
|
||||
vm_object_t vm_obj = vma->vm_obj;
|
||||
vm_page_t page;
|
||||
vm_pindex_t pindex;
|
||||
|
||||
VM_OBJECT_ASSERT_WLOCKED(vm_obj);
|
||||
pindex = OFF_TO_IDX(addr - vma->vm_start);
|
||||
if (vma->vm_pfn_count == 0)
|
||||
vma->vm_pfn_first = pindex;
|
||||
MPASS(pindex <= OFF_TO_IDX(vma->vm_end));
|
||||
|
||||
page = vm_page_grab(vm_obj, pindex, VM_ALLOC_NORMAL);
|
||||
if (page == NULL) {
|
||||
page = PHYS_TO_VM_PAGE(IDX_TO_OFF(pfn));
|
||||
vm_page_xbusy(page);
|
||||
if (vm_page_insert(page, vm_obj, pindex)) {
|
||||
vm_page_xunbusy(page);
|
||||
return (VM_FAULT_OOM);
|
||||
}
|
||||
page->valid = VM_PAGE_BITS_ALL;
|
||||
}
|
||||
pmap_page_set_memattr(page, pgprot2cachemode(prot));
|
||||
vma->vm_pfn_count++;
|
||||
|
||||
return (VM_FAULT_NOPAGE);
|
||||
}
|
||||
#endif
|
||||
|
||||
static inline vm_fault_t
|
||||
vmf_insert_pfn(struct vm_area_struct *vma, unsigned long addr,
|
||||
unsigned long pfn)
|
||||
{
|
||||
vm_fault_t ret;
|
||||
|
||||
VM_OBJECT_WLOCK(vma->vm_obj);
|
||||
ret = lkpi_vmf_insert_pfn_prot_locked(vma, addr, pfn, vma->vm_page_prot);
|
||||
VM_OBJECT_WUNLOCK(vma->vm_obj);
|
||||
|
||||
return (ret);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
#endif /* defined(NV_BSD) */
|
||||
|
||||
#endif /* defined(__NVIDIA_DRM_CONFTEST_H__) */
|
||||
@@ -228,9 +228,6 @@ nv_drm_connector_detect(struct drm_connector *connector, bool force)
|
||||
}
|
||||
|
||||
static struct drm_connector_funcs nv_connector_funcs = {
|
||||
#if defined NV_DRM_ATOMIC_HELPER_CONNECTOR_DPMS_PRESENT
|
||||
.dpms = drm_atomic_helper_connector_dpms,
|
||||
#endif
|
||||
.destroy = nv_drm_connector_destroy,
|
||||
.reset = drm_atomic_helper_connector_reset,
|
||||
.force = __nv_drm_connector_force,
|
||||
@@ -314,7 +311,11 @@ static int nv_drm_connector_get_modes(struct drm_connector *connector)
|
||||
}
|
||||
|
||||
static int nv_drm_connector_mode_valid(struct drm_connector *connector,
|
||||
#if defined(NV_DRM_CONNECTOR_HELPER_FUNCS_MODE_VALID_HAS_CONST_MODE_ARG)
|
||||
const struct drm_display_mode *mode)
|
||||
#else
|
||||
struct drm_display_mode *mode)
|
||||
#endif
|
||||
{
|
||||
struct drm_device *dev = connector->dev;
|
||||
struct nv_drm_device *nv_dev = to_nv_device(dev);
|
||||
@@ -349,10 +350,125 @@ nv_drm_connector_best_encoder(struct drm_connector *connector)
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#if defined(NV_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_HAS_SUPPORTED_COLORSPACES_ARG)
|
||||
static const NvU32 __nv_drm_connector_supported_colorspaces =
|
||||
BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
|
||||
BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
|
||||
#endif
|
||||
|
||||
#if defined(NV_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY_PRESENT)
|
||||
static int
|
||||
__nv_drm_connector_atomic_check(struct drm_connector *connector,
|
||||
struct drm_atomic_state *state)
|
||||
{
|
||||
struct drm_connector_state *new_connector_state =
|
||||
drm_atomic_get_new_connector_state(state, connector);
|
||||
struct drm_connector_state *old_connector_state =
|
||||
drm_atomic_get_old_connector_state(state, connector);
|
||||
struct nv_drm_device *nv_dev = to_nv_device(connector->dev);
|
||||
|
||||
struct drm_crtc *crtc = new_connector_state->crtc;
|
||||
struct drm_crtc_state *crtc_state;
|
||||
struct nv_drm_crtc_state *nv_crtc_state;
|
||||
struct NvKmsKapiHeadRequestedConfig *req_config;
|
||||
|
||||
if (!crtc) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
|
||||
nv_crtc_state = to_nv_crtc_state(crtc_state);
|
||||
req_config = &nv_crtc_state->req_config;
|
||||
|
||||
/*
|
||||
* Override metadata for the entire head instead of allowing NVKMS to derive
|
||||
* it from the layers' metadata.
|
||||
*
|
||||
* This is the metadata that will sent to the display, and if applicable,
|
||||
* layers will be tone mapped to this metadata rather than that of the
|
||||
* display.
|
||||
*/
|
||||
req_config->flags.hdrInfoFrameChanged =
|
||||
!drm_connector_atomic_hdr_metadata_equal(old_connector_state,
|
||||
new_connector_state);
|
||||
if (new_connector_state->hdr_output_metadata &&
|
||||
new_connector_state->hdr_output_metadata->data) {
|
||||
|
||||
/*
|
||||
* Note that HDMI definitions are used here even though we might not
|
||||
* be using HDMI. While that seems odd, it is consistent with
|
||||
* upstream behavior.
|
||||
*/
|
||||
|
||||
struct hdr_output_metadata *hdr_metadata =
|
||||
new_connector_state->hdr_output_metadata->data;
|
||||
struct hdr_metadata_infoframe *info_frame =
|
||||
&hdr_metadata->hdmi_metadata_type1;
|
||||
unsigned int i;
|
||||
|
||||
if (hdr_metadata->metadata_type != HDMI_STATIC_METADATA_TYPE1) {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(info_frame->display_primaries); i++) {
|
||||
req_config->modeSetConfig.hdrInfoFrame.staticMetadata.displayPrimaries[i].x =
|
||||
info_frame->display_primaries[i].x;
|
||||
req_config->modeSetConfig.hdrInfoFrame.staticMetadata.displayPrimaries[i].y =
|
||||
info_frame->display_primaries[i].y;
|
||||
}
|
||||
|
||||
req_config->modeSetConfig.hdrInfoFrame.staticMetadata.whitePoint.x =
|
||||
info_frame->white_point.x;
|
||||
req_config->modeSetConfig.hdrInfoFrame.staticMetadata.whitePoint.y =
|
||||
info_frame->white_point.y;
|
||||
req_config->modeSetConfig.hdrInfoFrame.staticMetadata.maxDisplayMasteringLuminance =
|
||||
info_frame->max_display_mastering_luminance;
|
||||
req_config->modeSetConfig.hdrInfoFrame.staticMetadata.minDisplayMasteringLuminance =
|
||||
info_frame->min_display_mastering_luminance;
|
||||
req_config->modeSetConfig.hdrInfoFrame.staticMetadata.maxCLL =
|
||||
info_frame->max_cll;
|
||||
req_config->modeSetConfig.hdrInfoFrame.staticMetadata.maxFALL =
|
||||
info_frame->max_fall;
|
||||
|
||||
req_config->modeSetConfig.hdrInfoFrame.eotf = info_frame->eotf;
|
||||
|
||||
req_config->modeSetConfig.hdrInfoFrame.enabled = NV_TRUE;
|
||||
} else {
|
||||
req_config->modeSetConfig.hdrInfoFrame.enabled = NV_FALSE;
|
||||
}
|
||||
|
||||
req_config->flags.colorimetryChanged =
|
||||
(old_connector_state->colorspace != new_connector_state->colorspace);
|
||||
// When adding a case here, also add to __nv_drm_connector_supported_colorspaces
|
||||
switch (new_connector_state->colorspace) {
|
||||
case DRM_MODE_COLORIMETRY_DEFAULT:
|
||||
req_config->modeSetConfig.colorimetry =
|
||||
NVKMS_OUTPUT_COLORIMETRY_DEFAULT;
|
||||
break;
|
||||
case DRM_MODE_COLORIMETRY_BT2020_RGB:
|
||||
case DRM_MODE_COLORIMETRY_BT2020_YCC:
|
||||
// Ignore RGB/YCC
|
||||
// See https://patchwork.freedesktop.org/patch/525496/?series=111865&rev=4
|
||||
req_config->modeSetConfig.colorimetry =
|
||||
NVKMS_OUTPUT_COLORIMETRY_BT2100;
|
||||
break;
|
||||
default:
|
||||
// XXX HDR TODO: Add support for more color spaces
|
||||
NV_DRM_DEV_LOG_ERR(nv_dev, "Unsupported color space");
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif /* defined(NV_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY_PRESENT) */
|
||||
|
||||
static const struct drm_connector_helper_funcs nv_connector_helper_funcs = {
|
||||
.get_modes = nv_drm_connector_get_modes,
|
||||
.mode_valid = nv_drm_connector_mode_valid,
|
||||
.best_encoder = nv_drm_connector_best_encoder,
|
||||
#if defined(NV_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY_PRESENT)
|
||||
.atomic_check = __nv_drm_connector_atomic_check,
|
||||
#endif
|
||||
};
|
||||
|
||||
static struct drm_connector*
|
||||
@@ -405,6 +521,32 @@ nv_drm_connector_new(struct drm_device *dev,
|
||||
DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
|
||||
}
|
||||
|
||||
#if defined(NV_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY_PRESENT)
|
||||
if (nv_connector->type == NVKMS_CONNECTOR_TYPE_HDMI) {
|
||||
#if defined(NV_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_HAS_SUPPORTED_COLORSPACES_ARG)
|
||||
if (drm_mode_create_hdmi_colorspace_property(
|
||||
&nv_connector->base,
|
||||
__nv_drm_connector_supported_colorspaces) == 0) {
|
||||
#else
|
||||
if (drm_mode_create_hdmi_colorspace_property(&nv_connector->base) == 0) {
|
||||
#endif
|
||||
drm_connector_attach_colorspace_property(&nv_connector->base);
|
||||
}
|
||||
drm_connector_attach_hdr_output_metadata_property(&nv_connector->base);
|
||||
} else if (nv_connector->type == NVKMS_CONNECTOR_TYPE_DP) {
|
||||
#if defined(NV_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_HAS_SUPPORTED_COLORSPACES_ARG)
|
||||
if (drm_mode_create_dp_colorspace_property(
|
||||
&nv_connector->base,
|
||||
__nv_drm_connector_supported_colorspaces) == 0) {
|
||||
#else
|
||||
if (drm_mode_create_dp_colorspace_property(&nv_connector->base) == 0) {
|
||||
#endif
|
||||
drm_connector_attach_colorspace_property(&nv_connector->base);
|
||||
}
|
||||
drm_connector_attach_hdr_output_metadata_property(&nv_connector->base);
|
||||
}
|
||||
#endif /* defined(NV_DRM_CONNECTOR_ATTACH_HDR_OUTPUT_METADATA_PROPERTY_PRESENT) */
|
||||
|
||||
/* Register connector with DRM subsystem */
|
||||
|
||||
ret = drm_connector_register(&nv_connector->base);
|
||||
@@ -443,16 +585,11 @@ nv_drm_get_connector(struct drm_device *dev,
|
||||
char dpAddress[NVKMS_DP_ADDRESS_STRING_LENGTH])
|
||||
{
|
||||
struct drm_connector *connector = NULL;
|
||||
#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT)
|
||||
struct drm_connector_list_iter conn_iter;
|
||||
nv_drm_connector_list_iter_begin(dev, &conn_iter);
|
||||
#else
|
||||
struct drm_mode_config *config = &dev->mode_config;
|
||||
mutex_lock(&config->mutex);
|
||||
#endif
|
||||
drm_connector_list_iter_begin(dev, &conn_iter);
|
||||
|
||||
/* Lookup for existing connector with same physical index */
|
||||
nv_drm_for_each_connector(connector, &conn_iter, dev) {
|
||||
drm_for_each_connector_iter(connector, &conn_iter) {
|
||||
struct nv_drm_connector *nv_connector = to_nv_connector(connector);
|
||||
|
||||
if (nv_connector->physicalIndex == physicalIndex) {
|
||||
@@ -467,11 +604,7 @@ nv_drm_get_connector(struct drm_device *dev,
|
||||
connector = NULL;
|
||||
|
||||
done:
|
||||
#if defined(NV_DRM_CONNECTOR_LIST_ITER_PRESENT)
|
||||
nv_drm_connector_list_iter_end(&conn_iter);
|
||||
#else
|
||||
mutex_unlock(&config->mutex);
|
||||
#endif
|
||||
drm_connector_list_iter_end(&conn_iter);
|
||||
|
||||
if (!connector) {
|
||||
connector = nv_drm_connector_new(dev,
|
||||
@@ -31,9 +31,7 @@
|
||||
#include <drm/drmP.h>
|
||||
#endif
|
||||
|
||||
#if defined(NV_DRM_DRM_CONNECTOR_H_PRESENT)
|
||||
#include <drm/drm_connector.h>
|
||||
#endif
|
||||
|
||||
#include "nvtypes.h"
|
||||
#include "nvkms-api-types.h"
|
||||
3140
kernel-open/nvidia-drm/nvidia-drm-crtc.c
Normal file
3140
kernel-open/nvidia-drm/nvidia-drm-crtc.c
Normal file
File diff suppressed because it is too large
Load Diff
@@ -38,6 +38,13 @@
|
||||
#include "nvtypes.h"
|
||||
#include "nvkms-kapi.h"
|
||||
|
||||
enum nv_drm_transfer_function {
|
||||
NV_DRM_TRANSFER_FUNCTION_DEFAULT,
|
||||
NV_DRM_TRANSFER_FUNCTION_LINEAR,
|
||||
NV_DRM_TRANSFER_FUNCTION_PQ,
|
||||
NV_DRM_TRANSFER_FUNCTION_MAX,
|
||||
};
|
||||
|
||||
struct nv_drm_crtc {
|
||||
NvU32 head;
|
||||
|
||||
@@ -63,6 +70,8 @@ struct nv_drm_crtc {
|
||||
*/
|
||||
struct drm_file *modeset_permission_filep;
|
||||
|
||||
struct NvKmsLUTCaps olut_caps;
|
||||
|
||||
struct drm_crtc base;
|
||||
};
|
||||
|
||||
@@ -142,6 +151,12 @@ struct nv_drm_crtc_state {
|
||||
* nv_drm_atomic_crtc_destroy_state().
|
||||
*/
|
||||
struct nv_drm_flip *nv_flip;
|
||||
|
||||
enum nv_drm_transfer_function regamma_tf;
|
||||
struct drm_property_blob *regamma_lut;
|
||||
uint64_t regamma_divisor;
|
||||
struct nv_drm_lut_surface *regamma_drm_lut_surface;
|
||||
NvBool regamma_changed;
|
||||
};
|
||||
|
||||
static inline struct nv_drm_crtc_state *to_nv_crtc_state(struct drm_crtc_state *state)
|
||||
@@ -149,6 +164,11 @@ static inline struct nv_drm_crtc_state *to_nv_crtc_state(struct drm_crtc_state *
|
||||
return container_of(state, struct nv_drm_crtc_state, base);
|
||||
}
|
||||
|
||||
static inline const struct nv_drm_crtc_state *to_nv_crtc_state_const(const struct drm_crtc_state *state)
|
||||
{
|
||||
return container_of(state, struct nv_drm_crtc_state, base);
|
||||
}
|
||||
|
||||
struct nv_drm_plane {
|
||||
/**
|
||||
* @base:
|
||||
@@ -170,6 +190,16 @@ struct nv_drm_plane {
|
||||
* Index of this plane in the per head array of layers.
|
||||
*/
|
||||
uint32_t layer_idx;
|
||||
|
||||
/**
|
||||
* @supportsColorProperties
|
||||
*
|
||||
* If true, supports the COLOR_ENCODING and COLOR_RANGE properties.
|
||||
*/
|
||||
bool supportsColorProperties;
|
||||
|
||||
struct NvKmsLUTCaps ilut_caps;
|
||||
struct NvKmsLUTCaps tmo_caps;
|
||||
};
|
||||
|
||||
static inline struct nv_drm_plane *to_nv_plane(struct drm_plane *plane)
|
||||
@@ -180,13 +210,54 @@ static inline struct nv_drm_plane *to_nv_plane(struct drm_plane *plane)
|
||||
return container_of(plane, struct nv_drm_plane, base);
|
||||
}
|
||||
|
||||
struct nv_drm_nvkms_surface {
|
||||
struct NvKmsKapiDevice *pDevice;
|
||||
struct NvKmsKapiMemory *nvkms_memory;
|
||||
struct NvKmsKapiSurface *nvkms_surface;
|
||||
void *buffer;
|
||||
struct kref refcount;
|
||||
};
|
||||
|
||||
struct nv_drm_nvkms_surface_params {
|
||||
NvU32 width;
|
||||
NvU32 height;
|
||||
size_t surface_size;
|
||||
enum NvKmsSurfaceMemoryFormat format;
|
||||
};
|
||||
|
||||
struct nv_drm_lut_surface {
|
||||
struct nv_drm_nvkms_surface base;
|
||||
struct {
|
||||
NvU32 vssSegments;
|
||||
enum NvKmsLUTVssType vssType;
|
||||
|
||||
NvU32 lutEntries;
|
||||
enum NvKmsLUTFormat entryFormat;
|
||||
|
||||
} properties;
|
||||
};
|
||||
|
||||
struct nv_drm_plane_state {
|
||||
struct drm_plane_state base;
|
||||
s32 __user *fd_user_ptr;
|
||||
enum NvKmsInputColorSpace input_colorspace;
|
||||
enum nv_drm_input_color_space input_colorspace;
|
||||
#if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA)
|
||||
struct drm_property_blob *hdr_output_metadata;
|
||||
#endif
|
||||
struct drm_property_blob *lms_ctm;
|
||||
struct drm_property_blob *lms_to_itp_ctm;
|
||||
struct drm_property_blob *itp_to_lms_ctm;
|
||||
struct drm_property_blob *blend_ctm;
|
||||
|
||||
enum nv_drm_transfer_function degamma_tf;
|
||||
struct drm_property_blob *degamma_lut;
|
||||
uint64_t degamma_multiplier; /* S31.32 Sign-Magnitude Format */
|
||||
struct nv_drm_lut_surface *degamma_drm_lut_surface;
|
||||
NvBool degamma_changed;
|
||||
|
||||
struct drm_property_blob *tmo_lut;
|
||||
struct nv_drm_lut_surface *tmo_drm_lut_surface;
|
||||
NvBool tmo_changed;
|
||||
};
|
||||
|
||||
static inline struct nv_drm_plane_state *to_nv_drm_plane_state(struct drm_plane_state *state)
|
||||
File diff suppressed because it is too large
Load Diff
@@ -27,10 +27,19 @@
|
||||
|
||||
#if defined(NV_DRM_AVAILABLE)
|
||||
|
||||
struct NvKmsKapiGpuInfo;
|
||||
|
||||
int nv_drm_probe_devices(void);
|
||||
|
||||
void nv_drm_remove(NvU32 gpuId);
|
||||
void nv_drm_remove_devices(void);
|
||||
|
||||
void nv_drm_suspend_resume(NvBool suspend);
|
||||
|
||||
void nv_drm_register_drm_device(const struct NvKmsKapiGpuInfo *);
|
||||
|
||||
void nv_drm_update_drm_driver_features(void);
|
||||
|
||||
#endif /* defined(NV_DRM_AVAILABLE) */
|
||||
|
||||
#endif /* __NVIDIA_DRM_DRV_H__ */
|
||||
@@ -139,12 +139,8 @@ nv_drm_encoder_new(struct drm_device *dev,
|
||||
|
||||
ret = drm_encoder_init(dev,
|
||||
&nv_encoder->base, &nv_encoder_funcs,
|
||||
nvkms_connector_signal_to_drm_encoder_signal(format)
|
||||
#if defined(NV_DRM_ENCODER_INIT_HAS_NAME_ARG)
|
||||
, NULL
|
||||
#endif
|
||||
);
|
||||
|
||||
nvkms_connector_signal_to_drm_encoder_signal(format),
|
||||
NULL);
|
||||
if (ret != 0) {
|
||||
nv_drm_free(nv_encoder);
|
||||
|
||||
@@ -300,7 +296,7 @@ void nv_drm_handle_display_change(struct nv_drm_device *nv_dev,
|
||||
|
||||
nv_drm_connector_mark_connection_status_dirty(nv_encoder->nv_connector);
|
||||
|
||||
drm_kms_helper_hotplug_event(dev);
|
||||
schedule_delayed_work(&nv_dev->hotplug_event_work, 0);
|
||||
}
|
||||
|
||||
void nv_drm_handle_dynamic_display_connected(struct nv_drm_device *nv_dev,
|
||||
@@ -319,7 +315,7 @@ void nv_drm_handle_dynamic_display_connected(struct nv_drm_device *nv_dev,
|
||||
nv_encoder = get_nv_encoder_from_nvkms_display(dev, hDisplay);
|
||||
|
||||
if (nv_encoder != NULL) {
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
NV_DRM_DEV_LOG_INFO(
|
||||
nv_dev,
|
||||
"Encoder with NvKmsKapiDisplay 0x%08x already exists.",
|
||||
hDisplay);
|
||||
@@ -336,17 +332,6 @@ void nv_drm_handle_dynamic_display_connected(struct nv_drm_device *nv_dev,
|
||||
return;
|
||||
}
|
||||
|
||||
/*
|
||||
* On some kernels, DRM has the notion of a "primary group" that
|
||||
* tracks the global mode setting state for the device.
|
||||
*
|
||||
* On kernels where DRM has a primary group, we need to reinitialize
|
||||
* after adding encoders and connectors.
|
||||
*/
|
||||
#if defined(NV_DRM_REINIT_PRIMARY_MODE_GROUP_PRESENT)
|
||||
drm_reinit_primary_mode_group(dev);
|
||||
#endif
|
||||
|
||||
drm_kms_helper_hotplug_event(dev);
|
||||
schedule_delayed_work(&nv_dev->hotplug_event_work, 0);
|
||||
}
|
||||
#endif
|
||||
@@ -29,11 +29,7 @@
|
||||
|
||||
#include "nvidia-drm-priv.h"
|
||||
|
||||
#if defined(NV_DRM_DRM_ENCODER_H_PRESENT)
|
||||
#include <drm/drm_encoder.h>
|
||||
#else
|
||||
#include <drm/drmP.h>
|
||||
#endif
|
||||
|
||||
#include "nvkms-kapi.h"
|
||||
|
||||
@@ -36,12 +36,15 @@
|
||||
|
||||
static void __nv_drm_framebuffer_free(struct nv_drm_framebuffer *nv_fb)
|
||||
{
|
||||
struct drm_framebuffer *fb = &nv_fb->base;
|
||||
uint32_t i;
|
||||
|
||||
/* Unreference gem object */
|
||||
for (i = 0; i < ARRAY_SIZE(nv_fb->nv_gem); i++) {
|
||||
if (nv_fb->nv_gem[i] != NULL) {
|
||||
nv_drm_gem_object_unreference_unlocked(nv_fb->nv_gem[i]);
|
||||
for (i = 0; i < NVKMS_MAX_PLANES_PER_SURFACE; i++) {
|
||||
struct drm_gem_object *gem = fb->obj[i];
|
||||
if (gem != NULL) {
|
||||
struct nv_drm_gem_object *nv_gem = to_nv_gem_object(gem);
|
||||
nv_drm_gem_object_unreference_unlocked(nv_gem);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -69,10 +72,8 @@ static int
|
||||
nv_drm_framebuffer_create_handle(struct drm_framebuffer *fb,
|
||||
struct drm_file *file, unsigned int *handle)
|
||||
{
|
||||
struct nv_drm_framebuffer *nv_fb = to_nv_framebuffer(fb);
|
||||
|
||||
return nv_drm_gem_handle_create(file,
|
||||
nv_fb->nv_gem[0],
|
||||
to_nv_gem_object(fb->obj[0]),
|
||||
handle);
|
||||
}
|
||||
|
||||
@@ -82,12 +83,12 @@ static struct drm_framebuffer_funcs nv_framebuffer_funcs = {
|
||||
};
|
||||
|
||||
static struct nv_drm_framebuffer *nv_drm_framebuffer_alloc(
|
||||
struct drm_device *dev,
|
||||
struct nv_drm_device *nv_dev,
|
||||
struct drm_file *file,
|
||||
struct drm_mode_fb_cmd2 *cmd)
|
||||
const struct drm_mode_fb_cmd2 *cmd)
|
||||
{
|
||||
struct nv_drm_device *nv_dev = to_nv_device(dev);
|
||||
struct nv_drm_framebuffer *nv_fb;
|
||||
struct nv_drm_gem_object *nv_gem;
|
||||
const int num_planes = nv_drm_format_num_planes(cmd->pixel_format);
|
||||
uint32_t i;
|
||||
|
||||
@@ -101,21 +102,22 @@ static struct nv_drm_framebuffer *nv_drm_framebuffer_alloc(
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
if (num_planes > ARRAY_SIZE(nv_fb->nv_gem)) {
|
||||
if (num_planes > NVKMS_MAX_PLANES_PER_SURFACE) {
|
||||
NV_DRM_DEV_DEBUG_DRIVER(nv_dev, "Unsupported number of planes");
|
||||
goto failed;
|
||||
}
|
||||
|
||||
for (i = 0; i < num_planes; i++) {
|
||||
if ((nv_fb->nv_gem[i] = nv_drm_gem_object_lookup(
|
||||
dev,
|
||||
file,
|
||||
cmd->handles[i])) == NULL) {
|
||||
nv_gem = nv_drm_gem_object_lookup(file, cmd->handles[i]);
|
||||
|
||||
if (nv_gem == NULL) {
|
||||
NV_DRM_DEV_DEBUG_DRIVER(
|
||||
nv_dev,
|
||||
"Failed to find gem object of type nvkms memory");
|
||||
goto failed;
|
||||
}
|
||||
|
||||
nv_fb->base.obj[i] = &nv_gem->base;
|
||||
}
|
||||
|
||||
return nv_fb;
|
||||
@@ -135,12 +137,14 @@ static int nv_drm_framebuffer_init(struct drm_device *dev,
|
||||
{
|
||||
struct nv_drm_device *nv_dev = to_nv_device(dev);
|
||||
struct NvKmsKapiCreateSurfaceParams params = { };
|
||||
struct nv_drm_gem_object *nv_gem;
|
||||
struct drm_framebuffer *fb = &nv_fb->base;
|
||||
uint32_t i;
|
||||
int ret;
|
||||
|
||||
/* Initialize the base framebuffer object and add it to drm subsystem */
|
||||
|
||||
ret = drm_framebuffer_init(dev, &nv_fb->base, &nv_framebuffer_funcs);
|
||||
ret = drm_framebuffer_init(dev, fb, &nv_framebuffer_funcs);
|
||||
if (ret != 0) {
|
||||
NV_DRM_DEV_DEBUG_DRIVER(
|
||||
nv_dev,
|
||||
@@ -148,23 +152,18 @@ static int nv_drm_framebuffer_init(struct drm_device *dev,
|
||||
return ret;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(nv_fb->nv_gem); i++) {
|
||||
if (nv_fb->nv_gem[i] != NULL) {
|
||||
if (!nvKms->isMemoryValidForDisplay(nv_dev->pDevice,
|
||||
nv_fb->nv_gem[i]->pMemory)) {
|
||||
NV_DRM_DEV_LOG_INFO(
|
||||
nv_dev,
|
||||
"Framebuffer memory not appropriate for scanout");
|
||||
goto fail;
|
||||
}
|
||||
for (i = 0; i < NVKMS_MAX_PLANES_PER_SURFACE; i++) {
|
||||
struct drm_gem_object *gem = fb->obj[i];
|
||||
if (gem != NULL) {
|
||||
nv_gem = to_nv_gem_object(gem);
|
||||
|
||||
params.planes[i].memory = nv_fb->nv_gem[i]->pMemory;
|
||||
params.planes[i].offset = nv_fb->base.offsets[i];
|
||||
params.planes[i].pitch = nv_fb->base.pitches[i];
|
||||
params.planes[i].memory = nv_gem->pMemory;
|
||||
params.planes[i].offset = fb->offsets[i];
|
||||
params.planes[i].pitch = fb->pitches[i];
|
||||
}
|
||||
}
|
||||
params.height = nv_fb->base.height;
|
||||
params.width = nv_fb->base.width;
|
||||
params.height = fb->height;
|
||||
params.width = fb->width;
|
||||
params.format = format;
|
||||
|
||||
if (have_modifier) {
|
||||
@@ -188,6 +187,43 @@ static int nv_drm_framebuffer_init(struct drm_device *dev,
|
||||
params.explicit_layout = false;
|
||||
}
|
||||
|
||||
/*
|
||||
* XXX work around an invalid pitch assumption in DRM.
|
||||
*
|
||||
* The smallest pitch the display hardware allows is 256.
|
||||
*
|
||||
* If a DRM client allocates a 32x32 cursor surface through
|
||||
* DRM_IOCTL_MODE_CREATE_DUMB, we'll correctly round the pitch to 256:
|
||||
*
|
||||
* pitch = round(32width * 4Bpp, 256) = 256
|
||||
*
|
||||
* and then allocate an 8k surface:
|
||||
*
|
||||
* size = pitch * 32height = 8196
|
||||
*
|
||||
* and report the rounded pitch and size back to the client through the
|
||||
* struct drm_mode_create_dumb ioctl params.
|
||||
*
|
||||
* But when the DRM client passes that buffer object handle to
|
||||
* DRM_IOCTL_MODE_CURSOR, the client has no way to specify the pitch. This
|
||||
* path in drm:
|
||||
*
|
||||
* DRM_IOCTL_MODE_CURSOR
|
||||
* drm_mode_cursor_ioctl()
|
||||
* drm_mode_cursor_common()
|
||||
* drm_mode_cursor_universal()
|
||||
*
|
||||
* will implicitly create a framebuffer from the buffer object, and compute
|
||||
* the pitch as width x 32 (without aligning to our minimum pitch).
|
||||
*
|
||||
* Intercept this case and force the pitch back to 256.
|
||||
*/
|
||||
if ((params.width == 32) &&
|
||||
(params.height == 32) &&
|
||||
(params.planes[0].pitch == 128)) {
|
||||
params.planes[0].pitch = 256;
|
||||
}
|
||||
|
||||
/* Create NvKmsKapiSurface */
|
||||
|
||||
nv_fb->pSurface = nvKms->createSurface(nv_dev->pDevice, ¶ms);
|
||||
@@ -199,23 +235,21 @@ static int nv_drm_framebuffer_init(struct drm_device *dev,
|
||||
return 0;
|
||||
|
||||
fail:
|
||||
drm_framebuffer_cleanup(&nv_fb->base);
|
||||
drm_framebuffer_cleanup(fb);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
struct drm_framebuffer *nv_drm_internal_framebuffer_create(
|
||||
struct drm_framebuffer *nv_drm_framebuffer_create(
|
||||
struct drm_device *dev,
|
||||
struct drm_file *file,
|
||||
struct drm_mode_fb_cmd2 *cmd)
|
||||
const struct drm_mode_fb_cmd2 *cmd)
|
||||
{
|
||||
struct nv_drm_device *nv_dev = to_nv_device(dev);
|
||||
struct nv_drm_framebuffer *nv_fb;
|
||||
uint64_t modifier = 0;
|
||||
int ret;
|
||||
enum NvKmsSurfaceMemoryFormat format;
|
||||
#if defined(NV_DRM_FORMAT_MODIFIERS_PRESENT)
|
||||
int i;
|
||||
#endif
|
||||
bool have_modifier = false;
|
||||
|
||||
/* Check whether NvKms supports the given pixel format */
|
||||
@@ -226,7 +260,6 @@ struct drm_framebuffer *nv_drm_internal_framebuffer_create(
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
|
||||
#if defined(NV_DRM_FORMAT_MODIFIERS_PRESENT)
|
||||
if (cmd->flags & DRM_MODE_FB_MODIFIERS) {
|
||||
have_modifier = true;
|
||||
modifier = cmd->modifier[0];
|
||||
@@ -240,14 +273,13 @@ struct drm_framebuffer *nv_drm_internal_framebuffer_create(
|
||||
if (nv_dev->modifiers[i] == DRM_FORMAT_MOD_INVALID) {
|
||||
NV_DRM_DEV_DEBUG_DRIVER(
|
||||
nv_dev,
|
||||
"Invalid format modifier for framebuffer object: 0x%016llx",
|
||||
"Invalid format modifier for framebuffer object: 0x%016" NvU64_fmtx,
|
||||
modifier);
|
||||
return ERR_PTR(-EINVAL);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
nv_fb = nv_drm_framebuffer_alloc(dev, file, cmd);
|
||||
nv_fb = nv_drm_framebuffer_alloc(nv_dev, file, cmd);
|
||||
if (IS_ERR(nv_fb)) {
|
||||
return (struct drm_framebuffer *)nv_fb;
|
||||
}
|
||||
@@ -255,9 +287,7 @@ struct drm_framebuffer *nv_drm_internal_framebuffer_create(
|
||||
/* Fill out framebuffer metadata from the userspace fb creation request */
|
||||
|
||||
drm_helper_mode_fill_fb_struct(
|
||||
#if defined(NV_DRM_HELPER_MODE_FILL_FB_STRUCT_HAS_DEV_ARG)
|
||||
dev,
|
||||
#endif
|
||||
&nv_fb->base,
|
||||
cmd);
|
||||
|
||||
@@ -31,19 +31,13 @@
|
||||
#include <drm/drmP.h>
|
||||
#endif
|
||||
|
||||
#if defined(NV_DRM_DRM_FRAMEBUFFER_H_PRESENT)
|
||||
#include <drm/drm_framebuffer.h>
|
||||
#endif
|
||||
|
||||
#include "nvidia-drm-gem-nvkms-memory.h"
|
||||
#include "nvkms-kapi.h"
|
||||
|
||||
struct nv_drm_framebuffer {
|
||||
struct NvKmsKapiSurface *pSurface;
|
||||
|
||||
struct nv_drm_gem_object*
|
||||
nv_gem[NVKMS_MAX_PLANES_PER_SURFACE];
|
||||
|
||||
struct drm_framebuffer base;
|
||||
};
|
||||
|
||||
@@ -56,10 +50,10 @@ static inline struct nv_drm_framebuffer *to_nv_framebuffer(
|
||||
return container_of(fb, struct nv_drm_framebuffer, base);
|
||||
}
|
||||
|
||||
struct drm_framebuffer *nv_drm_internal_framebuffer_create(
|
||||
struct drm_framebuffer *nv_drm_framebuffer_create(
|
||||
struct drm_device *dev,
|
||||
struct drm_file *file,
|
||||
struct drm_mode_fb_cmd2 *cmd);
|
||||
const struct drm_mode_fb_cmd2 *cmd);
|
||||
|
||||
#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2016-2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -34,9 +34,7 @@
|
||||
#include "nvidia-drm-fence.h"
|
||||
#include "nvidia-dma-resv-helper.h"
|
||||
|
||||
#if defined(NV_DRM_FENCE_AVAILABLE)
|
||||
|
||||
#include "nvidia-dma-fence-helper.h"
|
||||
#include <linux/dma-fence.h>
|
||||
|
||||
#define NV_DRM_SEMAPHORE_SURFACE_FENCE_MAX_TIMEOUT_MS 5000
|
||||
|
||||
@@ -83,42 +81,42 @@ struct nv_drm_prime_fence_context {
|
||||
|
||||
struct nv_drm_prime_fence {
|
||||
struct list_head list_entry;
|
||||
nv_dma_fence_t base;
|
||||
struct dma_fence base;
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
static inline
|
||||
struct nv_drm_prime_fence *to_nv_drm_prime_fence(nv_dma_fence_t *fence)
|
||||
struct nv_drm_prime_fence *to_nv_drm_prime_fence(struct dma_fence *fence)
|
||||
{
|
||||
return container_of(fence, struct nv_drm_prime_fence, base);
|
||||
}
|
||||
|
||||
static const char*
|
||||
nv_drm_gem_fence_op_get_driver_name(nv_dma_fence_t *fence)
|
||||
nv_drm_gem_fence_op_get_driver_name(struct dma_fence *fence)
|
||||
{
|
||||
return "NVIDIA";
|
||||
}
|
||||
|
||||
static const char*
|
||||
nv_drm_gem_prime_fence_op_get_timeline_name(nv_dma_fence_t *fence)
|
||||
nv_drm_gem_prime_fence_op_get_timeline_name(struct dma_fence *fence)
|
||||
{
|
||||
return "nvidia.prime";
|
||||
}
|
||||
|
||||
static bool nv_drm_gem_prime_fence_op_enable_signaling(nv_dma_fence_t *fence)
|
||||
static bool nv_drm_gem_prime_fence_op_enable_signaling(struct dma_fence *fence)
|
||||
{
|
||||
// DO NOTHING
|
||||
return true;
|
||||
}
|
||||
|
||||
static void nv_drm_gem_prime_fence_op_release(nv_dma_fence_t *fence)
|
||||
static void nv_drm_gem_prime_fence_op_release(struct dma_fence *fence)
|
||||
{
|
||||
struct nv_drm_prime_fence *nv_fence = to_nv_drm_prime_fence(fence);
|
||||
nv_drm_free(nv_fence);
|
||||
}
|
||||
|
||||
static signed long
|
||||
nv_drm_gem_prime_fence_op_wait(nv_dma_fence_t *fence,
|
||||
nv_drm_gem_prime_fence_op_wait(struct dma_fence *fence,
|
||||
bool intr, signed long timeout)
|
||||
{
|
||||
/*
|
||||
@@ -131,12 +129,12 @@ nv_drm_gem_prime_fence_op_wait(nv_dma_fence_t *fence,
|
||||
* that it should never get hit during normal operation, but not so long
|
||||
* that the system becomes unresponsive.
|
||||
*/
|
||||
return nv_dma_fence_default_wait(fence, intr,
|
||||
return dma_fence_default_wait(fence, intr,
|
||||
(timeout == MAX_SCHEDULE_TIMEOUT) ?
|
||||
msecs_to_jiffies(96) : timeout);
|
||||
}
|
||||
|
||||
static const nv_dma_fence_ops_t nv_drm_gem_prime_fence_ops = {
|
||||
static const struct dma_fence_ops nv_drm_gem_prime_fence_ops = {
|
||||
.get_driver_name = nv_drm_gem_fence_op_get_driver_name,
|
||||
.get_timeline_name = nv_drm_gem_prime_fence_op_get_timeline_name,
|
||||
.enable_signaling = nv_drm_gem_prime_fence_op_enable_signaling,
|
||||
@@ -148,8 +146,8 @@ static inline void
|
||||
__nv_drm_prime_fence_signal(struct nv_drm_prime_fence *nv_fence)
|
||||
{
|
||||
list_del(&nv_fence->list_entry);
|
||||
nv_dma_fence_signal(&nv_fence->base);
|
||||
nv_dma_fence_put(&nv_fence->base);
|
||||
dma_fence_signal(&nv_fence->base);
|
||||
dma_fence_put(&nv_fence->base);
|
||||
}
|
||||
|
||||
static void nv_drm_gem_prime_force_fence_signal(
|
||||
@@ -289,18 +287,16 @@ __nv_drm_prime_fence_context_new(
|
||||
}
|
||||
|
||||
/*
|
||||
* nv_dma_fence_context_alloc() cannot fail, so we do not need
|
||||
* dma_fence_context_alloc() cannot fail, so we do not need
|
||||
* to check a return value.
|
||||
*/
|
||||
|
||||
*nv_prime_fence_context = (struct nv_drm_prime_fence_context) {
|
||||
.base.ops = &nv_drm_prime_fence_context_ops,
|
||||
.base.nv_dev = nv_dev,
|
||||
.base.context = nv_dma_fence_context_alloc(1),
|
||||
.base.fenceSemIndex = p->index,
|
||||
.pSemSurface = pSemSurface,
|
||||
.pLinearAddress = pLinearAddress,
|
||||
};
|
||||
nv_prime_fence_context->base.ops = &nv_drm_prime_fence_context_ops;
|
||||
nv_prime_fence_context->base.nv_dev = nv_dev;
|
||||
nv_prime_fence_context->base.context = dma_fence_context_alloc(1);
|
||||
nv_prime_fence_context->base.fenceSemIndex = p->index;
|
||||
nv_prime_fence_context->pSemSurface = pSemSurface;
|
||||
nv_prime_fence_context->pLinearAddress = pLinearAddress;
|
||||
|
||||
INIT_LIST_HEAD(&nv_prime_fence_context->pending);
|
||||
|
||||
@@ -345,7 +341,7 @@ failed:
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static nv_dma_fence_t *__nv_drm_prime_fence_context_create_fence(
|
||||
static struct dma_fence *__nv_drm_prime_fence_context_create_fence(
|
||||
struct nv_drm_prime_fence_context *nv_prime_fence_context,
|
||||
unsigned int seqno)
|
||||
{
|
||||
@@ -371,12 +367,12 @@ static nv_dma_fence_t *__nv_drm_prime_fence_context_create_fence(
|
||||
|
||||
spin_lock_init(&nv_fence->lock);
|
||||
|
||||
nv_dma_fence_init(&nv_fence->base, &nv_drm_gem_prime_fence_ops,
|
||||
&nv_fence->lock, nv_prime_fence_context->base.context,
|
||||
seqno);
|
||||
dma_fence_init(&nv_fence->base, &nv_drm_gem_prime_fence_ops,
|
||||
&nv_fence->lock, nv_prime_fence_context->base.context,
|
||||
seqno);
|
||||
|
||||
/* The context maintains a reference to any pending fences. */
|
||||
nv_dma_fence_get(&nv_fence->base);
|
||||
dma_fence_get(&nv_fence->base);
|
||||
|
||||
list_add_tail(&nv_fence->list_entry, &nv_prime_fence_context->pending);
|
||||
|
||||
@@ -426,12 +422,11 @@ const struct nv_drm_gem_object_funcs nv_fence_context_gem_ops = {
|
||||
static inline
|
||||
struct nv_drm_fence_context *
|
||||
__nv_drm_fence_context_lookup(
|
||||
struct drm_device *dev,
|
||||
struct drm_file *filp,
|
||||
u32 handle)
|
||||
{
|
||||
struct nv_drm_gem_object *nv_gem =
|
||||
nv_drm_gem_object_lookup(dev, filp, handle);
|
||||
nv_drm_gem_object_lookup(filp, handle);
|
||||
|
||||
if (nv_gem != NULL && nv_gem->ops != &nv_fence_context_gem_ops) {
|
||||
nv_drm_gem_object_unreference_unlocked(nv_gem);
|
||||
@@ -465,10 +460,15 @@ int nv_drm_prime_fence_context_create_ioctl(struct drm_device *dev,
|
||||
{
|
||||
struct nv_drm_device *nv_dev = to_nv_device(dev);
|
||||
struct drm_nvidia_prime_fence_context_create_params *p = data;
|
||||
struct nv_drm_prime_fence_context *nv_prime_fence_context =
|
||||
__nv_drm_prime_fence_context_new(nv_dev, p);
|
||||
struct nv_drm_prime_fence_context *nv_prime_fence_context;
|
||||
int err;
|
||||
|
||||
if (nv_dev->pDevice == NULL) {
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
nv_prime_fence_context = __nv_drm_prime_fence_context_new(nv_dev, p);
|
||||
|
||||
if (!nv_prime_fence_context) {
|
||||
goto done;
|
||||
}
|
||||
@@ -487,6 +487,31 @@ done:
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
static int __nv_drm_gem_attach_fence(struct nv_drm_gem_object *nv_gem,
|
||||
struct dma_fence *fence,
|
||||
bool shared)
|
||||
{
|
||||
nv_dma_resv_t *resv = nv_drm_gem_res_obj(nv_gem);
|
||||
int ret;
|
||||
|
||||
nv_dma_resv_lock(resv, NULL);
|
||||
|
||||
ret = nv_dma_resv_reserve_fences(resv, 1, shared);
|
||||
if (ret == 0) {
|
||||
if (shared) {
|
||||
nv_dma_resv_add_shared_fence(resv, fence);
|
||||
} else {
|
||||
nv_dma_resv_add_excl_fence(resv, fence);
|
||||
}
|
||||
} else {
|
||||
NV_DRM_LOG_ERR("Failed to reserve fence. Error code: %d", ret);
|
||||
}
|
||||
|
||||
nv_dma_resv_unlock(resv);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev,
|
||||
void *data, struct drm_file *filep)
|
||||
{
|
||||
@@ -496,16 +521,19 @@ int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev,
|
||||
|
||||
struct nv_drm_gem_object *nv_gem;
|
||||
struct nv_drm_fence_context *nv_fence_context;
|
||||
struct dma_fence *fence;
|
||||
|
||||
nv_dma_fence_t *fence;
|
||||
nv_dma_resv_t *resv;
|
||||
if (nv_dev->pDevice == NULL) {
|
||||
ret = -EOPNOTSUPP;
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (p->__pad != 0) {
|
||||
NV_DRM_DEV_LOG_ERR(nv_dev, "Padding fields must be zeroed");
|
||||
goto done;
|
||||
}
|
||||
|
||||
nv_gem = nv_drm_gem_object_lookup(nv_dev->dev, filep, p->handle);
|
||||
nv_gem = nv_drm_gem_object_lookup(filep, p->handle);
|
||||
|
||||
if (!nv_gem) {
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
@@ -517,7 +545,6 @@ int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev,
|
||||
}
|
||||
|
||||
if((nv_fence_context = __nv_drm_fence_context_lookup(
|
||||
nv_dev->dev,
|
||||
filep,
|
||||
p->fence_context_handle)) == NULL) {
|
||||
|
||||
@@ -554,23 +581,9 @@ int nv_drm_gem_prime_fence_attach_ioctl(struct drm_device *dev,
|
||||
goto fence_context_create_fence_failed;
|
||||
}
|
||||
|
||||
resv = nv_drm_gem_res_obj(nv_gem);
|
||||
ret = __nv_drm_gem_attach_fence(nv_gem, fence, true /* exclusive */);
|
||||
|
||||
nv_dma_resv_lock(resv, NULL);
|
||||
|
||||
ret = nv_dma_resv_reserve_fences(resv, 1, false);
|
||||
if (ret == 0) {
|
||||
nv_dma_resv_add_excl_fence(resv, fence);
|
||||
} else {
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
nv_dev,
|
||||
"Failed to reserve fence. Error code: %d", ret);
|
||||
}
|
||||
|
||||
nv_dma_resv_unlock(resv);
|
||||
|
||||
/* dma_resv_add_excl_fence takes its own reference to the fence. */
|
||||
nv_dma_fence_put(fence);
|
||||
dma_fence_put(fence);
|
||||
|
||||
fence_context_create_fence_failed:
|
||||
nv_drm_gem_object_unreference_unlocked(&nv_fence_context->base);
|
||||
@@ -583,7 +596,7 @@ done:
|
||||
}
|
||||
|
||||
struct nv_drm_semsurf_fence {
|
||||
nv_dma_fence_t base;
|
||||
struct dma_fence base;
|
||||
spinlock_t lock;
|
||||
|
||||
/*
|
||||
@@ -611,7 +624,7 @@ struct nv_drm_semsurf_fence_callback {
|
||||
};
|
||||
|
||||
struct nv_drm_sync_fd_wait_data {
|
||||
nv_dma_fence_cb_t dma_fence_cb;
|
||||
struct dma_fence_cb dma_fence_cb;
|
||||
struct nv_drm_semsurf_fence_ctx *ctx;
|
||||
nv_drm_work work; /* Deferred second half of fence wait callback */
|
||||
|
||||
@@ -742,15 +755,15 @@ __nv_drm_semsurf_force_complete_pending(struct nv_drm_semsurf_fence_ctx *ctx)
|
||||
&ctx->pending_fences,
|
||||
typeof(*nv_fence),
|
||||
pending_node);
|
||||
nv_dma_fence_t *fence = &nv_fence->base;
|
||||
struct dma_fence *fence = &nv_fence->base;
|
||||
|
||||
list_del(&nv_fence->pending_node);
|
||||
|
||||
nv_dma_fence_set_error(fence, -ETIMEDOUT);
|
||||
nv_dma_fence_signal(fence);
|
||||
dma_fence_set_error(fence, -ETIMEDOUT);
|
||||
dma_fence_signal(fence);
|
||||
|
||||
/* Remove the pending list's reference */
|
||||
nv_dma_fence_put(fence);
|
||||
dma_fence_put(fence);
|
||||
}
|
||||
|
||||
/*
|
||||
@@ -807,7 +820,7 @@ __nv_drm_semsurf_ctx_process_completed(struct nv_drm_semsurf_fence_ctx *ctx,
|
||||
struct list_head finished;
|
||||
struct list_head timed_out;
|
||||
struct nv_drm_semsurf_fence *nv_fence;
|
||||
nv_dma_fence_t *fence;
|
||||
struct dma_fence *fence;
|
||||
NvU64 currentSeqno = __nv_drm_get_semsurf_ctx_seqno(ctx);
|
||||
NvU64 fenceSeqno = 0;
|
||||
unsigned long flags;
|
||||
@@ -871,8 +884,8 @@ __nv_drm_semsurf_ctx_process_completed(struct nv_drm_semsurf_fence_ctx *ctx,
|
||||
nv_fence = list_first_entry(&finished, typeof(*nv_fence), pending_node);
|
||||
list_del_init(&nv_fence->pending_node);
|
||||
fence = &nv_fence->base;
|
||||
nv_dma_fence_signal(fence);
|
||||
nv_dma_fence_put(fence); /* Drops the pending list's reference */
|
||||
dma_fence_signal(fence);
|
||||
dma_fence_put(fence); /* Drops the pending list's reference */
|
||||
}
|
||||
|
||||
while (!list_empty(&timed_out)) {
|
||||
@@ -880,9 +893,9 @@ __nv_drm_semsurf_ctx_process_completed(struct nv_drm_semsurf_fence_ctx *ctx,
|
||||
pending_node);
|
||||
list_del_init(&nv_fence->pending_node);
|
||||
fence = &nv_fence->base;
|
||||
nv_dma_fence_set_error(fence, -ETIMEDOUT);
|
||||
nv_dma_fence_signal(fence);
|
||||
nv_dma_fence_put(fence); /* Drops the pending list's reference */
|
||||
dma_fence_set_error(fence, -ETIMEDOUT);
|
||||
dma_fence_signal(fence);
|
||||
dma_fence_put(fence); /* Drops the pending list's reference */
|
||||
}
|
||||
}
|
||||
|
||||
@@ -1115,7 +1128,7 @@ static void __nv_drm_semsurf_fence_ctx_destroy(
|
||||
*/
|
||||
nv_drm_workthread_shutdown(&ctx->worker);
|
||||
|
||||
nv_drm_del_timer_sync(&ctx->timer);
|
||||
nv_timer_delete_sync(&ctx->timer.kernel_timer);
|
||||
|
||||
/*
|
||||
* The semaphore surface could still be sending callbacks, so it is still
|
||||
@@ -1248,22 +1261,20 @@ __nv_drm_semsurf_fence_ctx_new(
|
||||
}
|
||||
|
||||
/*
|
||||
* nv_dma_fence_context_alloc() cannot fail, so we do not need
|
||||
* dma_fence_context_alloc() cannot fail, so we do not need
|
||||
* to check a return value.
|
||||
*/
|
||||
|
||||
*ctx = (struct nv_drm_semsurf_fence_ctx) {
|
||||
.base.ops = &nv_drm_semsurf_fence_ctx_ops,
|
||||
.base.nv_dev = nv_dev,
|
||||
.base.context = nv_dma_fence_context_alloc(1),
|
||||
.base.fenceSemIndex = p->index,
|
||||
.pSemSurface = pSemSurface,
|
||||
.pSemMapping.pVoid = semMapping,
|
||||
.pMaxSubmittedMapping = (volatile NvU64 *)maxSubmittedMapping,
|
||||
.callback.local = NULL,
|
||||
.callback.nvKms = NULL,
|
||||
.current_wait_value = 0,
|
||||
};
|
||||
ctx->base.ops = &nv_drm_semsurf_fence_ctx_ops;
|
||||
ctx->base.nv_dev = nv_dev;
|
||||
ctx->base.context = dma_fence_context_alloc(1);
|
||||
ctx->base.fenceSemIndex = p->index;
|
||||
ctx->pSemSurface = pSemSurface;
|
||||
ctx->pSemMapping.pVoid = semMapping;
|
||||
ctx->pMaxSubmittedMapping = (volatile NvU64 *)maxSubmittedMapping;
|
||||
ctx->callback.local = NULL;
|
||||
ctx->callback.nvKms = NULL;
|
||||
ctx->current_wait_value = 0;
|
||||
|
||||
spin_lock_init(&ctx->lock);
|
||||
INIT_LIST_HEAD(&ctx->pending_fences);
|
||||
@@ -1303,6 +1314,10 @@ int nv_drm_semsurf_fence_ctx_create_ioctl(struct drm_device *dev,
|
||||
struct nv_drm_semsurf_fence_ctx *ctx;
|
||||
int err;
|
||||
|
||||
if (nv_dev->pDevice == NULL) {
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
if (p->__pad != 0) {
|
||||
NV_DRM_DEV_LOG_ERR(nv_dev, "Padding fields must be zeroed");
|
||||
return -EINVAL;
|
||||
@@ -1324,26 +1339,26 @@ int nv_drm_semsurf_fence_ctx_create_ioctl(struct drm_device *dev,
|
||||
}
|
||||
|
||||
static inline struct nv_drm_semsurf_fence*
|
||||
to_nv_drm_semsurf_fence(nv_dma_fence_t *fence)
|
||||
to_nv_drm_semsurf_fence(struct dma_fence *fence)
|
||||
{
|
||||
return container_of(fence, struct nv_drm_semsurf_fence, base);
|
||||
}
|
||||
|
||||
static const char*
|
||||
__nv_drm_semsurf_fence_op_get_timeline_name(nv_dma_fence_t *fence)
|
||||
__nv_drm_semsurf_fence_op_get_timeline_name(struct dma_fence *fence)
|
||||
{
|
||||
return "nvidia.semaphore_surface";
|
||||
}
|
||||
|
||||
static bool
|
||||
__nv_drm_semsurf_fence_op_enable_signaling(nv_dma_fence_t *fence)
|
||||
__nv_drm_semsurf_fence_op_enable_signaling(struct dma_fence *fence)
|
||||
{
|
||||
// DO NOTHING - Could defer RM callback registration until this point
|
||||
return true;
|
||||
}
|
||||
|
||||
static void
|
||||
__nv_drm_semsurf_fence_op_release(nv_dma_fence_t *fence)
|
||||
__nv_drm_semsurf_fence_op_release(struct dma_fence *fence)
|
||||
{
|
||||
struct nv_drm_semsurf_fence *nv_fence =
|
||||
to_nv_drm_semsurf_fence(fence);
|
||||
@@ -1351,11 +1366,12 @@ __nv_drm_semsurf_fence_op_release(nv_dma_fence_t *fence)
|
||||
nv_drm_free(nv_fence);
|
||||
}
|
||||
|
||||
static const nv_dma_fence_ops_t nv_drm_semsurf_fence_ops = {
|
||||
static const struct dma_fence_ops nv_drm_semsurf_fence_ops = {
|
||||
.get_driver_name = nv_drm_gem_fence_op_get_driver_name,
|
||||
.get_timeline_name = __nv_drm_semsurf_fence_op_get_timeline_name,
|
||||
.enable_signaling = __nv_drm_semsurf_fence_op_enable_signaling,
|
||||
.release = __nv_drm_semsurf_fence_op_release,
|
||||
.wait = dma_fence_default_wait,
|
||||
#if defined(NV_DMA_FENCE_OPS_HAS_USE_64BIT_SEQNO)
|
||||
.use_64bit_seqno = true,
|
||||
#endif
|
||||
@@ -1381,7 +1397,7 @@ __nv_drm_semsurf_ctx_add_pending(struct nv_drm_semsurf_fence_ctx *ctx,
|
||||
}
|
||||
|
||||
/* Add a reference to the fence for the list */
|
||||
nv_dma_fence_get(&nv_fence->base);
|
||||
dma_fence_get(&nv_fence->base);
|
||||
INIT_LIST_HEAD(&nv_fence->pending_node);
|
||||
|
||||
nv_fence->timeout = nv_drm_timeout_from_ms(timeoutMS);
|
||||
@@ -1414,16 +1430,21 @@ __nv_drm_semsurf_ctx_add_pending(struct nv_drm_semsurf_fence_ctx *ctx,
|
||||
__nv_drm_semsurf_ctx_reg_callbacks(ctx);
|
||||
}
|
||||
|
||||
static nv_dma_fence_t *__nv_drm_semsurf_fence_ctx_create_fence(
|
||||
static struct dma_fence *__nv_drm_semsurf_fence_ctx_create_fence(
|
||||
struct nv_drm_device *nv_dev,
|
||||
struct nv_drm_semsurf_fence_ctx *ctx,
|
||||
NvU64 wait_value,
|
||||
NvU64 timeout_value_ms)
|
||||
{
|
||||
struct nv_drm_semsurf_fence *nv_fence;
|
||||
nv_dma_fence_t *fence;
|
||||
struct dma_fence *fence;
|
||||
int ret = 0;
|
||||
|
||||
if (timeout_value_ms == 0 ||
|
||||
timeout_value_ms > NV_DRM_SEMAPHORE_SURFACE_FENCE_MAX_TIMEOUT_MS) {
|
||||
timeout_value_ms = NV_DRM_SEMAPHORE_SURFACE_FENCE_MAX_TIMEOUT_MS;
|
||||
}
|
||||
|
||||
if ((nv_fence = nv_drm_calloc(1, sizeof(*nv_fence))) == NULL) {
|
||||
ret = -ENOMEM;
|
||||
goto out;
|
||||
@@ -1436,9 +1457,9 @@ static nv_dma_fence_t *__nv_drm_semsurf_fence_ctx_create_fence(
|
||||
#endif
|
||||
|
||||
/* Initializes the fence with one reference (for the caller) */
|
||||
nv_dma_fence_init(fence, &nv_drm_semsurf_fence_ops,
|
||||
&nv_fence->lock,
|
||||
ctx->base.context, wait_value);
|
||||
dma_fence_init(fence, &nv_drm_semsurf_fence_ops,
|
||||
&nv_fence->lock,
|
||||
ctx->base.context, wait_value);
|
||||
|
||||
__nv_drm_semsurf_ctx_add_pending(ctx, nv_fence, timeout_value_ms);
|
||||
|
||||
@@ -1454,18 +1475,21 @@ int nv_drm_semsurf_fence_create_ioctl(struct drm_device *dev,
|
||||
struct nv_drm_device *nv_dev = to_nv_device(dev);
|
||||
struct drm_nvidia_semsurf_fence_create_params *p = data;
|
||||
struct nv_drm_fence_context *nv_fence_context;
|
||||
nv_dma_fence_t *fence;
|
||||
uint32_t timeout = NV_DRM_SEMAPHORE_SURFACE_FENCE_MAX_TIMEOUT_MS;
|
||||
struct dma_fence *fence;
|
||||
int ret = -EINVAL;
|
||||
int fd;
|
||||
|
||||
if (nv_dev->pDevice == NULL) {
|
||||
ret = -EOPNOTSUPP;
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (p->__pad != 0) {
|
||||
NV_DRM_DEV_LOG_ERR(nv_dev, "Padding fields must be zeroed");
|
||||
goto done;
|
||||
}
|
||||
|
||||
if ((nv_fence_context = __nv_drm_fence_context_lookup(
|
||||
nv_dev->dev,
|
||||
filep,
|
||||
p->fence_context_handle)) == NULL) {
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
@@ -1485,16 +1509,11 @@ int nv_drm_semsurf_fence_create_ioctl(struct drm_device *dev,
|
||||
goto fence_context_create_fence_failed;
|
||||
}
|
||||
|
||||
if ((p->timeout_value_ms != 0) &&
|
||||
(p->timeout_value_ms < timeout)) {
|
||||
timeout = p->timeout_value_ms;
|
||||
}
|
||||
|
||||
fence = __nv_drm_semsurf_fence_ctx_create_fence(
|
||||
nv_dev,
|
||||
to_semsurf_fence_ctx(nv_fence_context),
|
||||
p->wait_value,
|
||||
timeout);
|
||||
p->timeout_value_ms);
|
||||
|
||||
if (IS_ERR(fence)) {
|
||||
ret = PTR_ERR(fence);
|
||||
@@ -1526,7 +1545,7 @@ fence_context_create_sync_failed:
|
||||
* FD will still hold a reference, and the pending list (if the fence hasn't
|
||||
* already been signaled) will also retain a reference.
|
||||
*/
|
||||
nv_dma_fence_put(fence);
|
||||
dma_fence_put(fence);
|
||||
|
||||
fence_context_create_fence_failed:
|
||||
nv_drm_gem_object_unreference_unlocked(&nv_fence_context->base);
|
||||
@@ -1584,8 +1603,8 @@ __nv_drm_semsurf_wait_fence_work_cb
|
||||
static void
|
||||
__nv_drm_semsurf_wait_fence_cb
|
||||
(
|
||||
nv_dma_fence_t *fence,
|
||||
nv_dma_fence_cb_t *cb
|
||||
struct dma_fence *fence,
|
||||
struct dma_fence_cb *cb
|
||||
)
|
||||
{
|
||||
struct nv_drm_sync_fd_wait_data *wait_data =
|
||||
@@ -1610,7 +1629,7 @@ __nv_drm_semsurf_wait_fence_cb
|
||||
}
|
||||
|
||||
/* Don't need to reference the fence anymore, just the fence context. */
|
||||
nv_dma_fence_put(fence);
|
||||
dma_fence_put(fence);
|
||||
}
|
||||
|
||||
int nv_drm_semsurf_fence_wait_ioctl(struct drm_device *dev,
|
||||
@@ -1622,20 +1641,23 @@ int nv_drm_semsurf_fence_wait_ioctl(struct drm_device *dev,
|
||||
struct nv_drm_fence_context *nv_fence_context;
|
||||
struct nv_drm_semsurf_fence_ctx *ctx;
|
||||
struct nv_drm_sync_fd_wait_data *wait_data = NULL;
|
||||
nv_dma_fence_t *fence;
|
||||
struct dma_fence *fence;
|
||||
unsigned long flags;
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (nv_dev->pDevice == NULL) {
|
||||
return -EOPNOTSUPP;
|
||||
}
|
||||
|
||||
if (p->pre_wait_value >= p->post_wait_value) {
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
nv_dev,
|
||||
"Non-monotonic wait values specified to fence wait: 0x%llu, 0x%llu",
|
||||
"Non-monotonic wait values specified to fence wait: 0x%" NvU64_fmtu ", 0x%" NvU64_fmtu,
|
||||
p->pre_wait_value, p->post_wait_value);
|
||||
goto done;
|
||||
}
|
||||
|
||||
if ((nv_fence_context = __nv_drm_fence_context_lookup(
|
||||
nv_dev->dev,
|
||||
filep,
|
||||
p->fence_context_handle)) == NULL) {
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
@@ -1688,9 +1710,9 @@ int nv_drm_semsurf_fence_wait_ioctl(struct drm_device *dev,
|
||||
list_add(&wait_data->pending_node, &ctx->pending_waits);
|
||||
spin_unlock_irqrestore(&ctx->lock, flags);
|
||||
|
||||
ret = nv_dma_fence_add_callback(fence,
|
||||
&wait_data->dma_fence_cb,
|
||||
__nv_drm_semsurf_wait_fence_cb);
|
||||
ret = dma_fence_add_callback(fence,
|
||||
&wait_data->dma_fence_cb,
|
||||
__nv_drm_semsurf_wait_fence_cb);
|
||||
|
||||
if (ret) {
|
||||
if (ret == -ENOENT) {
|
||||
@@ -1702,7 +1724,7 @@ int nv_drm_semsurf_fence_wait_ioctl(struct drm_device *dev,
|
||||
}
|
||||
|
||||
/* Execute second half of wait immediately, avoiding the worker thread */
|
||||
nv_dma_fence_put(fence);
|
||||
dma_fence_put(fence);
|
||||
__nv_drm_semsurf_wait_fence_work_cb(wait_data);
|
||||
}
|
||||
|
||||
@@ -1723,6 +1745,85 @@ done:
|
||||
return 0;
|
||||
}
|
||||
|
||||
#endif /* NV_DRM_FENCE_AVAILABLE */
|
||||
int nv_drm_semsurf_fence_attach_ioctl(struct drm_device *dev,
|
||||
void *data,
|
||||
struct drm_file *filep)
|
||||
{
|
||||
struct nv_drm_device *nv_dev = to_nv_device(dev);
|
||||
struct drm_nvidia_semsurf_fence_attach_params *p = data;
|
||||
struct nv_drm_gem_object *nv_gem = NULL;
|
||||
struct nv_drm_fence_context *nv_fence_context = NULL;
|
||||
struct dma_fence *fence;
|
||||
int ret = -EINVAL;
|
||||
|
||||
if (nv_dev->pDevice == NULL) {
|
||||
ret = -EOPNOTSUPP;
|
||||
goto done;
|
||||
}
|
||||
|
||||
nv_gem = nv_drm_gem_object_lookup(filep, p->handle);
|
||||
|
||||
if (!nv_gem) {
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
nv_dev,
|
||||
"Failed to lookup gem object for fence attach: 0x%08x",
|
||||
p->handle);
|
||||
|
||||
goto done;
|
||||
}
|
||||
|
||||
nv_fence_context = __nv_drm_fence_context_lookup(
|
||||
filep,
|
||||
p->fence_context_handle);
|
||||
|
||||
if (!nv_fence_context) {
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
nv_dev,
|
||||
"Failed to lookup gem object for fence context: 0x%08x",
|
||||
p->fence_context_handle);
|
||||
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (nv_fence_context->ops != &nv_drm_semsurf_fence_ctx_ops) {
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
nv_dev,
|
||||
"Wrong fence context type: 0x%08x",
|
||||
p->fence_context_handle);
|
||||
|
||||
goto done;
|
||||
}
|
||||
|
||||
fence = __nv_drm_semsurf_fence_ctx_create_fence(
|
||||
nv_dev,
|
||||
to_semsurf_fence_ctx(nv_fence_context),
|
||||
p->wait_value,
|
||||
p->timeout_value_ms);
|
||||
|
||||
if (IS_ERR(fence)) {
|
||||
ret = PTR_ERR(fence);
|
||||
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
nv_dev,
|
||||
"Failed to allocate fence: 0x%08x", p->handle);
|
||||
|
||||
goto done;
|
||||
}
|
||||
|
||||
ret = __nv_drm_gem_attach_fence(nv_gem, fence, p->shared);
|
||||
|
||||
dma_fence_put(fence);
|
||||
|
||||
done:
|
||||
if (nv_fence_context) {
|
||||
nv_drm_gem_object_unreference_unlocked(&nv_fence_context->base);
|
||||
}
|
||||
|
||||
if (nv_gem) {
|
||||
nv_drm_gem_object_unreference_unlocked(nv_gem);
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif /* NV_DRM_AVAILABLE */
|
||||
@@ -30,8 +30,6 @@
|
||||
struct drm_file;
|
||||
struct drm_device;
|
||||
|
||||
#if defined(NV_DRM_FENCE_AVAILABLE)
|
||||
|
||||
int nv_drm_fence_supported_ioctl(struct drm_device *dev,
|
||||
void *data, struct drm_file *filep);
|
||||
|
||||
@@ -53,7 +51,9 @@ int nv_drm_semsurf_fence_wait_ioctl(struct drm_device *dev,
|
||||
void *data,
|
||||
struct drm_file *filep);
|
||||
|
||||
#endif /* NV_DRM_FENCE_AVAILABLE */
|
||||
int nv_drm_semsurf_fence_attach_ioctl(struct drm_device *dev,
|
||||
void *data,
|
||||
struct drm_file *filep);
|
||||
|
||||
#endif /* NV_DRM_AVAILABLE */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2019-2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -35,15 +35,22 @@
|
||||
|
||||
static const u32 nvkms_to_drm_format[] = {
|
||||
/* RGB formats */
|
||||
[NvKmsSurfaceMemoryFormatA1R5G5B5] = DRM_FORMAT_ARGB1555,
|
||||
[NvKmsSurfaceMemoryFormatX1R5G5B5] = DRM_FORMAT_XRGB1555,
|
||||
[NvKmsSurfaceMemoryFormatR5G6B5] = DRM_FORMAT_RGB565,
|
||||
[NvKmsSurfaceMemoryFormatA8R8G8B8] = DRM_FORMAT_ARGB8888,
|
||||
[NvKmsSurfaceMemoryFormatX8R8G8B8] = DRM_FORMAT_XRGB8888,
|
||||
[NvKmsSurfaceMemoryFormatX8B8G8R8] = DRM_FORMAT_XBGR8888,
|
||||
[NvKmsSurfaceMemoryFormatA2B10G10R10] = DRM_FORMAT_ABGR2101010,
|
||||
[NvKmsSurfaceMemoryFormatX2B10G10R10] = DRM_FORMAT_XBGR2101010,
|
||||
[NvKmsSurfaceMemoryFormatA8B8G8R8] = DRM_FORMAT_ABGR8888,
|
||||
[NvKmsSurfaceMemoryFormatA1R5G5B5] = DRM_FORMAT_ARGB1555,
|
||||
[NvKmsSurfaceMemoryFormatX1R5G5B5] = DRM_FORMAT_XRGB1555,
|
||||
[NvKmsSurfaceMemoryFormatR5G6B5] = DRM_FORMAT_RGB565,
|
||||
[NvKmsSurfaceMemoryFormatA8R8G8B8] = DRM_FORMAT_ARGB8888,
|
||||
[NvKmsSurfaceMemoryFormatX8R8G8B8] = DRM_FORMAT_XRGB8888,
|
||||
[NvKmsSurfaceMemoryFormatX8B8G8R8] = DRM_FORMAT_XBGR8888,
|
||||
[NvKmsSurfaceMemoryFormatA2B10G10R10] = DRM_FORMAT_ABGR2101010,
|
||||
[NvKmsSurfaceMemoryFormatX2B10G10R10] = DRM_FORMAT_XBGR2101010,
|
||||
[NvKmsSurfaceMemoryFormatA8B8G8R8] = DRM_FORMAT_ABGR8888,
|
||||
#if defined(DRM_FORMAT_ABGR16161616)
|
||||
/*
|
||||
* DRM_FORMAT_ABGR16161616 was introduced by Linux kernel commit
|
||||
* ff92ecf575a92 (v5.14).
|
||||
*/
|
||||
[NvKmsSurfaceMemoryFormatR16G16B16A16] = DRM_FORMAT_ABGR16161616,
|
||||
#endif
|
||||
#if defined(DRM_FORMAT_ABGR16161616F)
|
||||
[NvKmsSurfaceMemoryFormatRF16GF16BF16AF16] = DRM_FORMAT_ABGR16161616F,
|
||||
#endif
|
||||
@@ -166,4 +173,37 @@ uint32_t *nv_drm_format_array_alloc(
|
||||
return array;
|
||||
}
|
||||
|
||||
bool nv_drm_format_is_yuv(u32 format)
|
||||
{
|
||||
#if defined(NV_DRM_FORMAT_INFO_HAS_IS_YUV)
|
||||
const struct drm_format_info *format_info = drm_format_info(format);
|
||||
return (format_info != NULL) && format_info->is_yuv;
|
||||
#else
|
||||
switch (format) {
|
||||
case DRM_FORMAT_YUYV:
|
||||
case DRM_FORMAT_UYVY:
|
||||
|
||||
case DRM_FORMAT_NV24:
|
||||
case DRM_FORMAT_NV42:
|
||||
case DRM_FORMAT_NV16:
|
||||
case DRM_FORMAT_NV61:
|
||||
case DRM_FORMAT_NV12:
|
||||
case DRM_FORMAT_NV21:
|
||||
|
||||
#if defined(DRM_FORMAT_P210)
|
||||
case DRM_FORMAT_P210:
|
||||
#endif
|
||||
#if defined(DRM_FORMAT_P010)
|
||||
case DRM_FORMAT_P010:
|
||||
#endif
|
||||
#if defined(DRM_FORMAT_P012)
|
||||
case DRM_FORMAT_P012:
|
||||
#endif
|
||||
return true;
|
||||
default:
|
||||
return false;
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
#endif
|
||||
@@ -38,6 +38,8 @@ uint32_t *nv_drm_format_array_alloc(
|
||||
unsigned int *count,
|
||||
const long unsigned int nvkms_format_mask);
|
||||
|
||||
bool nv_drm_format_is_yuv(u32 format);
|
||||
|
||||
#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
|
||||
|
||||
#endif /* __NVIDIA_DRM_FORMAT_H__ */
|
||||
@@ -24,17 +24,13 @@
|
||||
|
||||
#if defined(NV_DRM_AVAILABLE)
|
||||
|
||||
#if defined(NV_DRM_DRM_PRIME_H_PRESENT)
|
||||
#include <drm/drm_prime.h>
|
||||
#endif
|
||||
|
||||
#if defined(NV_DRM_DRMP_H_PRESENT)
|
||||
#include <drm/drmP.h>
|
||||
#endif
|
||||
|
||||
#if defined(NV_DRM_DRM_DRV_H_PRESENT)
|
||||
#include <drm/drm_drv.h>
|
||||
#endif
|
||||
|
||||
#include "nvidia-drm-gem-dma-buf.h"
|
||||
#include "nvidia-drm-ioctl.h"
|
||||
@@ -71,12 +67,42 @@ static int __nv_drm_gem_dma_buf_create_mmap_offset(
|
||||
static int __nv_drm_gem_dma_buf_mmap(struct nv_drm_gem_object *nv_gem,
|
||||
struct vm_area_struct *vma)
|
||||
{
|
||||
#if defined(NV_LINUX)
|
||||
struct dma_buf_attachment *attach = nv_gem->base.import_attach;
|
||||
struct dma_buf *dma_buf = attach->dmabuf;
|
||||
#endif
|
||||
struct file *old_file;
|
||||
int ret;
|
||||
|
||||
/* check if buffer supports mmap */
|
||||
#if defined(NV_BSD)
|
||||
/*
|
||||
* Most of the FreeBSD DRM code refers to struct file*, which is actually
|
||||
* a struct linux_file*. The dmabuf code in FreeBSD is not actually plumbed
|
||||
* through the same linuxkpi bits it seems (probably so it can be used
|
||||
* elsewhere), so dma_buf->file really is a native FreeBSD struct file...
|
||||
*/
|
||||
if (!nv_gem->base.filp->f_op->mmap)
|
||||
return -EINVAL;
|
||||
|
||||
/* readjust the vma */
|
||||
get_file(nv_gem->base.filp);
|
||||
old_file = vma->vm_file;
|
||||
vma->vm_file = nv_gem->base.filp;
|
||||
vma->vm_pgoff -= drm_vma_node_start(&nv_gem->base.vma_node);
|
||||
|
||||
ret = nv_gem->base.filp->f_op->mmap(nv_gem->base.filp, vma);
|
||||
|
||||
if (ret) {
|
||||
/* restore old parameters on failure */
|
||||
vma->vm_file = old_file;
|
||||
vma->vm_pgoff += drm_vma_node_start(&nv_gem->base.vma_node);
|
||||
fput(nv_gem->base.filp);
|
||||
} else {
|
||||
if (old_file)
|
||||
fput(old_file);
|
||||
}
|
||||
#else
|
||||
if (!dma_buf->file->f_op->mmap)
|
||||
return -EINVAL;
|
||||
|
||||
@@ -84,18 +110,20 @@ static int __nv_drm_gem_dma_buf_mmap(struct nv_drm_gem_object *nv_gem,
|
||||
get_file(dma_buf->file);
|
||||
old_file = vma->vm_file;
|
||||
vma->vm_file = dma_buf->file;
|
||||
vma->vm_pgoff -= drm_vma_node_start(&nv_gem->base.vma_node);;
|
||||
vma->vm_pgoff -= drm_vma_node_start(&nv_gem->base.vma_node);
|
||||
|
||||
ret = dma_buf->file->f_op->mmap(dma_buf->file, vma);
|
||||
|
||||
if (ret) {
|
||||
/* restore old parameters on failure */
|
||||
vma->vm_file = old_file;
|
||||
vma->vm_pgoff += drm_vma_node_start(&nv_gem->base.vma_node);
|
||||
fput(dma_buf->file);
|
||||
} else {
|
||||
if (old_file)
|
||||
fput(old_file);
|
||||
}
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
@@ -162,7 +190,7 @@ int nv_drm_gem_export_dmabuf_memory_ioctl(struct drm_device *dev,
|
||||
}
|
||||
|
||||
if ((nv_dma_buf = nv_drm_gem_object_dma_buf_lookup(
|
||||
dev, filep, p->handle)) == NULL) {
|
||||
filep, p->handle)) == NULL) {
|
||||
ret = -EINVAL;
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
nv_dev,
|
||||
@@ -48,12 +48,11 @@ static inline struct nv_drm_gem_dma_buf *to_nv_dma_buf(
|
||||
|
||||
static inline
|
||||
struct nv_drm_gem_dma_buf *nv_drm_gem_object_dma_buf_lookup(
|
||||
struct drm_device *dev,
|
||||
struct drm_file *filp,
|
||||
u32 handle)
|
||||
{
|
||||
struct nv_drm_gem_object *nv_gem =
|
||||
nv_drm_gem_object_lookup(dev, filp, handle);
|
||||
nv_drm_gem_object_lookup(filp, handle);
|
||||
|
||||
if (nv_gem != NULL && nv_gem->ops != &__nv_gem_dma_buf_ops) {
|
||||
nv_drm_gem_object_unreference_unlocked(nv_gem);
|
||||
@@ -28,17 +28,13 @@
|
||||
#include "nvidia-drm-helper.h"
|
||||
#include "nvidia-drm-ioctl.h"
|
||||
|
||||
#if defined(NV_DRM_DRM_DRV_H_PRESENT)
|
||||
#include <drm/drm_drv.h>
|
||||
#endif
|
||||
|
||||
#if defined(NV_DRM_DRM_PRIME_H_PRESENT)
|
||||
#include <drm/drm_prime.h>
|
||||
#endif
|
||||
|
||||
#include <linux/io.h>
|
||||
|
||||
#include "nv-mm.h"
|
||||
#if defined(NV_BSD)
|
||||
#include <vm/vm_pageout.h>
|
||||
#endif
|
||||
|
||||
static void __nv_drm_gem_nvkms_memory_free(struct nv_drm_gem_object *nv_gem)
|
||||
{
|
||||
@@ -68,9 +64,20 @@ static void __nv_drm_gem_nvkms_memory_free(struct nv_drm_gem_object *nv_gem)
|
||||
nv_drm_free(nv_nvkms_memory);
|
||||
}
|
||||
|
||||
static int __nv_drm_gem_nvkms_map(
|
||||
struct nv_drm_gem_nvkms_memory *nv_nvkms_memory);
|
||||
|
||||
static int __nv_drm_gem_nvkms_mmap(struct nv_drm_gem_object *nv_gem,
|
||||
struct vm_area_struct *vma)
|
||||
{
|
||||
struct nv_drm_gem_nvkms_memory *nv_nvkms_memory =
|
||||
to_nv_nvkms_memory(nv_gem);
|
||||
|
||||
int ret = __nv_drm_gem_nvkms_map(nv_nvkms_memory);
|
||||
if (ret) {
|
||||
return ret;
|
||||
}
|
||||
|
||||
return drm_gem_mmap_obj(&nv_gem->base,
|
||||
drm_vma_node_size(&nv_gem->base.vma_node) << PAGE_SHIFT, vma);
|
||||
}
|
||||
@@ -83,7 +90,7 @@ static vm_fault_t __nv_drm_gem_nvkms_handle_vma_fault(
|
||||
#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
|
||||
struct nv_drm_gem_nvkms_memory *nv_nvkms_memory =
|
||||
to_nv_nvkms_memory(nv_gem);
|
||||
unsigned long address = nv_page_fault_va(vmf);
|
||||
unsigned long address = vmf->address;
|
||||
struct drm_gem_object *gem = vma->vm_private_data;
|
||||
unsigned long page_offset, pfn;
|
||||
vm_fault_t ret;
|
||||
@@ -93,7 +100,17 @@ static vm_fault_t __nv_drm_gem_nvkms_handle_vma_fault(
|
||||
if (nv_nvkms_memory->pages_count == 0) {
|
||||
pfn = (unsigned long)(uintptr_t)nv_nvkms_memory->pPhysicalAddress;
|
||||
pfn >>= PAGE_SHIFT;
|
||||
#if defined(NV_LINUX)
|
||||
/*
|
||||
* FreeBSD doesn't set pgoff. We instead have pfn be the base physical
|
||||
* address, and we will calculate the index pidx from the virtual address.
|
||||
*
|
||||
* This only works because linux_cdev_pager_populate passes the pidx as
|
||||
* vmf->virtual_address. Then we turn the virtual address
|
||||
* into a physical page number.
|
||||
*/
|
||||
pfn += page_offset;
|
||||
#endif
|
||||
} else {
|
||||
BUG_ON(page_offset >= nv_nvkms_memory->pages_count);
|
||||
pfn = page_to_pfn(nv_nvkms_memory->pages[page_offset]);
|
||||
@@ -133,11 +150,18 @@ static struct drm_gem_object *__nv_drm_gem_nvkms_prime_dup(
|
||||
static int __nv_drm_gem_nvkms_map(
|
||||
struct nv_drm_gem_nvkms_memory *nv_nvkms_memory)
|
||||
{
|
||||
int ret = 0;
|
||||
struct nv_drm_device *nv_dev = nv_nvkms_memory->base.nv_dev;
|
||||
struct NvKmsKapiMemory *pMemory = nv_nvkms_memory->base.pMemory;
|
||||
|
||||
if (!nv_dev->hasVideoMemory) {
|
||||
return 0;
|
||||
mutex_lock(&nv_nvkms_memory->map_lock);
|
||||
|
||||
if (nv_nvkms_memory->physically_mapped) {
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (!nvKms->isVidmem(pMemory)) {
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (!nvKms->mapMemory(nv_dev->pDevice,
|
||||
@@ -148,7 +172,8 @@ static int __nv_drm_gem_nvkms_map(
|
||||
nv_dev,
|
||||
"Failed to map NvKmsKapiMemory 0x%p",
|
||||
pMemory);
|
||||
return -ENOMEM;
|
||||
ret = -ENOMEM;
|
||||
goto done;
|
||||
}
|
||||
|
||||
nv_nvkms_memory->pWriteCombinedIORemapAddress = ioremap_wc(
|
||||
@@ -164,7 +189,9 @@ static int __nv_drm_gem_nvkms_map(
|
||||
|
||||
nv_nvkms_memory->physically_mapped = true;
|
||||
|
||||
return 0;
|
||||
done:
|
||||
mutex_unlock(&nv_nvkms_memory->map_lock);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static void *__nv_drm_gem_nvkms_prime_vmap(
|
||||
@@ -173,14 +200,40 @@ static void *__nv_drm_gem_nvkms_prime_vmap(
|
||||
struct nv_drm_gem_nvkms_memory *nv_nvkms_memory =
|
||||
to_nv_nvkms_memory(nv_gem);
|
||||
|
||||
if (!nv_nvkms_memory->physically_mapped) {
|
||||
int ret = __nv_drm_gem_nvkms_map(nv_nvkms_memory);
|
||||
if (ret) {
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
int ret = __nv_drm_gem_nvkms_map(nv_nvkms_memory);
|
||||
if (ret) {
|
||||
return ERR_PTR(ret);
|
||||
}
|
||||
|
||||
return nv_nvkms_memory->pWriteCombinedIORemapAddress;
|
||||
if (nv_nvkms_memory->physically_mapped) {
|
||||
return nv_nvkms_memory->pWriteCombinedIORemapAddress;
|
||||
}
|
||||
|
||||
/*
|
||||
* If this buffer isn't physically mapped, it might be backed by struct
|
||||
* pages. Use vmap in that case. Do a noncached mapping for system memory
|
||||
* as display is non io-coherent device in case of Tegra.
|
||||
*/
|
||||
if (nv_nvkms_memory->pages_count > 0) {
|
||||
return nv_drm_vmap(nv_nvkms_memory->pages,
|
||||
nv_nvkms_memory->pages_count,
|
||||
false);
|
||||
}
|
||||
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
static void __nv_drm_gem_nvkms_prime_vunmap(
|
||||
struct nv_drm_gem_object *nv_gem,
|
||||
void *address)
|
||||
{
|
||||
struct nv_drm_gem_nvkms_memory *nv_nvkms_memory =
|
||||
to_nv_nvkms_memory(nv_gem);
|
||||
|
||||
if (!nv_nvkms_memory->physically_mapped &&
|
||||
nv_nvkms_memory->pages_count > 0) {
|
||||
nv_drm_vunmap(address);
|
||||
}
|
||||
}
|
||||
|
||||
static int __nv_drm_gem_map_nvkms_memory_offset(
|
||||
@@ -188,17 +241,7 @@ static int __nv_drm_gem_map_nvkms_memory_offset(
|
||||
struct nv_drm_gem_object *nv_gem,
|
||||
uint64_t *offset)
|
||||
{
|
||||
struct nv_drm_gem_nvkms_memory *nv_nvkms_memory =
|
||||
to_nv_nvkms_memory(nv_gem);
|
||||
|
||||
if (!nv_nvkms_memory->physically_mapped) {
|
||||
int ret = __nv_drm_gem_nvkms_map(nv_nvkms_memory);
|
||||
if (ret) {
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
return nv_drm_gem_create_mmap_offset(&nv_nvkms_memory->base, offset);
|
||||
return nv_drm_gem_create_mmap_offset(nv_gem, offset);
|
||||
}
|
||||
|
||||
static struct sg_table *__nv_drm_gem_nvkms_memory_prime_get_sg_table(
|
||||
@@ -210,7 +253,7 @@ static struct sg_table *__nv_drm_gem_nvkms_memory_prime_get_sg_table(
|
||||
struct sg_table *sg_table;
|
||||
|
||||
if (nv_nvkms_memory->pages_count == 0) {
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
NV_DRM_DEV_DEBUG_DRIVER(
|
||||
nv_dev,
|
||||
"Cannot create sg_table for NvKmsKapiMemory 0x%p",
|
||||
nv_gem->pMemory);
|
||||
@@ -228,6 +271,7 @@ const struct nv_drm_gem_object_funcs nv_gem_nvkms_memory_ops = {
|
||||
.free = __nv_drm_gem_nvkms_memory_free,
|
||||
.prime_dup = __nv_drm_gem_nvkms_prime_dup,
|
||||
.prime_vmap = __nv_drm_gem_nvkms_prime_vmap,
|
||||
.prime_vunmap = __nv_drm_gem_nvkms_prime_vunmap,
|
||||
.mmap = __nv_drm_gem_nvkms_mmap,
|
||||
.handle_vma_fault = __nv_drm_gem_nvkms_handle_vma_fault,
|
||||
.create_mmap_offset = __nv_drm_gem_map_nvkms_memory_offset,
|
||||
@@ -243,16 +287,26 @@ static int __nv_drm_nvkms_gem_obj_init(
|
||||
NvU64 *pages = NULL;
|
||||
NvU32 numPages = 0;
|
||||
|
||||
if ((size % PAGE_SIZE) != 0) {
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
nv_dev,
|
||||
"NvKmsKapiMemory 0x%p size should be in a multiple of page size to "
|
||||
"create a gem object",
|
||||
pMemory);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
mutex_init(&nv_nvkms_memory->map_lock);
|
||||
nv_nvkms_memory->pPhysicalAddress = NULL;
|
||||
nv_nvkms_memory->pWriteCombinedIORemapAddress = NULL;
|
||||
nv_nvkms_memory->physically_mapped = false;
|
||||
|
||||
if (!nvKms->getMemoryPages(nv_dev->pDevice,
|
||||
if (!nvKms->isVidmem(pMemory) &&
|
||||
!nvKms->getMemoryPages(nv_dev->pDevice,
|
||||
pMemory,
|
||||
&pages,
|
||||
&numPages) &&
|
||||
!nv_dev->hasVideoMemory) {
|
||||
/* GetMemoryPages may fail for vidmem allocations,
|
||||
&numPages)) {
|
||||
/* GetMemoryPages will fail for vidmem allocations,
|
||||
* but it should not fail for sysmem allocations. */
|
||||
NV_DRM_DEV_LOG_ERR(nv_dev,
|
||||
"Failed to get memory pages for NvKmsKapiMemory 0x%p",
|
||||
@@ -279,6 +333,7 @@ int nv_drm_dumb_create(
|
||||
struct nv_drm_gem_nvkms_memory *nv_nvkms_memory;
|
||||
uint8_t compressible = 0;
|
||||
struct NvKmsKapiMemory *pMemory;
|
||||
struct NvKmsKapiAllocateMemoryParams allocParams = { };
|
||||
int ret = 0;
|
||||
|
||||
args->pitch = roundup(args->width * ((args->bpp + 7) >> 3),
|
||||
@@ -296,25 +351,19 @@ int nv_drm_dumb_create(
|
||||
goto fail;
|
||||
}
|
||||
|
||||
if (nv_dev->hasVideoMemory) {
|
||||
pMemory = nvKms->allocateVideoMemory(nv_dev->pDevice,
|
||||
NvKmsSurfaceMemoryLayoutPitch,
|
||||
NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT,
|
||||
args->size,
|
||||
&compressible);
|
||||
} else {
|
||||
pMemory = nvKms->allocateSystemMemory(nv_dev->pDevice,
|
||||
NvKmsSurfaceMemoryLayoutPitch,
|
||||
NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT,
|
||||
args->size,
|
||||
&compressible);
|
||||
}
|
||||
allocParams.layout = NvKmsSurfaceMemoryLayoutPitch;
|
||||
allocParams.type = NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT;
|
||||
allocParams.size = args->size;
|
||||
allocParams.noDisplayCaching = true;
|
||||
allocParams.useVideoMemory = nv_dev->hasVideoMemory;
|
||||
allocParams.compressible = &compressible;
|
||||
|
||||
pMemory = nvKms->allocateMemory(nv_dev->pDevice, &allocParams);
|
||||
if (pMemory == NULL) {
|
||||
ret = -ENOMEM;
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
nv_dev,
|
||||
"Failed to allocate NvKmsKapiMemory for dumb object of size %llu",
|
||||
"Failed to allocate NvKmsKapiMemory for dumb object of size %" NvU64_fmtu,
|
||||
args->size);
|
||||
goto nvkms_alloc_memory_failed;
|
||||
}
|
||||
@@ -358,7 +407,7 @@ int nv_drm_gem_import_nvkms_memory_ioctl(struct drm_device *dev,
|
||||
int ret;
|
||||
|
||||
if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
|
||||
ret = -EINVAL;
|
||||
ret = -EOPNOTSUPP;
|
||||
goto failed;
|
||||
}
|
||||
|
||||
@@ -408,7 +457,7 @@ int nv_drm_gem_export_nvkms_memory_ioctl(struct drm_device *dev,
|
||||
int ret = 0;
|
||||
|
||||
if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
|
||||
ret = -EINVAL;
|
||||
ret = -EOPNOTSUPP;
|
||||
goto done;
|
||||
}
|
||||
|
||||
@@ -419,7 +468,6 @@ int nv_drm_gem_export_nvkms_memory_ioctl(struct drm_device *dev,
|
||||
}
|
||||
|
||||
if ((nv_nvkms_memory = nv_drm_gem_object_nvkms_memory_lookup(
|
||||
dev,
|
||||
filep,
|
||||
p->handle)) == NULL) {
|
||||
ret = -EINVAL;
|
||||
@@ -456,12 +504,11 @@ int nv_drm_gem_alloc_nvkms_memory_ioctl(struct drm_device *dev,
|
||||
struct drm_nvidia_gem_alloc_nvkms_memory_params *p = data;
|
||||
struct nv_drm_gem_nvkms_memory *nv_nvkms_memory = NULL;
|
||||
struct NvKmsKapiMemory *pMemory;
|
||||
enum NvKmsSurfaceMemoryLayout layout;
|
||||
enum NvKmsKapiAllocationType type;
|
||||
struct NvKmsKapiAllocateMemoryParams allocParams = { };
|
||||
int ret = 0;
|
||||
|
||||
if (!drm_core_check_feature(dev, DRIVER_MODESET)) {
|
||||
ret = -EINVAL;
|
||||
ret = -EOPNOTSUPP;
|
||||
goto failed;
|
||||
}
|
||||
|
||||
@@ -477,25 +524,15 @@ int nv_drm_gem_alloc_nvkms_memory_ioctl(struct drm_device *dev,
|
||||
goto failed;
|
||||
}
|
||||
|
||||
layout = p->block_linear ?
|
||||
allocParams.layout = p->block_linear ?
|
||||
NvKmsSurfaceMemoryLayoutBlockLinear : NvKmsSurfaceMemoryLayoutPitch;
|
||||
type = (p->flags & NV_GEM_ALLOC_NO_SCANOUT) ?
|
||||
allocParams.type = (p->flags & NV_GEM_ALLOC_NO_SCANOUT) ?
|
||||
NVKMS_KAPI_ALLOCATION_TYPE_OFFSCREEN : NVKMS_KAPI_ALLOCATION_TYPE_SCANOUT;
|
||||
allocParams.size = p->memory_size;
|
||||
allocParams.useVideoMemory = nv_dev->hasVideoMemory;
|
||||
allocParams.compressible = &p->compressible;
|
||||
|
||||
if (nv_dev->hasVideoMemory) {
|
||||
pMemory = nvKms->allocateVideoMemory(nv_dev->pDevice,
|
||||
layout,
|
||||
type,
|
||||
p->memory_size,
|
||||
&p->compressible);
|
||||
} else {
|
||||
pMemory = nvKms->allocateSystemMemory(nv_dev->pDevice,
|
||||
layout,
|
||||
type,
|
||||
p->memory_size,
|
||||
&p->compressible);
|
||||
}
|
||||
|
||||
pMemory = nvKms->allocateMemory(nv_dev->pDevice, &allocParams);
|
||||
if (pMemory == NULL) {
|
||||
ret = -EINVAL;
|
||||
NV_DRM_DEV_LOG_ERR(nv_dev,
|
||||
@@ -529,14 +566,12 @@ static struct drm_gem_object *__nv_drm_gem_nvkms_prime_dup(
|
||||
{
|
||||
struct nv_drm_device *nv_dev = to_nv_device(dev);
|
||||
const struct nv_drm_device *nv_dev_src;
|
||||
const struct nv_drm_gem_nvkms_memory *nv_nvkms_memory_src;
|
||||
struct nv_drm_gem_nvkms_memory *nv_nvkms_memory;
|
||||
struct NvKmsKapiMemory *pMemory;
|
||||
|
||||
BUG_ON(nv_gem_src == NULL || nv_gem_src->ops != &nv_gem_nvkms_memory_ops);
|
||||
|
||||
nv_dev_src = to_nv_device(nv_gem_src->base.dev);
|
||||
nv_nvkms_memory_src = to_nv_nvkms_memory_const(nv_gem_src);
|
||||
|
||||
if ((nv_nvkms_memory =
|
||||
nv_drm_calloc(1, sizeof(*nv_nvkms_memory))) == NULL) {
|
||||
@@ -579,7 +614,6 @@ int nv_drm_dumb_map_offset(struct drm_file *file,
|
||||
int ret = -EINVAL;
|
||||
|
||||
if ((nv_nvkms_memory = nv_drm_gem_object_nvkms_memory_lookup(
|
||||
dev,
|
||||
file,
|
||||
handle)) == NULL) {
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
@@ -32,8 +32,15 @@
|
||||
struct nv_drm_gem_nvkms_memory {
|
||||
struct nv_drm_gem_object base;
|
||||
|
||||
/*
|
||||
* Lock to protect concurrent writes to physically_mapped, pPhysicalAddress,
|
||||
* and pWriteCombinedIORemapAddress.
|
||||
*
|
||||
* __nv_drm_gem_nvkms_map(), the sole writer, is structured such that
|
||||
* readers are not required to hold the lock.
|
||||
*/
|
||||
struct mutex map_lock;
|
||||
bool physically_mapped;
|
||||
|
||||
void *pPhysicalAddress;
|
||||
void *pWriteCombinedIORemapAddress;
|
||||
|
||||
@@ -65,12 +72,11 @@ static inline struct nv_drm_gem_nvkms_memory *to_nv_nvkms_memory_const(
|
||||
|
||||
static inline
|
||||
struct nv_drm_gem_nvkms_memory *nv_drm_gem_object_nvkms_memory_lookup(
|
||||
struct drm_device *dev,
|
||||
struct drm_file *filp,
|
||||
u32 handle)
|
||||
{
|
||||
struct nv_drm_gem_object *nv_gem =
|
||||
nv_drm_gem_object_lookup(dev, filp, handle);
|
||||
nv_drm_gem_object_lookup(filp, handle);
|
||||
|
||||
if (nv_gem != NULL && nv_gem->ops != &nv_gem_nvkms_memory_ops) {
|
||||
nv_drm_gem_object_unreference_unlocked(nv_gem);
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user