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| Author | SHA1 | Date | |
|---|---|---|---|
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bdcd6ec921 | ||
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cfdc1a1644 | ||
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c46a1b24d6 |
@@ -1,7 +1,7 @@
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# NVIDIA Linux Open GPU Kernel Module Source
|
||||
|
||||
This is the source release of the NVIDIA Linux open GPU kernel modules,
|
||||
version 540.4.0.
|
||||
version 540.5.0.
|
||||
|
||||
|
||||
## How to Build
|
||||
@@ -17,7 +17,7 @@ as root:
|
||||
|
||||
Note that the kernel modules built here must be used with GSP
|
||||
firmware and user-space NVIDIA GPU driver components from a corresponding
|
||||
540.4.0 driver release. This can be achieved by installing
|
||||
540.5.0 driver release. This can be achieved by installing
|
||||
the NVIDIA GPU driver from the .run file using the `--no-kernel-modules`
|
||||
option. E.g.,
|
||||
|
||||
@@ -180,7 +180,7 @@ software applications.
|
||||
## Compatible GPUs
|
||||
|
||||
The open-gpu-kernel-modules can be used on any Turing or later GPU
|
||||
(see the table below). However, in the 540.4.0 release,
|
||||
(see the table below). However, in the 540.5.0 release,
|
||||
GeForce and Workstation support is still considered alpha-quality.
|
||||
|
||||
To enable use of the open kernel modules on GeForce and Workstation GPUs,
|
||||
@@ -188,7 +188,7 @@ set the "NVreg_OpenRmEnableUnsupportedGpus" nvidia.ko kernel module
|
||||
parameter to 1. For more details, see the NVIDIA GPU driver end user
|
||||
README here:
|
||||
|
||||
https://us.download.nvidia.com/XFree86/Linux-x86_64/540.4.0/README/kernel_open.html
|
||||
https://us.download.nvidia.com/XFree86/Linux-x86_64/540.5.0/README/kernel_open.html
|
||||
|
||||
In the below table, if three IDs are listed, the first is the PCI Device
|
||||
ID, the second is the PCI Subsystem Vendor ID, and the third is the PCI
|
||||
|
||||
@@ -5,12 +5,12 @@ d13779dbbab1c776db15f462cd46b29f2c0f8c7c - Makefile
|
||||
5728867ce2e96b63b29367be6aa1c0e47bcafc8f - SECURITY.md
|
||||
6b73bf6a534ddc0f64e8ba88739381c3b7fb4b5c - nv-compiler.sh
|
||||
ac7f91dfb6c5c469d2d8196c6baebe46ede5aee0 - CHANGELOG.md
|
||||
fe4e34f7f517ffe6976a020c22fefcf24ec0c211 - README.md
|
||||
fb30136834a37c3b273df8352db5bcc1f46b3d7d - README.md
|
||||
ec5f1eb408e0b650158e0310fb1ddd8e9b323a6f - CONTRIBUTING.md
|
||||
af3ee56442f16029cb9b13537477c384226b22fc - CODE_OF_CONDUCT.md
|
||||
41123f5c3015f9a14cf35b7c75c5b720f5fbed07 - kernel-open/Kbuild
|
||||
e3d628e13e13e8f4b886c88d8b22adfbf3217a54 - kernel-open/Kbuild
|
||||
4f4410c3c8db46e5a98d7a35f7d909a49de6cb43 - kernel-open/Makefile
|
||||
4f39cccb3a96d6a8be929f524e48e673aaa0093f - kernel-open/conftest.sh
|
||||
3f1d791899ab2db1d55cc73ec56fc11c9bef67cb - kernel-open/conftest.sh
|
||||
0b1508742a1c5a04b6c3a4be1b48b506f4180848 - kernel-open/dkms.conf
|
||||
19a5da412ce1557b721b8550a4a80196f6162ba6 - kernel-open/common/inc/os_dsi_panel_props.h
|
||||
4750735d6f3b334499c81d499a06a654a052713d - kernel-open/common/inc/nv-caps.h
|
||||
@@ -33,6 +33,7 @@ d7ab0ee225361daacd280ff98848851933a10a98 - kernel-open/common/inc/nv-list-helper
|
||||
b02c378ac0521c380fc2403f0520949f785b1db6 - kernel-open/common/inc/nv-dmabuf.h
|
||||
689d6be9302d488000e57a329373feeb14e93798 - kernel-open/common/inc/nv-procfs-utils.h
|
||||
b417d06ed1845f5ed69181d8eb9de6b6a87fa973 - kernel-open/common/inc/nv-firmware.h
|
||||
d5253e7e4abd3ad8d72375260aa80037adcd8973 - kernel-open/common/inc/nv_dpy_id.h
|
||||
a69cfed9725a8ade97036a1cb795e9144be1836d - kernel-open/common/inc/nv-platform.h
|
||||
b986bc6591ba17a74ad81ec4c93347564c6d5165 - kernel-open/common/inc/nvkms-format.h
|
||||
fa267c903e9c449e62dbb6945906400d43417eff - kernel-open/common/inc/nvlimits.h
|
||||
@@ -53,12 +54,13 @@ d25291d32caef187daf3589ce4976e4fa6bec70d - kernel-open/common/inc/nv-time.h
|
||||
4856fe869a5f3141e5d7f7d1b0a6affad94cbc31 - kernel-open/common/inc/nv-pci.h
|
||||
95bf694a98ba78d5a19e66463b8adda631e6ce4c - kernel-open/common/inc/nvstatus.h
|
||||
b15c5fe5d969414640a2cb374b707c230e7597e4 - kernel-open/common/inc/nv-hash.h
|
||||
23e71bf8f57bc6777ee6ee419dfdd44d7a2a3c6e - kernel-open/common/inc/nvkms-kapi.h
|
||||
61a60660761e90aa622af2fda482d69473ab40d4 - kernel-open/common/inc/nvkms-kapi.h
|
||||
f428218ee6f5d0289602495a1cfb287db4fb0823 - kernel-open/common/inc/nv_uvm_interface.h
|
||||
1e7eec6561b04d2d21c3515987aaa116e9401c1f - kernel-open/common/inc/nv-kernel-interface-api.h
|
||||
1e9c09285aabbfd1010e786f08494cba36658a0d - kernel-open/common/inc/nvkms-api-types.h
|
||||
b3d26ddf643e0bd98847ee56b930c14d06cadf89 - kernel-open/common/inc/nvkms-api-types.h
|
||||
c9120c6a33932c7514608601f82ea85d2386b84f - kernel-open/common/inc/os-interface.h
|
||||
ceac0fe7333f3a67b8fb63de42ab567dd905949f - kernel-open/common/inc/nv-ioctl-numa.h
|
||||
995d8447f8539bd736cc09d62983ae8ebc7e3436 - kernel-open/common/inc/nv_common_utils.h
|
||||
c75bfc368c6ce3fc2c1a0c5062834e90d822b365 - kernel-open/common/inc/nv-memdbg.h
|
||||
1d17329caf26cdf931122b3c3b7edf4932f43c38 - kernel-open/common/inc/nv-msi.h
|
||||
3b12d770f8592b94a8c7774c372e80ad08c5774c - kernel-open/common/inc/nvi2c.h
|
||||
@@ -85,7 +87,7 @@ cf90d9ea3abced81d182ab3c4161e1b5d3ad280d - kernel-open/nvidia/nv-rsync.h
|
||||
d68af9144d3d487308e73d0a52f4474f8047d6ca - kernel-open/nvidia/nv-gpio.c
|
||||
fc22bea3040ae178492cb9c7a62f1d0012b1c113 - kernel-open/nvidia/nv-procfs.c
|
||||
aa6cf0ed774330e4afe4eaa55b3463ed31a2f7ae - kernel-open/nvidia/nv.c
|
||||
e0aff92ee8ddec261d8f0d81c41f837503c4b571 - kernel-open/nvidia/nv-dsi-parse-panel-props.c
|
||||
6047676c00c8396d7c9f5192b873377a42bb8988 - kernel-open/nvidia/nv-dsi-parse-panel-props.c
|
||||
9104dc5f36a825aaf1208b54b167965625d4a433 - kernel-open/nvidia/nv_uvm_interface.c
|
||||
fbae5663e3c278d8206d07ec6446ca4c2781795f - kernel-open/nvidia/nv-ibmnpu.h
|
||||
ab04c42e0e8e7f48f1a7074885278bbb6006d65f - kernel-open/nvidia/nv-bpmp.c
|
||||
@@ -113,7 +115,7 @@ c7f1aaa6a5f3a3cdf1e5f80adf40b3c9f185fb94 - kernel-open/nvidia/nv-report-err.c
|
||||
dd9e367cba9e0672c998ec6d570be38084a365ab - kernel-open/nvidia/libspdm_rand.c
|
||||
37654472e65659be229b5e35c6f25c0724929511 - kernel-open/nvidia/nv-frontend.c
|
||||
8f87a475c202458948025d1521968677fc11dd50 - kernel-open/nvidia/nv-msi.c
|
||||
6084c207652ea4bc02a6c94275cad00880acc059 - kernel-open/nvidia/nv-platform.c
|
||||
45cdfeaf7b31b7891b19840f17a996b382806f1c - kernel-open/nvidia/nv-platform.c
|
||||
dd819a875c584bc469082fcf519779ea00b1d952 - kernel-open/nvidia/libspdm_aead_aes_gcm.c
|
||||
69f203ad21e643f7b7c85e7e86bd4b674a3536de - kernel-open/nvidia/nv-acpi.c
|
||||
cf98395acb4430a7c105218f7a4b5f7e810b39cf - kernel-open/nvidia/os-registry.c
|
||||
@@ -126,7 +128,7 @@ cf98395acb4430a7c105218f7a4b5f7e810b39cf - kernel-open/nvidia/os-registry.c
|
||||
9883eb32e5d4377c3dce1c7cb54d0e05c05e128b - kernel-open/nvidia/nv-mmap.c
|
||||
68d781e929d103e6fa55fa92b5d4f933fbfb6526 - kernel-open/nvidia/nv-report-err.h
|
||||
95ae148b016e4111122c2d9f8f004b53e78998f3 - kernel-open/nvidia/nv-memdbg.c
|
||||
af3ddc5641076d1618e5a0d5dcc16c63a3d7d011 - kernel-open/nvidia/nvidia.Kbuild
|
||||
4de56ccb102fd148feaaa08002db0a5ea129a61a - kernel-open/nvidia/nvidia.Kbuild
|
||||
6060392eec4e707ac61ebca3995b6a966eba7fc1 - kernel-open/nvidia/nv-p2p.h
|
||||
7b1bd10726481626dd51f4eebb693794561c20f6 - kernel-open/nvidia/nv-host1x.c
|
||||
11778961efc78ef488be5387fa3de0c1b761c0d9 - kernel-open/nvidia/libspdm_sha.c
|
||||
@@ -153,7 +155,7 @@ d5ddc354e191d6178625b0df8e8b34e8c3e4c474 - kernel-open/nvidia/library/spdm_lib_c
|
||||
8b2063f0cc2e328f4f986c2ce556cfb626c89810 - kernel-open/nvidia-drm/nvidia-drm-utils.c
|
||||
6d65ea9f067e09831a8196022bfe00a145bec270 - kernel-open/nvidia-drm/nvidia-drm-gem-dma-buf.h
|
||||
f454b9ae53a2c308d6909d197c2b9a6543f7d8c3 - kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.c
|
||||
69f2ad23a2df1e20a38c60d251673db8bffcbd9e - kernel-open/nvidia-drm/nvidia-drm-modeset.c
|
||||
e1895532cf6ec0edc4b73eb169b33b8477151364 - kernel-open/nvidia-drm/nvidia-drm-modeset.c
|
||||
23586447526d9ffedd7878b6cf5ba00139fadb5e - kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.h
|
||||
99642b76e9a84b5a1d2e2f4a8c7fb7bcd77a44fd - kernel-open/nvidia-drm/nvidia-drm.h
|
||||
66b33e4ac9abe09835635f6776c1222deefad741 - kernel-open/nvidia-drm/nvidia-drm-fb.h
|
||||
@@ -163,37 +165,37 @@ ae6efc1bbec8a5e948b7244f4801f0b4b398f203 - kernel-open/nvidia-drm/nvidia-drm.c
|
||||
86666530006fc4446d7e3bbe175ce9d3350d8d81 - kernel-open/nvidia-drm/nvidia-drm-ioctl.h
|
||||
511ea7cd9e7778c6adc028ae13377c1a8856b72a - kernel-open/nvidia-drm/nvidia-drm-format.c
|
||||
aedc8183ac255b270f74899cf9fd1c974fdbf00b - kernel-open/nvidia-drm/nvidia-drm-drv.h
|
||||
624b30dc76058cc3a0797a86ffa5da46803e3ace - kernel-open/nvidia-drm/nvidia-drm-connector.h
|
||||
3a1e3e14eeda27330da9fb54f798556994b8953e - kernel-open/nvidia-drm/nvidia-drm-connector.h
|
||||
646e6b03521587cc1a02617afd697183e5d1a83a - kernel-open/nvidia-drm/nv-kthread-q.c
|
||||
d9221522e02e18b037b8929fbc075dc3c1e58654 - kernel-open/nvidia-drm/nv-pci-table.c
|
||||
eb98761cdc99141ad937966e5533c57189db376a - kernel-open/nvidia-drm/nvidia-drm-fence.h
|
||||
eca70b3b8146903ec678a60eebb0462e6ccf4569 - kernel-open/nvidia-drm/nvidia-drm-encoder.h
|
||||
b1bc97e6e0564f1526dedaf8bb68d081fc509cc7 - kernel-open/nvidia-drm/nvidia-drm-helper.h
|
||||
6dfbbc39799b6578fb1f16357e8e29c14dcf455a - kernel-open/nvidia-drm/nvidia-drm-encoder.h
|
||||
2529ef49fee3a01717aaabea530d94017d5c31cc - kernel-open/nvidia-drm/nvidia-drm-helper.h
|
||||
2a48c9643c836a1b0a0c133afa9439b4f5ce0feb - kernel-open/nvidia-drm/nvidia-drm-os-interface.h
|
||||
b83e4c3ba825a75233eaedb0ac33feed74a53ab7 - kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.c
|
||||
77339943a9d60e01708aae95c258476831f0b8fb - kernel-open/nvidia-drm/nvidia-drm-drv.c
|
||||
21c629706f242599f6a81380155dd00bb0d994e7 - kernel-open/nvidia-drm/nvidia-drm-drv.c
|
||||
203295380efca7e422746805437b05ce22505424 - kernel-open/nvidia-drm/nvidia-drm-gem.c
|
||||
c1a318e90decef16aa29768ea5c8946becc5a4a0 - kernel-open/nvidia-drm/nvidia-drm-encoder.c
|
||||
cd987993109f7c020e296bf397905190a866d4ff - kernel-open/nvidia-drm/nvidia-drm-encoder.c
|
||||
8bedc7374d7a43250e49fb09139c511b489d45e3 - kernel-open/nvidia-drm/nv-pci-table.h
|
||||
044071d60c8cc8ea66c6caaf1b70fe01c4081ad3 - kernel-open/nvidia-drm/nvidia-drm-conftest.h
|
||||
9df641d3a2ee920c4fc68bfe19e8a11b085af03b - kernel-open/nvidia-drm/nvidia-drm-conftest.h
|
||||
ec550cba2bebff2c5054b6e12fc43d81e37ade48 - kernel-open/nvidia-drm/nvidia-dma-fence-helper.h
|
||||
e362c64aa67b47becdbf5c8ba2a245e135adeedf - kernel-open/nvidia-drm/nvidia-drm-gem-dma-buf.c
|
||||
492a1b0b02dcd2d60f05ac670daeeddcaa4b0da5 - kernel-open/nvidia-drm/nvidia-dma-resv-helper.h
|
||||
b59e4cccbc405babf7cf230455b5b089e81b03bc - kernel-open/nvidia-drm/nvidia-drm-connector.c
|
||||
05d56aa5e69b2332dba36ed15703865533976681 - kernel-open/nvidia-drm/nvidia-drm-connector.c
|
||||
97b6c56b1407de976898e0a8b5a8f38a5211f8bb - kernel-open/nvidia-drm/nvidia-drm-format.h
|
||||
6859a86572262b38ae7a905f21921e9ceb74523d - kernel-open/nvidia-drm/nvidia-drm-priv.h
|
||||
62b38738a83f67d0ea336cfadff1db5a5eaa8521 - kernel-open/nvidia-drm/nvidia-drm-priv.h
|
||||
deb00fa4d1de972d93d8e72355d81ba87044c86f - kernel-open/nvidia-drm/nvidia-drm-fence.c
|
||||
8a8b431f45bd0fe477759c1527d792cb9a1fa3f5 - kernel-open/nvidia-drm/nvidia-drm-gem.h
|
||||
1b7c0e4bc236101b930a9a95a622c0031c56978d - kernel-open/nvidia-drm/nvidia-drm-modeset.h
|
||||
7ba9a7661d0227a2f8a8b96614e40302dfcd8c37 - kernel-open/nvidia-drm/nvidia-drm.Kbuild
|
||||
fa3bcbf2d4b25dc6e2337bcd9d04b0c1413be3da - kernel-open/nvidia-drm/nvidia-drm.Kbuild
|
||||
40b5613d1fbbe6b74bff67a5d07974ad321f75f0 - kernel-open/nvidia-drm/nvidia-drm-utils.h
|
||||
8da06bd922850e840c94ed380e3b92c63aecbf70 - kernel-open/nvidia-drm/nvidia-drm-fb.c
|
||||
53f37dd6d99d4bc8227db5d532e2f1309723468b - kernel-open/nvidia-drm/nvidia-drm-crtc.c
|
||||
71560a9be3b3c2cd1c85f5d781524aadb6869eed - kernel-open/nvidia-drm/nvidia-drm-crtc.c
|
||||
372ea4c8e7bbc0bdeb899e6f163c8f20c663ad22 - kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h
|
||||
e02497b93f0f13d8e1624ff2effe417ec63bc2b0 - kernel-open/nvidia-modeset/nvidia-modeset-linux.c
|
||||
0a0650835e8835d32418891a2fd25031f5d8770e - kernel-open/nvidia-modeset/nvkms.h
|
||||
646e6b03521587cc1a02617afd697183e5d1a83a - kernel-open/nvidia-modeset/nv-kthread-q.c
|
||||
7dbe6f8405e47c1380c6151c7c7d12b0b02ef7f4 - kernel-open/nvidia-modeset/nvidia-modeset.Kbuild
|
||||
180e72402720a8cc52eb3c0354723a5db3a3bcd3 - kernel-open/nvidia-modeset/nvidia-modeset.Kbuild
|
||||
2ea1436104463c5e3d177e8574c3b4298976d37e - kernel-open/nvidia-modeset/nvkms-ioctl.h
|
||||
36f9753dbbef7dd5610312d5b14bffac1a93cee4 - nouveau/nouveau_firmware_layout.ods
|
||||
7ad4bb8aebd57a9be26329a611b14c5a70ccf2b7 - nouveau/extract-firmware-nouveau.py
|
||||
@@ -381,7 +383,7 @@ d2992c1a9aac5b1b5cfefcca72e9a2401190158c - src/common/sdk/nvidia/inc/ctrl/ctrl00
|
||||
456707a5de78815fc6a33f2da7e2a2a45ccc4884 - src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073internal.h
|
||||
abed22b35137e2d40399eb4ed01724aa789cb635 - src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h
|
||||
505860d3cd6f7d5144f97195b9fb32dd5b8f74aa - src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
|
||||
51cbe71bafc97e853c2b75147d7e9cb5cf72cefa - src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
|
||||
f32b4e3e8efc0b39538df2b141e3e8845eed553c - src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
|
||||
8e807c3771f3d37885d4066d95ec71c05234b5ec - src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
|
||||
52f251090780737f14eb993150f3ae73be303921 - src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h
|
||||
77eb4fab61225663a3f49b868c983d5d532ca184 - src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h
|
||||
@@ -490,7 +492,7 @@ e670ffdd499c13e5025aceae5541426ab2ab0925 - src/common/inc/gps.h
|
||||
5257e84f2048b01258c78cec70987f158f6b0c44 - src/common/inc/nvlog_inc.h
|
||||
b58ed1b4372a5c84d5f3755b7090b196179a2729 - src/common/inc/nv_speculation_barrier.h
|
||||
d877f4b99ae7d18cc5c78b85e89c0a7e3f3e8418 - src/common/inc/nvPNPVendorIds.h
|
||||
cd9253d1a83b171ca5aa514bc24ac87f2f9af961 - src/common/inc/nvUnixVersion.h
|
||||
6e212afa22e8348eedf1b15bd4bd7f7fd698c3b2 - src/common/inc/nvUnixVersion.h
|
||||
1fc95a17ddb619570063f6707d6a395684bfa884 - src/common/inc/displayport/dpcd20.h
|
||||
90998aac8685a403fdec9ff875f7436373d76f71 - src/common/inc/displayport/dpcd14.h
|
||||
669268ea1660e9e5b876f90da003599ba01356bb - src/common/inc/displayport/displayport.h
|
||||
@@ -536,7 +538,7 @@ cd9d3f57a9212166eba32b25cebc866a8d5bc026 - src/common/displayport/inc/dp_qse.h
|
||||
72711e7f688ee25510fca0e7eef6a4a99bb0aff3 - src/common/displayport/inc/dp_linkconfig.h
|
||||
e02e5621eaea52a2266a86dcd587f4714680caf4 - src/common/displayport/inc/dp_linkedlist.h
|
||||
2067e2ca3b86014c3e6dfc51d6574d87ae12d907 - src/common/displayport/inc/dp_timer.h
|
||||
c953ceae3005d389fb0873d8c3cc3783c7b2d885 - src/common/displayport/inc/dp_connectorimpl.h
|
||||
5a0d4df6d025eb24ae8af408416378d1e9e2f17a - src/common/displayport/inc/dp_connectorimpl.h
|
||||
4a445c98d9541a53f77af2ffa154501793c01fe4 - src/common/displayport/inc/dp_connector.h
|
||||
660ba146cf1242947eac3e2ded50ef4387ca8f35 - src/common/displayport/inc/dp_messagecodings.h
|
||||
df11366a5bcfb641025f12cddf9b5e8c2ed008de - src/common/displayport/inc/dp_watermark.h
|
||||
@@ -548,7 +550,7 @@ d199166ebfe00628b9c4894a97c3bb9f09d355e5 - src/common/displayport/src/dp_message
|
||||
aa2e56f6c66bf91c2b4a6030de2d29480f69710e - src/common/displayport/src/dp_wardatabase.cpp
|
||||
de264916d0e3e873a4c624f237ea228469d0a980 - src/common/displayport/src/dp_watermark.cpp
|
||||
e874ffeaeb6deec57605bf91eaa2af116a9762bd - src/common/displayport/src/dp_bitstream.cpp
|
||||
f3d79cc73199a2250ac8219f0a696512f4e67d63 - src/common/displayport/src/dp_evoadapter.cpp
|
||||
6b2384144feb749a974ca794ff74031e13ed6610 - src/common/displayport/src/dp_evoadapter.cpp
|
||||
56ee9318a7b51a04baa1d25d7d9a798c733dc1bc - src/common/displayport/src/dp_vrr.cpp
|
||||
d991afdb694634e9df756184b5951739fc3fd0ab - src/common/displayport/src/dp_auxretry.cpp
|
||||
554e6b7dadbb68ac0f3d2e368ca3fd90832ea254 - src/common/displayport/src/dp_discovery.cpp
|
||||
@@ -556,12 +558,12 @@ d991afdb694634e9df756184b5951739fc3fd0ab - src/common/displayport/src/dp_auxretr
|
||||
719d2ddbfb8555636496cb5dd74ee6776059db92 - src/common/displayport/src/dp_timer.cpp
|
||||
1923346b4f1209a8ceaf30d240f1b05717149be4 - src/common/displayport/src/dp_deviceimpl.cpp
|
||||
98cec6b663cf630c789e9823675cbb4948e1ba5e - src/common/displayport/src/dp_edid.cpp
|
||||
6a27fd2443690afb573116c13d3f976348dee298 - src/common/displayport/src/dp_groupimpl.cpp
|
||||
9fc1b9ae59805ea96879de1960149398bfe8dccd - src/common/displayport/src/dp_groupimpl.cpp
|
||||
e10ed809c1ddb7e67f0d7caf88802f291c8567ef - src/common/displayport/src/dp_qse.cpp
|
||||
4803cde0fffcf89fed46d6deaeba5c96c669a908 - src/common/displayport/src/dp_messageheader.cpp
|
||||
9f31213ab8037d7bb18c96a67d2630d61546544a - src/common/displayport/src/dp_mst_edid.cpp
|
||||
f56f92e32710b0342805b785d34ba1a9f2a54ed3 - src/common/displayport/src/dp_guid.cpp
|
||||
b487eed6e639a1aa485b06255beef61e112f24b3 - src/common/displayport/src/dp_connectorimpl.cpp
|
||||
656cf635f5268df416d746378d25e773bde24758 - src/common/displayport/src/dp_connectorimpl.cpp
|
||||
f83b3c17e9f26651f12c8835a682abdd66aed3a2 - src/common/displayport/src/dp_splitter.cpp
|
||||
1543bbaba8f3e149239cf44be3c0d080c624d5ba - src/common/displayport/src/dp_buffer.cpp
|
||||
fa4f4869d3d63c0180f30ae3736600a6627284c6 - src/common/displayport/src/dp_merger.cpp
|
||||
@@ -747,7 +749,7 @@ b459db8ccf299f7bda0fa9fa18ef1e3aeb2996eb - src/nvidia/generated/g_gpu_user_share
|
||||
a1bfb789c1e23bac2b7a31255b7d738e40a290f2 - src/nvidia/generated/g_mem_nvoc.h
|
||||
fc7f913eab7ef26b877606e0593928784c3121ec - src/nvidia/generated/g_device_nvoc.c
|
||||
d960a819d29d7e968eaab0e7a29897426b7ba646 - src/nvidia/generated/g_io_vaspace_nvoc.h
|
||||
261e6dfca63b12cb12e97a2f0c4447a3954dbe0a - src/nvidia/generated/g_rpc-structures.h
|
||||
4931d4e65a7efb4c60f03ff13841e1740d4fbcae - src/nvidia/generated/g_rpc-structures.h
|
||||
b9f25e208f5ea6f566dbd9cbcaaa30cd0786c31b - src/nvidia/generated/g_client_nvoc.h
|
||||
9b0d4695e84ec959790dd553944cb44685c5c251 - src/nvidia/generated/g_event_nvoc.h
|
||||
10645f82dd031d0aa6f4a3dfc039ef776f2fdee9 - src/nvidia/generated/g_hal_nvoc.h
|
||||
@@ -777,7 +779,7 @@ c2eae693c1b8d8502db368048f3b1c45d0576dc5 - src/nvidia/generated/g_chips2halspec_
|
||||
0097015ef25011bee849966ef5248d206ab0f816 - src/nvidia/generated/g_gpu_resource_nvoc.h
|
||||
b18ed7a5d71571b57266995f0d30317814e8bd6e - src/nvidia/generated/g_gpu_access_nvoc.h
|
||||
81f915ae199df67c1884bfc18f3d23f20941af6a - src/nvidia/generated/g_dce_client_nvoc.c
|
||||
87510f9f25364673fedfd1d820aedc85852ef5df - src/nvidia/generated/g_rpc-message-header.h
|
||||
436c2b21a6d67fed4167b749fd79b85e073d9512 - src/nvidia/generated/g_rpc-message-header.h
|
||||
dad5def7d6c24268ac1e1a75038cbf33900745ff - src/nvidia/generated/g_binary_api_nvoc.h
|
||||
35889e5f6bdc996fa95c76d05e7b8902328d450b - src/nvidia/generated/g_rs_client_nvoc.h
|
||||
92c99fd64caa9f78664ed1fd54313ee82e2cf9c7 - src/nvidia/generated/g_disp_channel_nvoc.h
|
||||
@@ -829,7 +831,7 @@ bdb198b18c700dc396f73191a8e696d106a1f716 - src/nvidia/generated/g_resource_nvoc.
|
||||
c1652e6cc404f23660ee440b61c6d0b9149ff593 - src/nvidia/generated/g_gpu_resource_nvoc.c
|
||||
aac0c7df733e179f2a5906ab66b302a5bee82cbe - src/nvidia/generated/g_gpu_db_nvoc.h
|
||||
09597f23d6a5440258656be81e7e6709390128f8 - src/nvidia/generated/g_hal_private.h
|
||||
5274a731ecccd2ad0e57761831523e25cd742676 - src/nvidia/generated/g_sdk-structures.h
|
||||
00757a3a6c876b01e3232b301a120131f194acd5 - src/nvidia/generated/g_sdk-structures.h
|
||||
b35821f54f7ec965edd25a60e58d7639cd19df19 - src/nvidia/generated/g_hal_archimpl.h
|
||||
f5ad33480e2b73c6ff2bfd586e027f19318a597c - src/nvidia/generated/g_disp_console_mem_nvoc.h
|
||||
af86a67a1c33acc193efa6dba8bc46ebe5dbb5eb - src/nvidia/generated/g_gpu_class_list.c
|
||||
@@ -1180,7 +1182,7 @@ d81ef382635d0c4de47dfa3d709e0702f371ceb7 - src/nvidia/interface/rmapi/src/g_finn
|
||||
c3ab6005d7083e90145cac66addf815c4f93d9a0 - src/nvidia-modeset/lib/nvkms-format.c
|
||||
b8854261256a801af52d1201081afa9c17486a96 - src/nvidia-modeset/include/nvkms-3dvision.h
|
||||
ebafc51b2b274cd1818e471850a5efa9618eb17d - src/nvidia-modeset/include/nvkms-prealloc.h
|
||||
0739ffa368efb761544295c03bc0ad633b5a3349 - src/nvidia-modeset/include/nvkms-flip-workarea.h
|
||||
712798f7ead59ecab66551630967fe54472f2f9f - src/nvidia-modeset/include/nvkms-flip-workarea.h
|
||||
fa829f1cd3b73f194f39879c48962b703f640b65 - src/nvidia-modeset/include/nvkms-vrr.h
|
||||
49af4a8fa95d0e595deacadbca5360f097722e7f - src/nvidia-modeset/include/nvkms-evo1.h
|
||||
496b94af536dd912866a05f7b2da53050b50c2f5 - src/nvidia-modeset/include/nvkms-prealloc-types.h
|
||||
@@ -1193,7 +1195,7 @@ a79cfb74026085b0aa612c0ae6789083e196bbc2 - src/nvidia-modeset/include/nvkms-evo-
|
||||
6e3681d5caa36312804c91630eaaf510eda897d2 - src/nvidia-modeset/include/nvkms-dma.h
|
||||
eb5248c4b0b51e7aecd2de87e496253b3b235c70 - src/nvidia-modeset/include/nvkms-utils-flip.h
|
||||
377dd4a29b2ea5937a9b8fc3fba0c9e4ef92992e - src/nvidia-modeset/include/nvkms-cursor.h
|
||||
ec1374d339746b73bc7c7614695fde68c156074a - src/nvidia-modeset/include/nvkms-rm.h
|
||||
7347dc4c3d89053efaac4e7c64fb35cfdeaf305a - src/nvidia-modeset/include/nvkms-rm.h
|
||||
0449c65467d54097b65d60eec670450b126b07c1 - src/nvidia-modeset/include/nvkms-modeset.h
|
||||
be6e0e97c1e7ffc0daa2f14ef7b05b9f9c11dc16 - src/nvidia-modeset/include/nvkms-attributes.h
|
||||
07ac47b52b1b42c143501c4a95a88a3f86f5be03 - src/nvidia-modeset/include/nvkms-hdmi.h
|
||||
@@ -1202,15 +1204,15 @@ c90e4393f568d96bc98cb52a93bfc3fdea10658d - src/nvidia-modeset/include/nvkms-mode
|
||||
ae03509966df56d98fa72b7528ab43ec2b258381 - src/nvidia-modeset/include/nvkms-utils.h
|
||||
f5f3b11c78a8b0eef40c09e1751615a47f516edb - src/nvidia-modeset/include/nvkms-hal.h
|
||||
d05ef9a837f2927fe387e7d157ea76c7ef567807 - src/nvidia-modeset/include/nvkms-lut.h
|
||||
1b75646c99c748f9070208eb58f0082812eabbd9 - src/nvidia-modeset/include/nvkms-private.h
|
||||
2b720811867a06d24b22f03d098fe6d9fea423a0 - src/nvidia-modeset/include/nvkms-private.h
|
||||
6fa4708e4f6dfe63f149a1c70fa84bf9df01026a - src/nvidia-modeset/include/nvkms-evo.h
|
||||
4a94381bd8c24b09193577d3f05d6d61f178e1cf - src/nvidia-modeset/include/nvkms-ctxdma.h
|
||||
11bae7c491bbb0ba4cad94b645d47c384191fa5c - src/nvidia-modeset/include/nvkms-flip.h
|
||||
00d2f2fa1f7c96757f67b9ca3ff1c2699a493bd0 - src/nvidia-modeset/include/nvkms-modeset-types.h
|
||||
260b6ef87c755e55a803adad4ce49f2d57315f9a - src/nvidia-modeset/include/nvkms-event.h
|
||||
4f85782f39355e10576f21bee44a942c9317664c - src/nvidia-modeset/include/nvkms-event.h
|
||||
35fa1444c57f7adbbddddc612237f3ad38cdd78f - src/nvidia-modeset/include/nvkms-rmapi.h
|
||||
118d0ea84ff81de16fbdc2c7daf249ee5c82ed6e - src/nvidia-modeset/include/nvkms-modepool.h
|
||||
62be8578b3eec01438014f11a1b1b210b09d6ce6 - src/nvidia-modeset/include/nvkms-types.h
|
||||
fd0c300efa7a76783847cfc809242d304fe4435c - src/nvidia-modeset/include/nvkms-types.h
|
||||
4a33d410f090fd4f4dfc9a6de285f8e8fb1c9ced - src/nvidia-modeset/include/nvkms-surface.h
|
||||
b0d407b0413453ec71481f84cc448d090b90d609 - src/nvidia-modeset/include/nvkms-evo3.h
|
||||
8c7e0e15c1038fe518e98d8f86fafb250b10a1d2 - src/nvidia-modeset/include/nvkms-stereo.h
|
||||
@@ -1221,19 +1223,19 @@ a8fbb7a071c0e7b326f384fed7547e7b6ec81c3e - src/nvidia-modeset/include/dp/nvdp-ti
|
||||
ae43c46687d16b93189047d9eeed933a67e5571f - src/nvidia-modeset/include/dp/nvdp-connector.h
|
||||
727bd77cfbc9ac4989c2ab7eec171ceb516510aa - src/nvidia-modeset/kapi/include/nvkms-kapi-notifiers.h
|
||||
d77e520819f0fa8a775542f493af03f9f2aafc47 - src/nvidia-modeset/kapi/include/nvkms-kapi-internal.h
|
||||
277738dc6ab009b77546355299cadabc5144fc5c - src/nvidia-modeset/kapi/src/nvkms-kapi.c
|
||||
ff51857b54672bd80d740213e9b20f35bcdeed89 - src/nvidia-modeset/kapi/src/nvkms-kapi.c
|
||||
01d943d6edb0c647c2b8dbc44460948665b03e7a - src/nvidia-modeset/kapi/src/nvkms-kapi-notifiers.c
|
||||
ce42ceac4c4cf9d249d66ab57ae2f435cd9623fc - src/nvidia-modeset/kapi/src/nvkms-kapi-sync.c
|
||||
80c2c9a2a05beb0202239db8b0dd7080ff21c194 - src/nvidia-modeset/kapi/interface/nvkms-kapi-private.h
|
||||
23e71bf8f57bc6777ee6ee419dfdd44d7a2a3c6e - src/nvidia-modeset/kapi/interface/nvkms-kapi.h
|
||||
61a60660761e90aa622af2fda482d69473ab40d4 - src/nvidia-modeset/kapi/interface/nvkms-kapi.h
|
||||
26144f7b6e9358a5418735c5c357c964047b52ca - src/nvidia-modeset/src/nvkms-modeset.c
|
||||
5f559582336ab0e252f25039d43b114a6630758c - src/nvidia-modeset/src/nvkms-evo.c
|
||||
aa185dd37a2ece9f7698c9076ec5c9fc79b6a476 - src/nvidia-modeset/src/nvkms-hw-flip.c
|
||||
7262999494048226f8a94492899609fbecd729d8 - src/nvidia-modeset/src/nvkms-hw-flip.c
|
||||
6a35b80a6995777dc9500cac9659e6f0f0c12d23 - src/nvidia-modeset/src/nvkms-cursor3.c
|
||||
4f973e22225946be9c5c726a06ea3ad915ec4a03 - src/nvidia-modeset/src/nvkms-rm.c
|
||||
7326c2e84f81abbe6d8df0ce2632a83682fbd5dc - src/nvidia-modeset/src/nvkms-rm.c
|
||||
30ad7839985dea46e6b6d43499210a3056da51ad - src/nvidia-modeset/src/nvkms-utils-flip.c
|
||||
6a84fae64ca00bc8b5d9ae75c291140f23d8fd4d - src/nvidia-modeset/src/nvkms-evo3.c
|
||||
c13871725cc47dfb99b3d66ed41a57d2ea5f8f97 - src/nvidia-modeset/src/nvkms-flip.c
|
||||
2ff0dded5029b1284268ee9358f576828d073285 - src/nvidia-modeset/src/nvkms-evo3.c
|
||||
0343d2f40978b0780b0dae54b22f366f723ff08e - src/nvidia-modeset/src/nvkms-flip.c
|
||||
3e723edf2a0a2f4f93032feb4aeaaf7fd0acddfa - src/nvidia-modeset/src/g_nvkms-evo-states.c
|
||||
761c8540278a1ffb9fe4aa0adb1b4ee95524787a - src/nvidia-modeset/src/nvkms-hal.c
|
||||
9e4d3e3505a84d8634a2ef2307628a8fe551a4c3 - src/nvidia-modeset/src/nvkms-surface.c
|
||||
@@ -1242,14 +1244,14 @@ bd2e4a6102432d4ac1faf92b5d3db29e9e3cfafc - src/nvidia-modeset/src/nvkms-utils.c
|
||||
9a8746ee4a4e772b8ac13f06dc0de8a250fdb4c7 - src/nvidia-modeset/src/nvkms-ctxdma.c
|
||||
e7a717712eb5f710df2c735013f27b0c03ae276c - src/nvidia-modeset/src/nvkms-hdmi.c
|
||||
2fa9d9b3cbeeb9406f2dd51a4f4a5d53844a31c9 - src/nvidia-modeset/src/nvkms-dpy.c
|
||||
d01a59a7c22d3998f1cf97f2812c6f99dab4c097 - src/nvidia-modeset/src/nvkms.c
|
||||
f92ae2b0ba77cf14cbe966a0c66fe6ca02a7e73e - src/nvidia-modeset/src/nvkms.c
|
||||
dff88ceaf95239b51b60af915f92e389bb844425 - src/nvidia-modeset/src/nvkms-cursor.c
|
||||
2b304663f2a005b5ccdecfafb69a3407f2feeb18 - src/nvidia-modeset/src/nvkms-evo2.c
|
||||
94e9c19b7b6a5e56fd46b0885e7dd6fe698fe2df - src/nvidia-modeset/src/nvkms-prealloc.c
|
||||
795ddaec1aa05d152eedd28a3bc82ca49e44a72f - src/nvidia-modeset/src/nvkms-attributes.c
|
||||
65b02b48caff2a9100b8c5614f91d42fb20da9c0 - src/nvidia-modeset/src/nvkms-dpy-override.c
|
||||
9fea40b7b55d6ebf3f73b5d469751c873ffbe7c0 - src/nvidia-modeset/src/nvkms-dma.c
|
||||
da726d20eea99a96af4c10aace88f419e8ee2a34 - src/nvidia-modeset/src/nvkms-event.c
|
||||
7e16c9cc7e4a9a8329347133663f29aaa4ec7446 - src/nvidia-modeset/src/nvkms-event.c
|
||||
2fabe1c14116a2b07f24d01710394ee84a6e3914 - src/nvidia-modeset/src/nvkms-3dvision.c
|
||||
3261fd9a1eb14f7f3fb0917757b1e2704d4abbd2 - src/nvidia-modeset/src/nvkms-hw-states.c
|
||||
c799d52bdc792efc377fb5cd307b0eb445c44d6a - src/nvidia-modeset/src/nvkms-cursor2.c
|
||||
@@ -1267,14 +1269,14 @@ f96cd982b4c05351faa31d04ac30d6fa7c866bcb - src/nvidia-modeset/src/dp/nvdp-timer.
|
||||
a90b2c295271631b4c3abe6afb8dfd92d6b429c8 - src/nvidia-modeset/src/dp/nvdp-connector.cpp
|
||||
535ce9f743903eb83a341eef1be812f4e4b50887 - src/nvidia-modeset/src/dp/nvdp-evo-interface.cpp
|
||||
c19775aebdaaaee3500378d47af6ff0b8eb486b8 - src/nvidia-modeset/src/dp/nvdp-device.cpp
|
||||
a2a4b7063fa903cc434163ebceb7c8d48f703c33 - src/nvidia-modeset/src/dp/nvdp-connector-event-sink.cpp
|
||||
98046832ecc2cad21e727fecf2b9626dd212d95c - src/nvidia-modeset/src/dp/nvdp-connector-event-sink.cpp
|
||||
51af3c1ee6b74ee0c9add3fb7d50cbc502980789 - src/nvidia-modeset/src/dp/nvdp-evo-interface.hpp
|
||||
110ac212ee8832c3fa3c4f45d6d33eed0301e992 - src/nvidia-modeset/src/dp/nvdp-host.cpp
|
||||
69fed95ab3954dd5cb26590d02cd8ba09cdff1ac - src/nvidia-modeset/src/dp/nvdp-connector-event-sink.hpp
|
||||
372ea4c8e7bbc0bdeb899e6f163c8f20c663ad22 - src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h
|
||||
0a0650835e8835d32418891a2fd25031f5d8770e - src/nvidia-modeset/os-interface/include/nvkms.h
|
||||
7987b3cd8d56be40767c76286d78cf5962cd166c - src/nvidia-modeset/interface/nvkms-api.h
|
||||
beebcd654ab4db41c38a2d2e9c1575415a0ed815 - src/nvidia-modeset/interface/nvkms-api.h
|
||||
b986bc6591ba17a74ad81ec4c93347564c6d5165 - src/nvidia-modeset/interface/nvkms-format.h
|
||||
2ea1436104463c5e3d177e8574c3b4298976d37e - src/nvidia-modeset/interface/nvkms-ioctl.h
|
||||
1e9c09285aabbfd1010e786f08494cba36658a0d - src/nvidia-modeset/interface/nvkms-api-types.h
|
||||
b3d26ddf643e0bd98847ee56b930c14d06cadf89 - src/nvidia-modeset/interface/nvkms-api-types.h
|
||||
8e3e74d2b3f45381e7b0012d930cf451cbd1728f - src/nvidia-modeset/interface/nvkms-sync.h
|
||||
|
||||
@@ -72,7 +72,7 @@ EXTRA_CFLAGS += -I$(src)/common/inc
|
||||
EXTRA_CFLAGS += -I$(src)
|
||||
EXTRA_CFLAGS += -Wall $(DEFINES) $(INCLUDES) -Wno-cast-qual -Wno-error -Wno-format-extra-args
|
||||
EXTRA_CFLAGS += -D__KERNEL__ -DMODULE -DNVRM
|
||||
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"540.4.0\"
|
||||
EXTRA_CFLAGS += -DNV_VERSION_STRING=\"540.5.0\"
|
||||
|
||||
ifneq ($(SYSSRCHOST1X),)
|
||||
EXTRA_CFLAGS += -I$(SYSSRCHOST1X)
|
||||
@@ -212,6 +212,8 @@ $(obj)/conftest/patches.h: $(NV_CONFTEST_SCRIPT)
|
||||
# corresponding #define will be generated in conftest/headers.h.
|
||||
NV_HEADER_PRESENCE_TESTS = \
|
||||
asm/system.h \
|
||||
drm/display/drm_hdcp.h \
|
||||
drm/display/drm_hdcp_helper.h \
|
||||
drm/drmP.h \
|
||||
drm/drm_aperture.h \
|
||||
drm/drm_auth.h \
|
||||
|
||||
120
kernel-open/common/inc/nv_common_utils.h
Normal file
120
kernel-open/common/inc/nv_common_utils.h
Normal file
@@ -0,0 +1,120 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#ifndef __NV_COMMON_UTILS_H__
|
||||
#define __NV_COMMON_UTILS_H__
|
||||
|
||||
#include "nvtypes.h"
|
||||
#include "nvmisc.h"
|
||||
|
||||
#if !defined(TRUE)
|
||||
#define TRUE NV_TRUE
|
||||
#endif
|
||||
|
||||
#if !defined(FALSE)
|
||||
#define FALSE NV_FALSE
|
||||
#endif
|
||||
|
||||
#define NV_IS_UNSIGNED(x) ((__typeof__(x))-1 > 0)
|
||||
|
||||
/* Get the length of a statically-sized array. */
|
||||
#define ARRAY_LEN(_arr) (sizeof(_arr) / sizeof(_arr[0]))
|
||||
|
||||
#define NV_INVALID_HEAD 0xFFFFFFFF
|
||||
|
||||
#define NV_INVALID_CONNECTOR_PHYSICAL_INFORMATION (~0)
|
||||
|
||||
#if !defined(NV_MIN)
|
||||
# define NV_MIN(a,b) (((a)<(b))?(a):(b))
|
||||
#endif
|
||||
|
||||
#define NV_MIN3(a,b,c) NV_MIN(NV_MIN(a, b), c)
|
||||
#define NV_MIN4(a,b,c,d) NV_MIN3(NV_MIN(a,b),c,d)
|
||||
|
||||
#if !defined(NV_MAX)
|
||||
# define NV_MAX(a,b) (((a)>(b))?(a):(b))
|
||||
#endif
|
||||
|
||||
#define NV_MAX3(a,b,c) NV_MAX(NV_MAX(a, b), c)
|
||||
#define NV_MAX4(a,b,c,d) NV_MAX3(NV_MAX(a,b),c,d)
|
||||
|
||||
static inline int NV_LIMIT_VAL_TO_MIN_MAX(int val, int min, int max)
|
||||
{
|
||||
if (val < min) {
|
||||
return min;
|
||||
}
|
||||
if (val > max) {
|
||||
return max;
|
||||
}
|
||||
return val;
|
||||
}
|
||||
|
||||
#define NV_ROUNDUP_DIV(x,y) ((x) / (y) + (((x) % (y)) ? 1 : 0))
|
||||
|
||||
/*
|
||||
* Macros used for computing palette entries:
|
||||
*
|
||||
* NV_UNDER_REPLICATE(val, source_size, result_size) expands a value
|
||||
* of source_size bits into a value of target_size bits by shifting
|
||||
* the source value into the high bits and replicating the high bits
|
||||
* of the value into the low bits of the result.
|
||||
*
|
||||
* PALETTE_DEPTH_SHIFT(val, w) maps a colormap entry for a component
|
||||
* that has w bits to an appropriate entry in a LUT of 256 entries.
|
||||
*/
|
||||
static inline unsigned int NV_UNDER_REPLICATE(unsigned short val,
|
||||
int source_size,
|
||||
int result_size)
|
||||
{
|
||||
return (val << (result_size - source_size)) |
|
||||
(val >> ((source_size << 1) - result_size));
|
||||
}
|
||||
|
||||
|
||||
static inline unsigned short PALETTE_DEPTH_SHIFT(unsigned short val, int depth)
|
||||
{
|
||||
return NV_UNDER_REPLICATE(val, depth, 8);
|
||||
}
|
||||
|
||||
/*
|
||||
* Use __builtin_ffs where it is supported, or provide an equivalent
|
||||
* implementation for platforms like riscv where it is not.
|
||||
*/
|
||||
#if defined(__GNUC__) && !NVCPU_IS_RISCV64
|
||||
static inline int nv_ffs(int x)
|
||||
{
|
||||
return __builtin_ffs(x);
|
||||
}
|
||||
#else
|
||||
static inline int nv_ffs(int x)
|
||||
{
|
||||
if (x == 0)
|
||||
return 0;
|
||||
|
||||
LOWESTBITIDX_32(x);
|
||||
|
||||
return 1 + x;
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* __NV_COMMON_UTILS_H__ */
|
||||
370
kernel-open/common/inc/nv_dpy_id.h
Normal file
370
kernel-open/common/inc/nv_dpy_id.h
Normal file
@@ -0,0 +1,370 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2010-2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
/*
|
||||
* This header file defines the types NVDpyId and NVDpyIdList, as well
|
||||
* as inline functions to manipulate these types. NVDpyId and
|
||||
* NVDpyIdList should be treated as opaque by includers of this header
|
||||
* file.
|
||||
*/
|
||||
|
||||
#ifndef __NV_DPY_ID_H__
|
||||
#define __NV_DPY_ID_H__
|
||||
|
||||
#include "nvtypes.h"
|
||||
#include "nvmisc.h"
|
||||
#include "nv_common_utils.h"
|
||||
#include <nvlimits.h> /* NV_MAX_SUBDEVICES */
|
||||
|
||||
typedef struct {
|
||||
NvU32 opaqueDpyId;
|
||||
} NVDpyId;
|
||||
|
||||
typedef struct {
|
||||
NvU32 opaqueDpyIdList;
|
||||
} NVDpyIdList;
|
||||
|
||||
#define NV_DPY_ID_MAX_SUBDEVICES NV_MAX_SUBDEVICES
|
||||
#define NV_DPY_ID_MAX_DPYS_IN_LIST 32
|
||||
|
||||
/*
|
||||
* For use in combination with nvDpyIdToPrintFormat(); e.g.,
|
||||
*
|
||||
* printf("dpy id: " NV_DPY_ID_PRINT_FORMAT "\n",
|
||||
* nvDpyIdToPrintFormat(dpyId));
|
||||
*
|
||||
* The includer should not make assumptions about the return type of
|
||||
* nvDpyIdToPrintFormat().
|
||||
*/
|
||||
#define NV_DPY_ID_PRINT_FORMAT "0x%08x"
|
||||
|
||||
/* functions to return an invalid DpyId and empty DpyIdList */
|
||||
|
||||
static inline NVDpyId nvInvalidDpyId(void)
|
||||
{
|
||||
NVDpyId dpyId = { 0 };
|
||||
return dpyId;
|
||||
}
|
||||
|
||||
static inline NVDpyIdList nvEmptyDpyIdList(void)
|
||||
{
|
||||
NVDpyIdList dpyIdList = { 0 };
|
||||
return dpyIdList;
|
||||
}
|
||||
|
||||
static inline NVDpyIdList nvAllDpyIdList(void)
|
||||
{
|
||||
NVDpyIdList dpyIdList = { ~0U };
|
||||
return dpyIdList;
|
||||
}
|
||||
|
||||
static inline void
|
||||
nvEmptyDpyIdListSubDeviceArray(NVDpyIdList dpyIdList[NV_DPY_ID_MAX_SUBDEVICES])
|
||||
{
|
||||
int dispIndex;
|
||||
for (dispIndex = 0; dispIndex < NV_DPY_ID_MAX_SUBDEVICES; dispIndex++) {
|
||||
dpyIdList[dispIndex] = nvEmptyDpyIdList();
|
||||
}
|
||||
}
|
||||
|
||||
/* set operations on DpyIds and DpyIdLists: Add, Subtract, Intersect, Xor */
|
||||
|
||||
static inline __attribute__ ((warn_unused_result))
|
||||
NVDpyIdList nvAddDpyIdToDpyIdList(NVDpyId dpyId, NVDpyIdList dpyIdList)
|
||||
{
|
||||
NVDpyIdList tmpDpyIdList;
|
||||
tmpDpyIdList.opaqueDpyIdList = dpyIdList.opaqueDpyIdList |
|
||||
dpyId.opaqueDpyId;
|
||||
return tmpDpyIdList;
|
||||
}
|
||||
|
||||
/* Passing an invalid display ID makes this function return an empty list. */
|
||||
static inline __attribute__ ((warn_unused_result))
|
||||
NVDpyIdList nvAddDpyIdToEmptyDpyIdList(NVDpyId dpyId)
|
||||
{
|
||||
NVDpyIdList tmpDpyIdList;
|
||||
tmpDpyIdList.opaqueDpyIdList = dpyId.opaqueDpyId;
|
||||
return tmpDpyIdList;
|
||||
}
|
||||
|
||||
static inline __attribute__ ((warn_unused_result))
|
||||
NVDpyIdList nvAddDpyIdListToDpyIdList(NVDpyIdList dpyIdListA,
|
||||
NVDpyIdList dpyIdListB)
|
||||
{
|
||||
NVDpyIdList tmpDpyIdList;
|
||||
tmpDpyIdList.opaqueDpyIdList = dpyIdListB.opaqueDpyIdList |
|
||||
dpyIdListA.opaqueDpyIdList;
|
||||
return tmpDpyIdList;
|
||||
}
|
||||
|
||||
/* Returns: dpyIdList - dpyId */
|
||||
static inline __attribute__ ((warn_unused_result))
|
||||
NVDpyIdList nvDpyIdListMinusDpyId(NVDpyIdList dpyIdList, NVDpyId dpyId)
|
||||
{
|
||||
NVDpyIdList tmpDpyIdList;
|
||||
tmpDpyIdList.opaqueDpyIdList = dpyIdList.opaqueDpyIdList &
|
||||
(~dpyId.opaqueDpyId);
|
||||
return tmpDpyIdList;
|
||||
}
|
||||
|
||||
/* Returns: dpyIdListA - dpyIdListB */
|
||||
static inline __attribute__ ((warn_unused_result))
|
||||
NVDpyIdList nvDpyIdListMinusDpyIdList(NVDpyIdList dpyIdListA,
|
||||
NVDpyIdList dpyIdListB)
|
||||
{
|
||||
NVDpyIdList tmpDpyIdList;
|
||||
tmpDpyIdList.opaqueDpyIdList = dpyIdListA.opaqueDpyIdList &
|
||||
(~dpyIdListB.opaqueDpyIdList);
|
||||
return tmpDpyIdList;
|
||||
}
|
||||
|
||||
static inline __attribute__ ((warn_unused_result))
|
||||
NVDpyIdList nvIntersectDpyIdAndDpyIdList(NVDpyId dpyId, NVDpyIdList dpyIdList)
|
||||
{
|
||||
NVDpyIdList tmpDpyIdList;
|
||||
tmpDpyIdList.opaqueDpyIdList = dpyIdList.opaqueDpyIdList &
|
||||
dpyId.opaqueDpyId;
|
||||
return tmpDpyIdList;
|
||||
}
|
||||
|
||||
static inline __attribute__ ((warn_unused_result))
|
||||
NVDpyIdList nvIntersectDpyIdListAndDpyIdList(NVDpyIdList dpyIdListA,
|
||||
NVDpyIdList dpyIdListB)
|
||||
{
|
||||
NVDpyIdList tmpDpyIdList;
|
||||
tmpDpyIdList.opaqueDpyIdList = dpyIdListA.opaqueDpyIdList &
|
||||
dpyIdListB.opaqueDpyIdList;
|
||||
return tmpDpyIdList;
|
||||
}
|
||||
|
||||
static inline __attribute__ ((warn_unused_result))
|
||||
NVDpyIdList nvXorDpyIdAndDpyIdList(NVDpyId dpyId, NVDpyIdList dpyIdList)
|
||||
{
|
||||
NVDpyIdList tmpDpyIdList;
|
||||
tmpDpyIdList.opaqueDpyIdList = dpyIdList.opaqueDpyIdList ^
|
||||
dpyId.opaqueDpyId;
|
||||
return tmpDpyIdList;
|
||||
}
|
||||
|
||||
static inline __attribute__ ((warn_unused_result))
|
||||
NVDpyIdList nvXorDpyIdListAndDpyIdList(NVDpyIdList dpyIdListA,
|
||||
NVDpyIdList dpyIdListB)
|
||||
{
|
||||
NVDpyIdList tmpDpyIdList;
|
||||
tmpDpyIdList.opaqueDpyIdList = dpyIdListA.opaqueDpyIdList ^
|
||||
dpyIdListB.opaqueDpyIdList;
|
||||
return tmpDpyIdList;
|
||||
}
|
||||
|
||||
|
||||
/* boolean checks */
|
||||
|
||||
static inline NvBool nvDpyIdIsInDpyIdList(NVDpyId dpyId,
|
||||
NVDpyIdList dpyIdList)
|
||||
{
|
||||
return !!(dpyIdList.opaqueDpyIdList & dpyId.opaqueDpyId);
|
||||
}
|
||||
|
||||
static inline NvBool nvDpyIdIsInvalid(NVDpyId dpyId)
|
||||
{
|
||||
return (dpyId.opaqueDpyId == 0);
|
||||
}
|
||||
|
||||
static inline NvBool nvDpyIdListIsEmpty(NVDpyIdList dpyIdList)
|
||||
{
|
||||
return (dpyIdList.opaqueDpyIdList == 0);
|
||||
}
|
||||
|
||||
static inline NvBool
|
||||
nvDpyIdListSubDeviceArrayIsEmpty(NVDpyIdList
|
||||
dpyIdList[NV_DPY_ID_MAX_SUBDEVICES])
|
||||
{
|
||||
int dispIndex;
|
||||
for (dispIndex = 0; dispIndex < NV_DPY_ID_MAX_SUBDEVICES; dispIndex++) {
|
||||
if (!nvDpyIdListIsEmpty(dpyIdList[dispIndex])) {
|
||||
return NV_FALSE;
|
||||
}
|
||||
}
|
||||
return NV_TRUE;
|
||||
}
|
||||
|
||||
|
||||
static inline NvBool nvDpyIdsAreEqual(NVDpyId dpyIdA, NVDpyId dpyIdB)
|
||||
{
|
||||
return (dpyIdA.opaqueDpyId == dpyIdB.opaqueDpyId);
|
||||
}
|
||||
|
||||
static inline NvBool nvDpyIdListsAreEqual(NVDpyIdList dpyIdListA,
|
||||
NVDpyIdList dpyIdListB)
|
||||
{
|
||||
return (dpyIdListA.opaqueDpyIdList == dpyIdListB.opaqueDpyIdList);
|
||||
}
|
||||
|
||||
static inline NvBool nvDpyIdListIsASubSetofDpyIdList(NVDpyIdList dpyIdListA,
|
||||
NVDpyIdList dpyIdListB)
|
||||
{
|
||||
NVDpyIdList intersectedDpyIdList =
|
||||
nvIntersectDpyIdListAndDpyIdList(dpyIdListA, dpyIdListB);
|
||||
|
||||
return nvDpyIdListsAreEqual(intersectedDpyIdList, dpyIdListA);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* retrieve the individual dpyIds from dpyIdList; if dpyId is invalid,
|
||||
* start at the beginning of the list; otherwise, start at the dpyId
|
||||
* after the specified dpyId
|
||||
*/
|
||||
|
||||
static inline __attribute__ ((warn_unused_result))
|
||||
NVDpyId nvNextDpyIdInDpyIdListUnsorted(NVDpyId dpyId, NVDpyIdList dpyIdList)
|
||||
{
|
||||
if (nvDpyIdIsInvalid(dpyId)) {
|
||||
dpyId.opaqueDpyId = 1;
|
||||
} else {
|
||||
dpyId.opaqueDpyId <<= 1;
|
||||
}
|
||||
|
||||
while (dpyId.opaqueDpyId) {
|
||||
|
||||
if (nvDpyIdIsInDpyIdList(dpyId, dpyIdList)) {
|
||||
return dpyId;
|
||||
}
|
||||
|
||||
dpyId.opaqueDpyId <<= 1;
|
||||
}
|
||||
|
||||
/* no dpyIds left in dpyIdlist; return the invalid dpyId */
|
||||
|
||||
return nvInvalidDpyId();
|
||||
}
|
||||
|
||||
#define FOR_ALL_DPY_IDS(_dpyId, _dpyIdList) \
|
||||
for ((_dpyId) = nvNextDpyIdInDpyIdListUnsorted(nvInvalidDpyId(), \
|
||||
(_dpyIdList)); \
|
||||
!nvDpyIdIsInvalid(_dpyId); \
|
||||
(_dpyId) = nvNextDpyIdInDpyIdListUnsorted((_dpyId), \
|
||||
(_dpyIdList)))
|
||||
|
||||
/* report how many dpyIds are in the dpyIdList */
|
||||
|
||||
static inline int nvCountDpyIdsInDpyIdList(NVDpyIdList dpyIdList)
|
||||
{
|
||||
return nvPopCount32(dpyIdList.opaqueDpyIdList);
|
||||
}
|
||||
|
||||
static inline int
|
||||
nvCountDpyIdsInDpyIdListSubDeviceArray(NVDpyIdList
|
||||
dpyIdList[NV_DPY_ID_MAX_SUBDEVICES])
|
||||
{
|
||||
int dispIndex, n = 0;
|
||||
|
||||
for (dispIndex = 0; dispIndex < NV_DPY_ID_MAX_SUBDEVICES; dispIndex++) {
|
||||
n += nvCountDpyIdsInDpyIdList(dpyIdList[dispIndex]);
|
||||
}
|
||||
|
||||
return n;
|
||||
}
|
||||
|
||||
/* convert between dpyId/dpyIdList and NV-CONTROL values */
|
||||
|
||||
static inline int nvDpyIdToNvControlVal(NVDpyId dpyId)
|
||||
{
|
||||
return (int) dpyId.opaqueDpyId;
|
||||
}
|
||||
|
||||
static inline int nvDpyIdListToNvControlVal(NVDpyIdList dpyIdList)
|
||||
{
|
||||
return (int) dpyIdList.opaqueDpyIdList;
|
||||
}
|
||||
|
||||
static inline NVDpyId nvNvControlValToDpyId(int val)
|
||||
{
|
||||
NVDpyId dpyId;
|
||||
dpyId.opaqueDpyId = (val == 0) ? 0 : 1 << (nv_ffs(val)-1);
|
||||
return dpyId;
|
||||
}
|
||||
|
||||
static inline NVDpyIdList nvNvControlValToDpyIdList(int val)
|
||||
{
|
||||
NVDpyIdList dpyIdList;
|
||||
dpyIdList.opaqueDpyIdList = val;
|
||||
return dpyIdList;
|
||||
}
|
||||
|
||||
|
||||
/* convert between dpyId and NvU32 */
|
||||
|
||||
static inline NVDpyId nvNvU32ToDpyId(NvU32 val)
|
||||
{
|
||||
NVDpyId dpyId;
|
||||
dpyId.opaqueDpyId = (val == 0) ? 0 : 1 << (nv_ffs(val)-1);
|
||||
return dpyId;
|
||||
}
|
||||
|
||||
static inline NVDpyIdList nvNvU32ToDpyIdList(NvU32 val)
|
||||
{
|
||||
NVDpyIdList dpyIdList;
|
||||
dpyIdList.opaqueDpyIdList = val;
|
||||
return dpyIdList;
|
||||
}
|
||||
|
||||
static inline NvU32 nvDpyIdToNvU32(NVDpyId dpyId)
|
||||
{
|
||||
return dpyId.opaqueDpyId;
|
||||
}
|
||||
|
||||
static inline NvU32 nvDpyIdListToNvU32(NVDpyIdList dpyIdList)
|
||||
{
|
||||
return dpyIdList.opaqueDpyIdList;
|
||||
}
|
||||
|
||||
/* Return the bit position of dpyId: a number in the range [0..31]. */
|
||||
static inline NvU32 nvDpyIdToIndex(NVDpyId dpyId)
|
||||
{
|
||||
return nv_ffs(dpyId.opaqueDpyId) - 1;
|
||||
}
|
||||
|
||||
/* Return a display ID that is not in the list passed in. */
|
||||
|
||||
static inline NVDpyId nvNewDpyId(NVDpyIdList excludeList)
|
||||
{
|
||||
NVDpyId dpyId;
|
||||
if (~excludeList.opaqueDpyIdList == 0) {
|
||||
return nvInvalidDpyId();
|
||||
}
|
||||
dpyId.opaqueDpyId =
|
||||
1U << (nv_ffs(~excludeList.opaqueDpyIdList) - 1);
|
||||
return dpyId;
|
||||
}
|
||||
|
||||
/* See comment for NV_DPY_ID_PRINT_FORMAT. */
|
||||
static inline NvU32 nvDpyIdToPrintFormat(NVDpyId dpyId)
|
||||
{
|
||||
return nvDpyIdToNvU32(dpyId);
|
||||
}
|
||||
|
||||
/* Prevent usage of opaque values. */
|
||||
#define opaqueDpyId __ERROR_ACCESS_ME_VIA_NV_DPY_ID_H
|
||||
#define opaqueDpyIdList __ERROR_ACCESS_ME_VIA_NV_DPY_ID_H
|
||||
|
||||
#endif /* __NV_DPY_ID_H__ */
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -180,6 +180,8 @@ enum NvKmsEventType {
|
||||
NVKMS_EVENT_TYPE_DPY_ATTRIBUTE_CHANGED,
|
||||
NVKMS_EVENT_TYPE_FRAMELOCK_ATTRIBUTE_CHANGED,
|
||||
NVKMS_EVENT_TYPE_FLIP_OCCURRED,
|
||||
NVKMS_EVENT_TYPE_DPY_CP_CHANGED,
|
||||
NVKMS_EVENT_TYPE_DPY_CP_TOPOLOGY_CHANGED,
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
@@ -692,4 +694,31 @@ struct NvKmsSuperframeInfo {
|
||||
|
||||
typedef void (*NVVBlankIntrCallbackProc)(NvU64 param1, NvU64 param2);
|
||||
|
||||
enum NvKmsContentProtection {
|
||||
NVKMS_CP_OFF = 0,
|
||||
NVKMS_CP_HDCP1X_ON = 1,
|
||||
NVKMS_CP_HDCP2X_TYPE0_ON = 2,
|
||||
NVKMS_CP_HDCP2X_TYPE1_ON = 3,
|
||||
};
|
||||
|
||||
#define HDCP_TOPOLOGY_MAX_LINK_COUNT (2)
|
||||
#define HDCP_TOPOLOGY_MAX_DEV_COUNT (255)
|
||||
#define HDCP_TOPOLOGY_KSV_SIZE (5)
|
||||
|
||||
struct NvKmsHdcpTopology {
|
||||
NvBool isHdcpCapable;
|
||||
NvBool isHdcpAuthOn;
|
||||
NvBool isHdcpRp;
|
||||
NvBool isHdcp2X;
|
||||
NvBool maxCascadeExceeded;
|
||||
NvBool maxDeviceExceeded;
|
||||
NvBool isHdcp1DevDownstream;
|
||||
NvBool isHdcp2LegacyDevDownstream;
|
||||
NvU8 cascadeDepth;
|
||||
NvU8 linkCount;
|
||||
NvU8 bksv[HDCP_TOPOLOGY_MAX_LINK_COUNT * HDCP_TOPOLOGY_KSV_SIZE];
|
||||
NvU8 numOfBksv;
|
||||
NvU8 bksvList[HDCP_TOPOLOGY_MAX_DEV_COUNT * HDCP_TOPOLOGY_KSV_SIZE];
|
||||
};
|
||||
|
||||
#endif /* NVKMS_API_TYPES_H */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -26,6 +26,7 @@
|
||||
#include "nvtypes.h"
|
||||
|
||||
#include "nv-gpu-info.h"
|
||||
#include "nv_dpy_id.h"
|
||||
#include "nvkms-api-types.h"
|
||||
#include "nvkms-format.h"
|
||||
|
||||
@@ -190,6 +191,7 @@ struct NvKmsKapiConnectorInfo {
|
||||
NvU32 numIncompatibleConnectors;
|
||||
NvKmsKapiConnector incompatibleConnectorHandles[NVKMS_KAPI_MAX_CONNECTORS];
|
||||
|
||||
NVDpyIdList dynamicDpyIdList;
|
||||
};
|
||||
|
||||
struct NvKmsKapiStaticDisplayInfo {
|
||||
@@ -208,6 +210,8 @@ struct NvKmsKapiStaticDisplayInfo {
|
||||
NvKmsKapiDisplay possibleCloneHandles[NVKMS_KAPI_MAX_CLONE_DISPLAYS];
|
||||
|
||||
NvU32 headMask;
|
||||
|
||||
NvBool isDpMST;
|
||||
};
|
||||
|
||||
struct NvKmsKapiSyncpt {
|
||||
@@ -249,6 +253,8 @@ struct NvKmsKapiLayerConfig {
|
||||
|
||||
enum NvKmsInputColorSpace inputColorSpace;
|
||||
enum NvKmsInputColorRange inputColorRange;
|
||||
struct NvKmsCscMatrix csc;
|
||||
NvBool cscUseMain;
|
||||
};
|
||||
|
||||
struct NvKmsKapiLayerRequestedConfig {
|
||||
@@ -259,6 +265,7 @@ struct NvKmsKapiLayerRequestedConfig {
|
||||
NvBool srcWHChanged : 1;
|
||||
NvBool dstXYChanged : 1;
|
||||
NvBool dstWHChanged : 1;
|
||||
NvBool cscChanged : 1;
|
||||
} flags;
|
||||
};
|
||||
|
||||
@@ -348,6 +355,16 @@ struct NvKmsKapiEventDisplayChanged {
|
||||
NvKmsKapiDisplay display;
|
||||
};
|
||||
|
||||
struct NvKmsKapiEventDisplayCpChanged {
|
||||
NvKmsKapiDisplay display;
|
||||
enum NvKmsContentProtection cp;
|
||||
};
|
||||
|
||||
struct NvKmsKapiEventDisplayCpTopologyChanged {
|
||||
NvKmsKapiDisplay display;
|
||||
struct NvKmsHdcpTopology *topology;
|
||||
};
|
||||
|
||||
struct NvKmsKapiEventDynamicDisplayConnected {
|
||||
NvKmsKapiDisplay display;
|
||||
};
|
||||
@@ -379,6 +396,8 @@ struct NvKmsKapiEvent {
|
||||
struct NvKmsKapiEventDisplayChanged displayChanged;
|
||||
struct NvKmsKapiEventDynamicDisplayConnected dynamicDisplayConnected;
|
||||
struct NvKmsKapiEventFlipOccurred flipOccurred;
|
||||
struct NvKmsKapiEventDisplayCpChanged displayCpChanged;
|
||||
struct NvKmsKapiEventDisplayCpTopologyChanged displayCpTopologyChanged;
|
||||
} u;
|
||||
};
|
||||
|
||||
|
||||
@@ -1390,6 +1390,23 @@ compile_test() {
|
||||
compile_check_conftest "$CODE" "NV_DRM_DEV_UNREF_PRESENT" "" "functions"
|
||||
;;
|
||||
|
||||
drm_sysfs_connector_property_event)
|
||||
#
|
||||
# Determine if drm_sysfs_connector_property_event() is present.
|
||||
#
|
||||
# Commit 0cf8d292ba5e ("drm/sysfs: rename drm_sysfs_connector_status_event()")
|
||||
# renamed drm_sysfs_connector_status_event() to
|
||||
# drm_sysfs_connector_property_event() in Linux v6.5.
|
||||
#
|
||||
CODE="
|
||||
#include <drm/drm_sysfs.h>
|
||||
void conftest_drm_sysfs_connector_property_event(void) {
|
||||
drm_sysfs_connector_property_event();
|
||||
}"
|
||||
|
||||
compile_check_conftest "$CODE" "NV_DRM_SYSFS_CONNECTOR_PROPERTY_EVENT_PRESENT" "" "functions"
|
||||
;;
|
||||
|
||||
pde_data)
|
||||
#
|
||||
# Determine if the pde_data() function is present.
|
||||
@@ -5287,6 +5304,31 @@ compile_test() {
|
||||
fi
|
||||
;;
|
||||
|
||||
of_property_for_each_u32_has_internal_args)
|
||||
#
|
||||
# Determine if the internal arguments for the macro
|
||||
# of_property_for_each_u32() are present.
|
||||
#
|
||||
# Commit 9722c3b66e21 ("of: remove internal arguments from
|
||||
# of_property_for_each_u32()") removes two arguments from
|
||||
# of_property_for_each_u32() which are used internally within
|
||||
# the macro and so do not need to be passed. This change was
|
||||
# made for Linux v6.11.
|
||||
#
|
||||
CODE="
|
||||
#include <linux/of.h>
|
||||
void conftest_of_property_for_each_u32(struct device_node *np,
|
||||
char *propname) {
|
||||
struct property *iparam1;
|
||||
const __be32 *iparam2;
|
||||
u32 val;
|
||||
|
||||
of_property_for_each_u32(np, propname, iparam1, iparam2, val);
|
||||
}"
|
||||
|
||||
compile_check_conftest "$CODE" "NV_OF_PROPERTY_FOR_EACH_U32_HAS_INTERNAL_ARGS" "" "types"
|
||||
;;
|
||||
|
||||
of_property_read_variable_u8_array)
|
||||
#
|
||||
# Determine if of_property_read_variable_u8_array is present
|
||||
@@ -6373,6 +6415,29 @@ compile_test() {
|
||||
compile_check_conftest "$CODE" "NV_DRM_FBDEV_GENERIC_SETUP_PRESENT" "" "functions"
|
||||
;;
|
||||
|
||||
drm_output_poll_changed)
|
||||
#
|
||||
# Determine whether drm_mode_config_funcs.output_poll_changed
|
||||
# callback is present
|
||||
#
|
||||
# Removed by commit 446d0f4849b1 ("drm: Remove struct
|
||||
# drm_mode_config_funcs.output_poll_changed") in v6.12. Hotplug
|
||||
# event support is handled through the fbdev emulation interface
|
||||
# going forward.
|
||||
#
|
||||
CODE="
|
||||
#if defined(NV_DRM_DRM_MODE_CONFIG_H_PRESENT)
|
||||
#include <drm/drm_mode_config.h>
|
||||
#else
|
||||
#include <drm/drm_crtc.h>
|
||||
#endif
|
||||
int conftest_drm_output_poll_changed_available(void) {
|
||||
return offsetof(struct drm_mode_config_funcs, output_poll_changed);
|
||||
}"
|
||||
|
||||
compile_check_conftest "$CODE" "NV_DRM_OUTPUT_POLL_CHANGED_PRESENT" "" "types"
|
||||
;;
|
||||
|
||||
drm_aperture_remove_conflicting_pci_framebuffers)
|
||||
#
|
||||
# Determine whether drm_aperture_remove_conflicting_pci_framebuffers is present.
|
||||
@@ -6558,6 +6623,69 @@ compile_test() {
|
||||
compile_check_conftest "$CODE" "NV_DRM_APERTURE_REMOVE_CONFLICTING_FRAMEBUFFERS_HAS_NO_PRIMARY_ARG" "" "types"
|
||||
;;
|
||||
|
||||
platform_driver_struct_remove_returns_void)
|
||||
#
|
||||
# Determine if the 'platform_driver' structure 'remove' function
|
||||
# pointer returns void.
|
||||
#
|
||||
# Commit 0edb555a65d1 ("platform: Make platform_driver::remove()
|
||||
# return void") updated the platform_driver structure 'remove'
|
||||
# callback to return void instead of int in Linux v6.11-rc1.
|
||||
#
|
||||
echo "$CONFTEST_PREAMBLE
|
||||
#include <linux/platform_device.h>
|
||||
int conftest_platform_driver_struct_remove_returns_void(struct platform_device *pdev,
|
||||
struct platform_driver *driver) {
|
||||
return driver->remove(pdev);
|
||||
}" > conftest$$.c
|
||||
|
||||
$CC $CFLAGS -c conftest$$.c > /dev/null 2>&1
|
||||
rm -f conftest$$.c
|
||||
|
||||
if [ -f conftest$$.o ]; then
|
||||
rm -f conftest$$.o
|
||||
|
||||
echo "#undef NV_PLATFORM_DRIVER_STRUCT_REMOVE_RETURNS_VOID" | append_conftest "types"
|
||||
else
|
||||
echo "#define NV_PLATFORM_DRIVER_STRUCT_REMOVE_RETURNS_VOID" | append_conftest "types"
|
||||
fi
|
||||
;;
|
||||
|
||||
drm_mode_create_dp_colorspace_property_has_supported_colorspaces_arg)
|
||||
# Determine if drm_mode_create_dp_colorspace_property() takes the
|
||||
# 'supported_colorspaces' argument.
|
||||
#
|
||||
# The 'u32 supported_colorspaces' argument was added to
|
||||
# drm_mode_create_dp_colorspace_property() by linux-next commit
|
||||
# c265f340eaa8 ("drm/connector: Allow drivers to pass list of
|
||||
# supported colorspaces").
|
||||
#
|
||||
# To test if drm_mode_create_dp_colorspace_property() has the
|
||||
# 'supported_colorspaces' argument, declare a function prototype
|
||||
# with typeof drm_mode_create_dp_colorspace_property and then
|
||||
# define the corresponding function implementation with the
|
||||
# expected signature. Successful compilation indicates that
|
||||
# drm_mode_create_dp_colorspace_property() has the
|
||||
# 'supported_colorspaces' argument.
|
||||
#
|
||||
CODE="
|
||||
#if defined(NV_DRM_DRM_CRTC_H_PRESENT)
|
||||
#include <drm/drm_crtc.h>
|
||||
#endif
|
||||
#if defined(NV_DRM_DRM_CONNECTOR_H_PRESENT)
|
||||
#include <drm/drm_connector.h>
|
||||
#endif
|
||||
|
||||
typeof(drm_mode_create_dp_colorspace_property) conftest_drm_mode_create_dp_colorspace_property_has_supported_colorspaces_arg;
|
||||
int conftest_drm_mode_create_dp_colorspace_property_has_supported_colorspaces_arg(struct drm_connector *connector,
|
||||
u32 supported_colorspaces)
|
||||
{
|
||||
return 0;
|
||||
}"
|
||||
|
||||
compile_check_conftest "$CODE" "NV_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_HAS_SUPPORTED_COLORSPACES_ARG" "" "types"
|
||||
;;
|
||||
|
||||
# When adding a new conftest entry, please use the correct format for
|
||||
# specifying the relevant upstream Linux kernel commit.
|
||||
#
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2017 - 2024, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -61,4 +61,15 @@
|
||||
#undef NV_DRM_FENCE_AVAILABLE
|
||||
#endif
|
||||
|
||||
/*
|
||||
* We can support color management if either drm_helper_crtc_enable_color_mgmt()
|
||||
* or drm_crtc_enable_color_mgmt() exist.
|
||||
*/
|
||||
#if defined(NV_DRM_HELPER_CRTC_ENABLE_COLOR_MGMT_PRESENT) || \
|
||||
defined(NV_DRM_CRTC_ENABLE_COLOR_MGMT_PRESENT)
|
||||
#define NV_DRM_COLOR_MGMT_AVAILABLE
|
||||
#else
|
||||
#undef NV_DRM_COLOR_MGMT_AVAILABLE
|
||||
#endif
|
||||
|
||||
#endif /* defined(__NVIDIA_DRM_CONFTEST_H__) */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2015- 2024, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2015- 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -45,6 +45,16 @@
|
||||
#include <drm/drm_atomic_helper.h>
|
||||
#include <drm/drm_edid.h>
|
||||
|
||||
#if defined(NV_DRM_DISPLAY_DRM_HDCP_HELPER_H_PRESENT)
|
||||
#include <drm/display/drm_hdcp_helper.h>
|
||||
#elif defined(NV_DRM_DISPLAY_DRM_HDCP_H_PRESENT)
|
||||
#include <drm/display/drm_hdcp.h>
|
||||
#else
|
||||
#include <drm/drm_hdcp.h>
|
||||
#endif
|
||||
|
||||
#include <drm/drm_sysfs.h>
|
||||
|
||||
static void nv_drm_connector_destroy(struct drm_connector *connector)
|
||||
{
|
||||
struct nv_drm_connector *nv_connector = to_nv_connector(connector);
|
||||
@@ -245,6 +255,10 @@ static struct drm_connector_state* nv_drm_connector_atomic_duplicate_state(struc
|
||||
|
||||
nv_drm_new_connector_state->output_colorrange = nv_drm_old_connector_state->output_colorrange;
|
||||
nv_drm_new_connector_state->op_colorrange_changed = false;
|
||||
nv_drm_new_connector_state->hdcp_topology_blob = nv_drm_old_connector_state->hdcp_topology_blob;
|
||||
if (nv_drm_new_connector_state->hdcp_topology_blob) {
|
||||
drm_property_blob_get(nv_drm_new_connector_state->hdcp_topology_blob);
|
||||
}
|
||||
|
||||
return &nv_drm_new_connector_state->base;
|
||||
}
|
||||
@@ -257,6 +271,7 @@ static void nv_drm_connector_atomic_destroy_state(
|
||||
to_nv_drm_connector_state(state);
|
||||
|
||||
__drm_atomic_helper_connector_destroy_state(state);
|
||||
drm_property_blob_put(nv_drm_connector_state->hdcp_topology_blob);
|
||||
|
||||
nv_drm_free(nv_drm_connector_state);
|
||||
}
|
||||
@@ -437,6 +452,12 @@ nv_drm_connector_best_encoder(struct drm_connector *connector)
|
||||
return NULL;
|
||||
}
|
||||
|
||||
#if defined(NV_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_HAS_SUPPORTED_COLORSPACES_ARG)
|
||||
static const NvU32 __nv_drm_connector_supported_colorspaces =
|
||||
BIT(DRM_MODE_COLORIMETRY_BT2020_RGB) |
|
||||
BIT(DRM_MODE_COLORIMETRY_BT2020_YCC);
|
||||
#endif
|
||||
|
||||
static int
|
||||
nv_drm_connector_atomic_check(struct drm_connector *connector,
|
||||
struct drm_atomic_state *state)
|
||||
@@ -484,7 +505,7 @@ nv_drm_connector_atomic_check(struct drm_connector *connector,
|
||||
|
||||
req_config->flags.colorimetryChanged =
|
||||
(old_connector_state->colorspace != new_connector_state->colorspace);
|
||||
|
||||
// When adding a case here, also add to __nv_drm_connector_supported_colorspaces
|
||||
switch (new_connector_state->colorspace) {
|
||||
case DRM_MODE_COLORIMETRY_DEFAULT:
|
||||
req_config->modeSetConfig.colorimetry =
|
||||
@@ -549,6 +570,7 @@ nv_drm_connector_new(struct drm_device *dev,
|
||||
nv_connector->internal = internal;
|
||||
nv_connector->modeset_permission_filep = NULL;
|
||||
nv_connector->modeset_permission_crtc = NULL;
|
||||
nv_connector->cp = NVKMS_CP_OFF;
|
||||
|
||||
strcpy(nv_connector->dpAddress, dpAddress);
|
||||
|
||||
@@ -574,18 +596,47 @@ nv_drm_connector_new(struct drm_device *dev,
|
||||
DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
|
||||
}
|
||||
|
||||
/* attach content protection properties */
|
||||
if (nv_connector->type != NVKMS_CONNECTOR_TYPE_DSI) {
|
||||
ret = drm_connector_attach_content_protection_property(&nv_connector->base, true);
|
||||
if (ret != 0) {
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
nv_dev,
|
||||
"Failed to attach content protction properties to connector created from physical index %u",
|
||||
nv_connector->physicalIndex);
|
||||
goto failed_connector_init;
|
||||
}
|
||||
}
|
||||
|
||||
/* attach nvidia defined connector properties */
|
||||
if (nv_connector->type != NVKMS_CONNECTOR_TYPE_DSI) {
|
||||
drm_object_attach_property(&nv_connector->base.base,
|
||||
nv_dev->nv_hdcp_topology_property,
|
||||
0);
|
||||
}
|
||||
drm_object_attach_property(&nv_connector->base.base,
|
||||
nv_dev->nv_output_colorrange_property,
|
||||
NV_KMS_DPY_ATTRIBUTE_COLOR_RANGE_FULL);
|
||||
|
||||
if (nv_connector->type == NVKMS_CONNECTOR_TYPE_HDMI) {
|
||||
#if defined(NV_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_HAS_SUPPORTED_COLORSPACES_ARG)
|
||||
if (drm_mode_create_hdmi_colorspace_property(
|
||||
&nv_connector->base,
|
||||
__nv_drm_connector_supported_colorspaces) == 0) {
|
||||
#else
|
||||
if (drm_mode_create_hdmi_colorspace_property(&nv_connector->base) == 0) {
|
||||
#endif
|
||||
drm_connector_attach_colorspace_property(&nv_connector->base);
|
||||
}
|
||||
drm_connector_attach_hdr_output_metadata_property(&nv_connector->base);
|
||||
} else if (nv_connector->type == NVKMS_CONNECTOR_TYPE_DP) {
|
||||
#if defined(NV_DRM_MODE_CREATE_DP_COLORSPACE_PROPERTY_HAS_SUPPORTED_COLORSPACES_ARG)
|
||||
if (drm_mode_create_dp_colorspace_property(
|
||||
&nv_connector->base,
|
||||
__nv_drm_connector_supported_colorspaces) == 0) {
|
||||
#else
|
||||
if (drm_mode_create_dp_colorspace_property(&nv_connector->base) == 0) {
|
||||
#endif
|
||||
drm_connector_attach_colorspace_property(&nv_connector->base);
|
||||
}
|
||||
drm_connector_attach_hdr_output_metadata_property(&nv_connector->base);
|
||||
@@ -690,4 +741,67 @@ bool nv_drm_connector_revoke_permissions(struct drm_device *dev,
|
||||
return ret;
|
||||
}
|
||||
|
||||
void nv_drm_connector_update_content_protection(struct nv_drm_connector *nv_connector)
|
||||
{
|
||||
struct drm_connector *connector = &nv_connector->base;
|
||||
struct drm_connector_state *state = connector->state;
|
||||
unsigned int content_protection = state->content_protection;
|
||||
unsigned int hdcp_content_type = state->hdcp_content_type;
|
||||
bool update_cp = false;
|
||||
unsigned int cp_val;
|
||||
|
||||
if ((content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) &&
|
||||
(hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE0)) {
|
||||
if ((nv_connector->cp == NVKMS_CP_HDCP1X_ON) ||
|
||||
(nv_connector->cp == NVKMS_CP_HDCP2X_TYPE0_ON) ||
|
||||
(nv_connector->cp == NVKMS_CP_HDCP2X_TYPE1_ON)) {
|
||||
cp_val = DRM_MODE_CONTENT_PROTECTION_ENABLED;
|
||||
update_cp = true;
|
||||
}
|
||||
} else if ((content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) &&
|
||||
(hdcp_content_type == DRM_MODE_HDCP_CONTENT_TYPE1)) {
|
||||
if (nv_connector->cp == NVKMS_CP_HDCP2X_TYPE1_ON) {
|
||||
cp_val = DRM_MODE_CONTENT_PROTECTION_ENABLED;
|
||||
update_cp = true;
|
||||
}
|
||||
} else if (content_protection == DRM_MODE_CONTENT_PROTECTION_ENABLED) {
|
||||
if (nv_connector->cp == NVKMS_CP_OFF) {
|
||||
cp_val = DRM_MODE_CONTENT_PROTECTION_DESIRED;
|
||||
update_cp = true;
|
||||
}
|
||||
}
|
||||
|
||||
if (update_cp) {
|
||||
drm_hdcp_update_content_protection(connector, cp_val);
|
||||
}
|
||||
}
|
||||
|
||||
int nv_drm_connector_update_topology_property(struct nv_drm_connector *nv_connector,
|
||||
struct NvKmsHdcpTopology *topology)
|
||||
{
|
||||
struct drm_connector *connector = &nv_connector->base;
|
||||
struct drm_connector_state *state = connector->state;
|
||||
struct nv_drm_connector_state *nv_state = to_nv_drm_connector_state(state);
|
||||
struct drm_device *dev = connector->dev;
|
||||
struct nv_drm_device *nv_dev = to_nv_device(dev);
|
||||
int ret;
|
||||
|
||||
ret = drm_property_replace_global_blob(dev,
|
||||
&nv_state->hdcp_topology_blob,
|
||||
sizeof(*topology),
|
||||
topology,
|
||||
&connector->base,
|
||||
nv_dev->nv_hdcp_topology_property);
|
||||
// Generate uevent on cp property when topology is updated
|
||||
#if defined(NV_DRM_SYSFS_CONNECTOR_PROPERTY_EVENT_PRESENT)
|
||||
drm_sysfs_connector_property_event(connector,
|
||||
dev->mode_config.content_protection_property);
|
||||
#else
|
||||
drm_sysfs_connector_status_event(connector,
|
||||
dev->mode_config.content_protection_property);
|
||||
#endif
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#endif
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2016 - 2024, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2016 - 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -49,6 +49,8 @@ struct nv_drm_connector {
|
||||
struct nv_drm_encoder *nv_detected_encoder;
|
||||
struct edid *edid;
|
||||
|
||||
enum NvKmsContentProtection cp;
|
||||
|
||||
atomic_t connection_status_dirty;
|
||||
|
||||
/**
|
||||
@@ -81,6 +83,7 @@ struct nv_drm_connector_state {
|
||||
struct drm_connector_state base;
|
||||
enum NvKmsDpyAttributeColorRangeValue output_colorrange;
|
||||
NvBool op_colorrange_changed;
|
||||
struct drm_property_blob *hdcp_topology_blob;
|
||||
};
|
||||
|
||||
static inline struct nv_drm_connector_state *to_nv_drm_connector_state(
|
||||
@@ -118,6 +121,10 @@ nv_drm_get_connector(struct drm_device *dev,
|
||||
|
||||
bool nv_drm_connector_revoke_permissions(struct drm_device *dev,
|
||||
struct nv_drm_connector *nv_connector);
|
||||
void nv_drm_connector_update_content_protection(struct nv_drm_connector *nv_connector);
|
||||
int nv_drm_connector_update_topology_property(struct nv_drm_connector *nv_connector,
|
||||
struct NvKmsHdcpTopology *topology);
|
||||
|
||||
|
||||
#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
|
||||
|
||||
|
||||
@@ -49,6 +49,9 @@
|
||||
#endif
|
||||
|
||||
#include <drm/drm_vblank.h>
|
||||
#if defined(NV_DRM_DRM_COLOR_MGMT_H_PRESENT)
|
||||
#include <drm/drm_color_mgmt.h>
|
||||
#endif
|
||||
|
||||
#if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA)
|
||||
static int
|
||||
@@ -89,11 +92,22 @@ static void nv_drm_plane_destroy(struct drm_plane *plane)
|
||||
nv_drm_free(nv_plane);
|
||||
}
|
||||
|
||||
static inline void
|
||||
plane_config_clear(struct NvKmsKapiLayerConfig *layerConfig)
|
||||
{
|
||||
if (layerConfig == NULL) {
|
||||
return;
|
||||
}
|
||||
|
||||
memset(layerConfig, 0, sizeof(*layerConfig));
|
||||
layerConfig->csc = NVKMS_IDENTITY_CSC_MATRIX;
|
||||
}
|
||||
|
||||
static inline void
|
||||
plane_req_config_disable(struct NvKmsKapiLayerRequestedConfig *req_config)
|
||||
{
|
||||
/* Clear layer config */
|
||||
memset(&req_config->config, 0, sizeof(req_config->config));
|
||||
plane_config_clear(&req_config->config);
|
||||
|
||||
/* Set flags to get cleared layer config applied */
|
||||
req_config->flags.surfaceChanged = NV_TRUE;
|
||||
@@ -110,6 +124,45 @@ cursor_req_config_disable(struct NvKmsKapiCursorRequestedConfig *req_config)
|
||||
req_config->flags.surfaceChanged = NV_TRUE;
|
||||
}
|
||||
|
||||
#if defined(NV_DRM_COLOR_MGMT_AVAILABLE)
|
||||
static void color_mgmt_config_ctm_to_csc(struct NvKmsCscMatrix *nvkms_csc,
|
||||
struct drm_color_ctm *drm_ctm)
|
||||
{
|
||||
int y;
|
||||
|
||||
/* CTM is a 3x3 matrix while ours is 3x4. Zero out the last column. */
|
||||
nvkms_csc->m[0][3] = nvkms_csc->m[1][3] = nvkms_csc->m[2][3] = 0;
|
||||
|
||||
for (y = 0; y < 3; y++) {
|
||||
int x;
|
||||
|
||||
for (x = 0; x < 3; x++) {
|
||||
/*
|
||||
* Values in the CTM are encoded in S31.32 sign-magnitude fixed-
|
||||
* point format, while NvKms CSC values are signed 2's-complement
|
||||
* S15.16 (Ssign-extend12-3.16?) fixed-point format.
|
||||
*/
|
||||
NvU64 ctmVal = drm_ctm->matrix[y*3 + x];
|
||||
NvU64 signBit = ctmVal & (1ULL << 63);
|
||||
NvU64 magnitude = ctmVal & ~signBit;
|
||||
|
||||
/*
|
||||
* Drop the low 16 bits of the fractional part and the high 17 bits
|
||||
* of the integral part. Drop 17 bits to avoid corner cases where
|
||||
* the highest resulting bit is a 1, causing the `cscVal = -cscVal`
|
||||
* line to result in a positive number.
|
||||
*/
|
||||
NvS32 cscVal = (magnitude >> 16) & ((1ULL << 31) - 1);
|
||||
if (signBit) {
|
||||
cscVal = -cscVal;
|
||||
}
|
||||
|
||||
nvkms_csc->m[y][x] = cscVal;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* NV_DRM_COLOR_MGMT_AVAILABLE */
|
||||
|
||||
static void
|
||||
cursor_plane_req_config_update(struct drm_plane *plane,
|
||||
struct drm_plane_state *plane_state,
|
||||
@@ -236,6 +289,8 @@ plane_req_config_update(struct drm_plane *plane,
|
||||
.dstY = plane_state->crtc_y,
|
||||
.dstWidth = plane_state->crtc_w,
|
||||
.dstHeight = plane_state->crtc_h,
|
||||
|
||||
.csc = old_config.csc
|
||||
},
|
||||
};
|
||||
|
||||
@@ -569,6 +624,24 @@ static int nv_drm_plane_atomic_check(struct drm_plane *plane,
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if defined(NV_DRM_COLOR_MGMT_AVAILABLE)
|
||||
if (crtc_state->color_mgmt_changed || ((plane->state->crtc != plane_state->crtc))) {
|
||||
/*
|
||||
* According to the comment in the Linux kernel's
|
||||
* drivers/gpu/drm/drm_color_mgmt.c, if this property is NULL,
|
||||
* the CTM needs to be changed to the identity matrix
|
||||
*/
|
||||
if (crtc_state->ctm) {
|
||||
color_mgmt_config_ctm_to_csc(&plane_requested_config->config.csc,
|
||||
(struct drm_color_ctm *)crtc_state->ctm->data);
|
||||
} else {
|
||||
plane_requested_config->config.csc = NVKMS_IDENTITY_CSC_MATRIX;
|
||||
}
|
||||
plane_requested_config->config.cscUseMain = NV_FALSE;
|
||||
plane_requested_config->flags.cscChanged = NV_TRUE;
|
||||
}
|
||||
#endif /* NV_DRM_COLOR_MGMT_AVAILABLE */
|
||||
|
||||
if (__is_async_flip_requested(plane, crtc_state)) {
|
||||
/*
|
||||
* Async flip requests that the flip happen 'as soon as
|
||||
@@ -812,6 +885,21 @@ static inline void nv_drm_crtc_duplicate_req_head_modeset_config(
|
||||
}
|
||||
}
|
||||
|
||||
static inline struct nv_drm_crtc_state *nv_drm_crtc_state_alloc(void)
|
||||
{
|
||||
struct nv_drm_crtc_state *nv_state = nv_drm_calloc(1, sizeof(*nv_state));
|
||||
int i;
|
||||
|
||||
if (nv_state == NULL) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(nv_state->req_config.layerRequestedConfig); i++) {
|
||||
plane_config_clear(&nv_state->req_config.layerRequestedConfig[i].config);
|
||||
}
|
||||
return nv_state;
|
||||
}
|
||||
|
||||
/**
|
||||
* nv_drm_atomic_crtc_reset - crtc state reset hook
|
||||
* @crtc: DRM crtc
|
||||
@@ -820,7 +908,7 @@ static inline void nv_drm_crtc_duplicate_req_head_modeset_config(
|
||||
*/
|
||||
static void nv_drm_atomic_crtc_reset(struct drm_crtc *crtc)
|
||||
{
|
||||
struct nv_drm_crtc_state *nv_state = nv_drm_calloc(1, sizeof(*nv_state));
|
||||
struct nv_drm_crtc_state *nv_state = nv_drm_crtc_state_alloc();
|
||||
|
||||
if (!nv_state) {
|
||||
return;
|
||||
@@ -853,7 +941,7 @@ static void nv_drm_atomic_crtc_reset(struct drm_crtc *crtc)
|
||||
static struct drm_crtc_state*
|
||||
nv_drm_atomic_crtc_duplicate_state(struct drm_crtc *crtc)
|
||||
{
|
||||
struct nv_drm_crtc_state *nv_state = nv_drm_calloc(1, sizeof(*nv_state));
|
||||
struct nv_drm_crtc_state *nv_state = nv_drm_crtc_state_alloc();
|
||||
|
||||
if (nv_state == NULL) {
|
||||
return NULL;
|
||||
@@ -865,14 +953,20 @@ nv_drm_atomic_crtc_duplicate_state(struct drm_crtc *crtc)
|
||||
return NULL;
|
||||
}
|
||||
|
||||
__drm_atomic_helper_crtc_duplicate_state(crtc, &nv_state->base);
|
||||
|
||||
INIT_LIST_HEAD(&nv_state->nv_flip->list_entry);
|
||||
|
||||
/*
|
||||
* nv_drm_crtc_duplicate_req_head_modeset_config potentially allocates
|
||||
* nv_state->req_config.modeSetConfig.lut.{in,out}put.pRamps, so they should
|
||||
* be freed in any following failure paths.
|
||||
*/
|
||||
|
||||
nv_drm_crtc_duplicate_req_head_modeset_config(
|
||||
&(to_nv_crtc_state(crtc->state)->req_config),
|
||||
&nv_state->req_config);
|
||||
|
||||
__drm_atomic_helper_crtc_duplicate_state(crtc, &nv_state->base);
|
||||
|
||||
return &nv_state->base;
|
||||
}
|
||||
|
||||
@@ -1343,7 +1437,7 @@ static struct drm_crtc *__nv_drm_crtc_create(struct nv_drm_device *nv_dev,
|
||||
goto failed;
|
||||
}
|
||||
|
||||
nv_state = nv_drm_calloc(1, sizeof(*nv_state));
|
||||
nv_state = nv_drm_crtc_state_alloc();
|
||||
if (nv_state == NULL) {
|
||||
goto failed_state_alloc;
|
||||
}
|
||||
@@ -1379,6 +1473,14 @@ static struct drm_crtc *__nv_drm_crtc_create(struct nv_drm_device *nv_dev,
|
||||
|
||||
drm_crtc_helper_add(&nv_crtc->base, &nv_crtc_helper_funcs);
|
||||
|
||||
#if defined(NV_DRM_COLOR_MGMT_AVAILABLE)
|
||||
#if defined(NV_DRM_CRTC_ENABLE_COLOR_MGMT_PRESENT)
|
||||
drm_crtc_enable_color_mgmt(&nv_crtc->base, 0, true, 0);
|
||||
#else
|
||||
drm_helper_crtc_enable_color_mgmt(&nv_crtc->base, 0, 0);
|
||||
#endif
|
||||
#endif
|
||||
|
||||
return &nv_crtc->base;
|
||||
|
||||
failed_init_crtc:
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2024, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2015-2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -35,6 +35,8 @@
|
||||
#include "nvidia-drm-gem-nvkms-memory.h"
|
||||
#include "nvidia-drm-gem-user-memory.h"
|
||||
#include "nvidia-drm-gem-dma-buf.h"
|
||||
#include "nvidia-drm-utils.h"
|
||||
#include "nv_dpy_id.h"
|
||||
|
||||
#if defined(NV_DRM_AVAILABLE)
|
||||
|
||||
@@ -71,6 +73,7 @@
|
||||
|
||||
#include <linux/pci.h>
|
||||
#include <linux/workqueue.h>
|
||||
#include <linux/sort.h>
|
||||
|
||||
/*
|
||||
* Commit fcd70cd36b9b ("drm: Split out drm_probe_helper.h")
|
||||
@@ -164,6 +167,7 @@ static const char* nv_get_output_colorrange_name(
|
||||
|
||||
#if defined(NV_DRM_ATOMIC_MODESET_AVAILABLE)
|
||||
|
||||
#if defined(NV_DRM_OUTPUT_POLL_CHANGED_PRESENT)
|
||||
static void nv_drm_output_poll_changed(struct drm_device *dev)
|
||||
{
|
||||
struct drm_connector *connector = NULL;
|
||||
@@ -207,6 +211,7 @@ static void nv_drm_output_poll_changed(struct drm_device *dev)
|
||||
nv_drm_connector_list_iter_end(&conn_iter);
|
||||
#endif
|
||||
}
|
||||
#endif /* NV_DRM_OUTPUT_POLL_CHANGED_PRESENT */
|
||||
|
||||
static struct drm_framebuffer *nv_drm_framebuffer_create(
|
||||
struct drm_device *dev,
|
||||
@@ -244,7 +249,9 @@ static const struct drm_mode_config_funcs nv_mode_config_funcs = {
|
||||
.atomic_check = nv_drm_atomic_check,
|
||||
.atomic_commit = nv_drm_atomic_commit,
|
||||
|
||||
#if defined(NV_DRM_OUTPUT_POLL_CHANGED_PRESENT)
|
||||
.output_poll_changed = nv_drm_output_poll_changed,
|
||||
#endif
|
||||
};
|
||||
|
||||
static void nv_drm_event_callback(const struct NvKmsKapiEvent *event)
|
||||
@@ -264,6 +271,20 @@ static void nv_drm_event_callback(const struct NvKmsKapiEvent *event)
|
||||
event->u.displayChanged.display);
|
||||
break;
|
||||
|
||||
case NVKMS_EVENT_TYPE_DPY_CP_CHANGED:
|
||||
nv_drm_handle_display_cp_change(
|
||||
nv_dev,
|
||||
event->u.displayCpChanged.display,
|
||||
event->u.displayCpChanged.cp);
|
||||
break;
|
||||
|
||||
case NVKMS_EVENT_TYPE_DPY_CP_TOPOLOGY_CHANGED:
|
||||
nv_drm_handle_display_cp_topology_change(
|
||||
nv_dev,
|
||||
event->u.displayCpTopologyChanged.display,
|
||||
event->u.displayCpTopologyChanged.topology);
|
||||
break;
|
||||
|
||||
case NVKMS_EVENT_TYPE_DYNAMIC_DPY_CONNECTED:
|
||||
nv_drm_handle_dynamic_display_connected(
|
||||
nv_dev,
|
||||
@@ -284,6 +305,123 @@ done:
|
||||
mutex_unlock(&nv_dev->lock);
|
||||
}
|
||||
|
||||
struct nv_drm_mst_display_info {
|
||||
NvKmsKapiDisplay handle;
|
||||
NvBool isDpMST;
|
||||
char dpAddress[NVKMS_DP_ADDRESS_STRING_LENGTH];
|
||||
};
|
||||
|
||||
/*
|
||||
* Helper function to get DpMST display info.
|
||||
* dpMSTDisplayInfos is allocated dynamically,
|
||||
* so it needs to be freed after finishing the query.
|
||||
*/
|
||||
static int nv_drm_get_mst_display_infos
|
||||
(
|
||||
struct nv_drm_device *nv_dev,
|
||||
NvKmsKapiDisplay hDisplay,
|
||||
struct nv_drm_mst_display_info **dpMSTDisplayInfos,
|
||||
NvU32 *nDynamicDisplays
|
||||
)
|
||||
{
|
||||
struct NvKmsKapiStaticDisplayInfo *displayInfo = NULL;
|
||||
struct NvKmsKapiStaticDisplayInfo *dynamicDisplayInfo = NULL;
|
||||
struct NvKmsKapiConnectorInfo *connectorInfo = NULL;
|
||||
struct nv_drm_mst_display_info *displayInfos = NULL;
|
||||
NvU32 i = 0;
|
||||
int ret = 0;
|
||||
NVDpyId dpyId;
|
||||
*nDynamicDisplays = 0;
|
||||
|
||||
/* Query NvKmsKapiStaticDisplayInfo and NvKmsKapiConnectorInfo */
|
||||
|
||||
if ((displayInfo = nv_drm_calloc(1, sizeof(*displayInfo))) == NULL) {
|
||||
ret = -ENOMEM;
|
||||
goto done;
|
||||
}
|
||||
|
||||
if ((dynamicDisplayInfo = nv_drm_calloc(1, sizeof(*dynamicDisplayInfo))) == NULL) {
|
||||
ret = -ENOMEM;
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (!nvKms->getStaticDisplayInfo(nv_dev->pDevice, hDisplay, displayInfo)) {
|
||||
ret = -EINVAL;
|
||||
goto done;
|
||||
}
|
||||
|
||||
connectorInfo = nvkms_get_connector_info(nv_dev->pDevice,
|
||||
displayInfo->connectorHandle);
|
||||
|
||||
if (IS_ERR(connectorInfo)) {
|
||||
ret = PTR_ERR(connectorInfo);
|
||||
goto done;
|
||||
}
|
||||
|
||||
|
||||
*nDynamicDisplays = nvCountDpyIdsInDpyIdList(connectorInfo->dynamicDpyIdList);
|
||||
|
||||
if (*nDynamicDisplays == 0) {
|
||||
goto done;
|
||||
}
|
||||
|
||||
if ((displayInfos = nv_drm_calloc(*nDynamicDisplays, sizeof(*displayInfos))) == NULL) {
|
||||
ret = -ENOMEM;
|
||||
goto done;
|
||||
}
|
||||
|
||||
FOR_ALL_DPY_IDS(dpyId, connectorInfo->dynamicDpyIdList) {
|
||||
if (!nvKms->getStaticDisplayInfo(nv_dev->pDevice,
|
||||
nvDpyIdToNvU32(dpyId),
|
||||
dynamicDisplayInfo)) {
|
||||
ret = -EINVAL;
|
||||
nv_drm_free(displayInfos);
|
||||
goto done;
|
||||
}
|
||||
|
||||
displayInfos[i].handle = dynamicDisplayInfo->handle;
|
||||
displayInfos[i].isDpMST = dynamicDisplayInfo->isDpMST;
|
||||
memcpy(displayInfos[i].dpAddress, dynamicDisplayInfo->dpAddress, sizeof(dynamicDisplayInfo->dpAddress));
|
||||
|
||||
i++;
|
||||
}
|
||||
|
||||
*dpMSTDisplayInfos = displayInfos;
|
||||
|
||||
done:
|
||||
|
||||
nv_drm_free(displayInfo);
|
||||
|
||||
nv_drm_free(dynamicDisplayInfo);
|
||||
|
||||
nv_drm_free(connectorInfo);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int nv_drm_disp_cmp (const void *l, const void *r)
|
||||
{
|
||||
struct nv_drm_mst_display_info *l_info = (struct nv_drm_mst_display_info *)l;
|
||||
struct nv_drm_mst_display_info *r_info = (struct nv_drm_mst_display_info *)r;
|
||||
|
||||
return strcmp(l_info->dpAddress, r_info->dpAddress);
|
||||
}
|
||||
|
||||
/*
|
||||
* Helper function to sort the dpAddress in terms of string.
|
||||
* This function is to create DRM connectors ID order deterministically.
|
||||
* It's not numerically.
|
||||
*/
|
||||
static void nv_drm_sort_dynamic_displays_by_dp_addr
|
||||
(
|
||||
struct nv_drm_mst_display_info *infos,
|
||||
int nDynamicDisplays
|
||||
)
|
||||
{
|
||||
sort(infos, nDynamicDisplays, sizeof(*infos), nv_drm_disp_cmp, NULL);
|
||||
}
|
||||
|
||||
|
||||
/*
|
||||
* Helper function to initialize drm_device::mode_config from
|
||||
* NvKmsKapiDevice's resource information.
|
||||
@@ -365,9 +503,11 @@ static void nv_drm_enumerate_encoders_and_connectors
|
||||
nv_dev,
|
||||
"Failed to enumurate NvKmsKapiDisplay handles");
|
||||
} else {
|
||||
NvU32 i;
|
||||
NvU32 i, j;
|
||||
NvU32 nDynamicDisplays = 0;
|
||||
|
||||
for (i = 0; i < nDisplays; i++) {
|
||||
struct nv_drm_mst_display_info *displayInfos = NULL;
|
||||
struct drm_encoder *encoder =
|
||||
nv_drm_add_encoder(dev, hDisplays[i]);
|
||||
|
||||
@@ -377,6 +517,34 @@ static void nv_drm_enumerate_encoders_and_connectors
|
||||
"Failed to add connector for NvKmsKapiDisplay 0x%08x",
|
||||
hDisplays[i]);
|
||||
}
|
||||
|
||||
if (nv_drm_get_mst_display_infos(nv_dev, hDisplays[i],
|
||||
&displayInfos, &nDynamicDisplays)) {
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
nv_dev,
|
||||
"Failed to get dynamic displays");
|
||||
} else if (nDynamicDisplays) {
|
||||
nv_drm_sort_dynamic_displays_by_dp_addr(displayInfos, nDynamicDisplays);
|
||||
|
||||
for (j = 0; j < nDynamicDisplays; j++) {
|
||||
if (displayInfos[j].isDpMST) {
|
||||
struct drm_encoder *mst_encoder =
|
||||
nv_drm_add_encoder(dev, displayInfos[j].handle);
|
||||
|
||||
NV_DRM_DEV_DEBUG_DRIVER(nv_dev, "found DP MST port display handle %u",
|
||||
displayInfos[j].handle);
|
||||
|
||||
if (IS_ERR(mst_encoder)) {
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
nv_dev,
|
||||
"Failed to add connector for NvKmsKapiDisplay 0x%08x",
|
||||
displayInfos[j].handle);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
nv_drm_free(displayInfos);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -469,6 +637,14 @@ static int nv_drm_create_properties(struct nv_drm_device *nv_dev)
|
||||
}
|
||||
#endif
|
||||
|
||||
/* hdcp_topology is immutable by user space */
|
||||
nv_dev->nv_hdcp_topology_property =
|
||||
drm_property_create(nv_dev->dev, DRM_MODE_PROP_BLOB | DRM_MODE_PROP_IMMUTABLE,
|
||||
"NV_HDCP_TOPOLOGY", 0);
|
||||
if (nv_dev->nv_hdcp_topology_property == NULL) {
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -617,6 +793,8 @@ static int nv_drm_load(struct drm_device *dev, unsigned long flags)
|
||||
nv_dev->pDevice,
|
||||
((1 << NVKMS_EVENT_TYPE_DPY_CHANGED) |
|
||||
(1 << NVKMS_EVENT_TYPE_DYNAMIC_DPY_CONNECTED) |
|
||||
(1 << NVKMS_EVENT_TYPE_DPY_CP_CHANGED) |
|
||||
(1 << NVKMS_EVENT_TYPE_DPY_CP_TOPOLOGY_CHANGED) |
|
||||
(1 << NVKMS_EVENT_TYPE_FLIP_OCCURRED)))) {
|
||||
NV_DRM_DEV_LOG_ERR(nv_dev, "Failed to register event mask");
|
||||
}
|
||||
@@ -763,6 +941,62 @@ static void nv_drm_master_set(struct drm_device *dev,
|
||||
}
|
||||
#endif
|
||||
|
||||
static
|
||||
int nv_drm_reset_input_colorspace(struct drm_device *dev)
|
||||
{
|
||||
struct drm_atomic_state *state;
|
||||
struct drm_plane_state *plane_state;
|
||||
struct drm_plane *plane;
|
||||
struct nv_drm_plane_state *nv_drm_plane_state;
|
||||
struct drm_modeset_acquire_ctx ctx;
|
||||
int ret = 0;
|
||||
bool do_reset = false;
|
||||
NvU32 flags = 0;
|
||||
|
||||
state = drm_atomic_state_alloc(dev);
|
||||
if (!state)
|
||||
return -ENOMEM;
|
||||
|
||||
#if defined(DRM_MODESET_ACQUIRE_INTERRUPTIBLE)
|
||||
flags |= DRM_MODESET_ACQUIRE_INTERRUPTIBLE;
|
||||
#endif
|
||||
drm_modeset_acquire_init(&ctx, flags);
|
||||
state->acquire_ctx = &ctx;
|
||||
|
||||
nv_drm_for_each_plane(plane, dev) {
|
||||
plane_state = drm_atomic_get_plane_state(state, plane);
|
||||
if (IS_ERR(plane_state)) {
|
||||
ret = PTR_ERR(plane_state);
|
||||
goto out;
|
||||
}
|
||||
|
||||
nv_drm_plane_state = to_nv_drm_plane_state(plane_state);
|
||||
if (nv_drm_plane_state) {
|
||||
if (nv_drm_plane_state->input_colorspace != NVKMS_INPUT_COLORSPACE_NONE) {
|
||||
nv_drm_plane_state->input_colorspace = NVKMS_INPUT_COLORSPACE_NONE;
|
||||
do_reset = true;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (do_reset) {
|
||||
ret = drm_atomic_commit(state);
|
||||
}
|
||||
|
||||
out:
|
||||
#if defined(NV_DRM_ATOMIC_STATE_REF_COUNTING_PRESENT)
|
||||
drm_atomic_state_put(state);
|
||||
#else
|
||||
// In case of success, drm_atomic_commit() takes care to cleanup and free state.
|
||||
if (ret != 0) {
|
||||
drm_atomic_state_free(state);
|
||||
}
|
||||
#endif
|
||||
drm_modeset_drop_locks(&ctx);
|
||||
drm_modeset_acquire_fini(&ctx);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
#if defined(NV_DRM_MASTER_DROP_HAS_FROM_RELEASE_ARG)
|
||||
static
|
||||
@@ -806,6 +1040,12 @@ void nv_drm_master_drop(struct drm_device *dev, struct drm_file *file_priv)
|
||||
drm_modeset_unlock_all(dev);
|
||||
|
||||
nvKms->releaseOwnership(nv_dev->pDevice);
|
||||
} else {
|
||||
int err = nv_drm_reset_input_colorspace(dev);
|
||||
if (err != 0) {
|
||||
NV_DRM_DEV_LOG_WARN(nv_dev,
|
||||
"nv_drm_reset_input_colorspace failed with error code: %d !", err);
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
|
||||
@@ -1540,6 +1780,10 @@ static const struct file_operations nv_drm_fops = {
|
||||
.read = drm_read,
|
||||
|
||||
.llseek = noop_llseek,
|
||||
|
||||
#if defined(FOP_UNSIGNED_OFFSET)
|
||||
.fop_flags = FOP_UNSIGNED_OFFSET,
|
||||
#endif
|
||||
};
|
||||
|
||||
static const struct drm_ioctl_desc nv_drm_ioctls[] = {
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2015-2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -303,6 +303,47 @@ void nv_drm_handle_display_change(struct nv_drm_device *nv_dev,
|
||||
schedule_delayed_work(&nv_dev->hotplug_event_work, 0);
|
||||
}
|
||||
|
||||
void nv_drm_handle_display_cp_change(struct nv_drm_device *nv_dev,
|
||||
NvKmsKapiDisplay hDisplay,
|
||||
enum NvKmsContentProtection cp)
|
||||
{
|
||||
struct drm_device *dev = nv_dev->dev;
|
||||
struct nv_drm_encoder *nv_encoder = NULL;
|
||||
|
||||
nv_encoder = get_nv_encoder_from_nvkms_display(dev, hDisplay);
|
||||
if (nv_encoder == NULL) {
|
||||
return;
|
||||
}
|
||||
|
||||
mutex_lock(&dev->mode_config.mutex);
|
||||
|
||||
nv_encoder->nv_connector->cp = cp;
|
||||
|
||||
mutex_unlock(&dev->mode_config.mutex);
|
||||
|
||||
nv_drm_connector_update_content_protection(nv_encoder->nv_connector);
|
||||
}
|
||||
|
||||
void nv_drm_handle_display_cp_topology_change(struct nv_drm_device *nv_dev,
|
||||
NvKmsKapiDisplay hDisplay,
|
||||
struct NvKmsHdcpTopology *topology)
|
||||
{
|
||||
struct drm_device *dev = nv_dev->dev;
|
||||
struct nv_drm_encoder *nv_encoder = NULL;
|
||||
|
||||
mutex_lock(&dev->mode_config.mutex);
|
||||
|
||||
nv_encoder = get_nv_encoder_from_nvkms_display(dev, hDisplay);
|
||||
|
||||
mutex_unlock(&dev->mode_config.mutex);
|
||||
|
||||
if (nv_encoder == NULL) {
|
||||
NV_DRM_DEV_LOG_ERR(nv_dev, "Encoder not found for display %d", hDisplay);
|
||||
return;
|
||||
}
|
||||
nv_drm_connector_update_topology_property(nv_encoder->nv_connector, topology);
|
||||
}
|
||||
|
||||
void nv_drm_handle_dynamic_display_connected(struct nv_drm_device *nv_dev,
|
||||
NvKmsKapiDisplay hDisplay)
|
||||
{
|
||||
@@ -319,7 +360,7 @@ void nv_drm_handle_dynamic_display_connected(struct nv_drm_device *nv_dev,
|
||||
nv_encoder = get_nv_encoder_from_nvkms_display(dev, hDisplay);
|
||||
|
||||
if (nv_encoder != NULL) {
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
NV_DRM_DEV_LOG_INFO(
|
||||
nv_dev,
|
||||
"Encoder with NvKmsKapiDisplay 0x%08x already exists.",
|
||||
hDisplay);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2016-2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -60,6 +60,14 @@ nv_drm_add_encoder(struct drm_device *dev, NvKmsKapiDisplay hDisplay);
|
||||
void nv_drm_handle_display_change(struct nv_drm_device *nv_dev,
|
||||
NvKmsKapiDisplay hDisplay);
|
||||
|
||||
void nv_drm_handle_display_cp_change(struct nv_drm_device *nv_dev,
|
||||
NvKmsKapiDisplay hDisplay,
|
||||
enum NvKmsContentProtection cp);
|
||||
|
||||
void nv_drm_handle_display_cp_topology_change(struct nv_drm_device *nv_dev,
|
||||
NvKmsKapiDisplay hDisplay,
|
||||
struct NvKmsHdcpTopology *topology);
|
||||
|
||||
void nv_drm_handle_dynamic_display_connected(struct nv_drm_device *nv_dev,
|
||||
NvKmsKapiDisplay hDisplay);
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2016, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2016 - 2024, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -306,6 +306,36 @@ int nv_drm_atomic_helper_disable_all(struct drm_device *dev,
|
||||
for_each_plane_in_state(__state, plane, plane_state, __i)
|
||||
#endif
|
||||
|
||||
/*
|
||||
* for_each_new_plane_in_state() was added by kernel commit
|
||||
* 581e49fe6b411f407102a7f2377648849e0fa37f which was Signed-off-by:
|
||||
* Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
|
||||
* Daniel Vetter <daniel.vetter@ffwll.ch>
|
||||
*
|
||||
* This commit also added the old_state and new_state pointers to
|
||||
* __drm_planes_state. Because of this, the best that can be done on kernel
|
||||
* versions without this macro is for_each_plane_in_state.
|
||||
*/
|
||||
|
||||
/**
|
||||
* nv_drm_for_each_new_plane_in_state - iterate over all planes in an atomic update
|
||||
* @__state: &struct drm_atomic_state pointer
|
||||
* @plane: &struct drm_plane iteration cursor
|
||||
* @new_plane_state: &struct drm_plane_state iteration cursor for the new state
|
||||
* @__i: int iteration cursor, for macro-internal use
|
||||
*
|
||||
* This iterates over all planes in an atomic update, tracking only the new
|
||||
* state. This is useful in enable functions, where we need the new state the
|
||||
* hardware should be in when the atomic commit operation has completed.
|
||||
*/
|
||||
#if !defined(for_each_new_plane_in_state)
|
||||
#define nv_drm_for_each_new_plane_in_state(__state, plane, new_plane_state, __i) \
|
||||
nv_drm_for_each_plane_in_state(__state, plane, new_plane_state, __i)
|
||||
#else
|
||||
#define nv_drm_for_each_new_plane_in_state(__state, plane, new_plane_state, __i) \
|
||||
for_each_new_plane_in_state(__state, plane, new_plane_state, __i)
|
||||
#endif
|
||||
|
||||
static inline struct drm_connector *
|
||||
nv_drm_connector_lookup(struct drm_device *dev, struct drm_file *filep,
|
||||
uint32_t id)
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2015, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2015 - 2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -26,6 +26,7 @@
|
||||
|
||||
#include "nvidia-drm-priv.h"
|
||||
#include "nvidia-drm-modeset.h"
|
||||
#include "nvidia-drm-connector.h"
|
||||
#include "nvidia-drm-crtc.h"
|
||||
#include "nvidia-drm-os-interface.h"
|
||||
#include "nvidia-drm-helper.h"
|
||||
@@ -339,6 +340,14 @@ nv_drm_atomic_apply_modeset_config(struct drm_device *dev,
|
||||
}
|
||||
|
||||
}
|
||||
struct drm_connector *connector;
|
||||
struct drm_connector_state *connector_state;
|
||||
int j;
|
||||
nv_drm_for_each_connector_in_state(state, connector, connector_state, j) {
|
||||
if (connector->state->content_protection == DRM_MODE_CONTENT_PROTECTION_DESIRED) {
|
||||
nv_drm_connector_update_content_protection(to_nv_connector(connector));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (commit && nv_dev->supportsSyncpts) {
|
||||
@@ -360,6 +369,24 @@ int nv_drm_atomic_check(struct drm_device *dev,
|
||||
{
|
||||
int ret = 0;
|
||||
|
||||
#if defined(NV_DRM_COLOR_MGMT_AVAILABLE)
|
||||
struct drm_crtc *crtc;
|
||||
struct drm_crtc_state *crtc_state;
|
||||
int i;
|
||||
|
||||
nv_drm_for_each_crtc_in_state(state, crtc, crtc_state, i) {
|
||||
/*
|
||||
* if the color management changed on the crtc, we need to update the
|
||||
* crtc's plane's CSC matrices, so add the crtc's planes to the commit
|
||||
*/
|
||||
if (crtc_state->color_mgmt_changed) {
|
||||
if ((ret = drm_atomic_add_affected_planes(state, crtc)) != 0) {
|
||||
goto done;
|
||||
}
|
||||
}
|
||||
}
|
||||
#endif /* NV_DRM_COLOR_MGMT_AVAILABLE */
|
||||
|
||||
if ((ret = drm_atomic_helper_check(dev, state)) != 0) {
|
||||
goto done;
|
||||
}
|
||||
@@ -496,42 +523,56 @@ int nv_drm_atomic_commit(struct drm_device *dev,
|
||||
struct nv_drm_device *nv_dev = to_nv_device(dev);
|
||||
|
||||
/*
|
||||
* drm_mode_config_funcs::atomic_commit() mandates to return -EBUSY
|
||||
* for nonblocking commit if previous updates (commit tasks/flip event) are
|
||||
* pending. In case of blocking commits it mandates to wait for previous
|
||||
* updates to complete.
|
||||
* XXX: drm_mode_config_funcs::atomic_commit() mandates to return -EBUSY
|
||||
* for nonblocking commit if the commit would need to wait for previous
|
||||
* updates (commit tasks/flip event) to complete. In case of blocking
|
||||
* commits it mandates to wait for previous updates to complete. However,
|
||||
* the kernel DRM-KMS documentation does explicitly allow maintaining a
|
||||
* queue of outstanding commits.
|
||||
*
|
||||
* Our system already implements such a queue, but due to
|
||||
* bug 4054608, it is currently not used.
|
||||
*/
|
||||
if (nonblock) {
|
||||
nv_drm_for_each_crtc_in_state(state, crtc, crtc_state, i) {
|
||||
struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc);
|
||||
nv_drm_for_each_crtc_in_state(state, crtc, crtc_state, i) {
|
||||
struct nv_drm_crtc *nv_crtc = to_nv_crtc(crtc);
|
||||
|
||||
/*
|
||||
* Here you aren't required to hold nv_drm_crtc::flip_list_lock
|
||||
* because:
|
||||
*
|
||||
* The core DRM driver acquires lock for all affected crtcs before
|
||||
* calling into ->commit() hook, therefore it is not possible for
|
||||
* other threads to call into ->commit() hook affecting same crtcs
|
||||
* and enqueue flip objects into flip_list -
|
||||
*
|
||||
* nv_drm_atomic_commit_internal()
|
||||
* |-> nv_drm_atomic_apply_modeset_config(commit=true)
|
||||
* |-> nv_drm_crtc_enqueue_flip()
|
||||
*
|
||||
* Only possibility is list_empty check races with code path
|
||||
* dequeuing flip object -
|
||||
*
|
||||
* __nv_drm_handle_flip_event()
|
||||
* |-> nv_drm_crtc_dequeue_flip()
|
||||
*
|
||||
* But this race condition can't lead list_empty() to return
|
||||
* incorrect result. nv_drm_crtc_dequeue_flip() in the middle of
|
||||
* updating the list could not trick us into thinking the list is
|
||||
* empty when it isn't.
|
||||
*/
|
||||
/*
|
||||
* Here you aren't required to hold nv_drm_crtc::flip_list_lock
|
||||
* because:
|
||||
*
|
||||
* The core DRM driver acquires lock for all affected crtcs before
|
||||
* calling into ->commit() hook, therefore it is not possible for
|
||||
* other threads to call into ->commit() hook affecting same crtcs
|
||||
* and enqueue flip objects into flip_list -
|
||||
*
|
||||
* nv_drm_atomic_commit_internal()
|
||||
* |-> nv_drm_atomic_apply_modeset_config(commit=true)
|
||||
* |-> nv_drm_crtc_enqueue_flip()
|
||||
*
|
||||
* Only possibility is list_empty check races with code path
|
||||
* dequeuing flip object -
|
||||
*
|
||||
* __nv_drm_handle_flip_event()
|
||||
* |-> nv_drm_crtc_dequeue_flip()
|
||||
*
|
||||
* But this race condition can't lead list_empty() to return
|
||||
* incorrect result. nv_drm_crtc_dequeue_flip() in the middle of
|
||||
* updating the list could not trick us into thinking the list is
|
||||
* empty when it isn't.
|
||||
*/
|
||||
if (nonblock) {
|
||||
if (!list_empty(&nv_crtc->flip_list)) {
|
||||
return -EBUSY;
|
||||
}
|
||||
} else {
|
||||
if (wait_event_timeout(
|
||||
nv_dev->flip_event_wq,
|
||||
list_empty(&nv_crtc->flip_list),
|
||||
3 * HZ /* 3 second */) == 0) {
|
||||
NV_DRM_DEV_LOG_ERR(
|
||||
nv_dev,
|
||||
"Flip event timeout on head %u", nv_crtc->head);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2015-2025, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -158,6 +158,7 @@ struct nv_drm_device {
|
||||
#if defined(NV_DRM_HAS_HDR_OUTPUT_METADATA)
|
||||
struct drm_property *nv_hdr_output_metadata_property;
|
||||
#endif
|
||||
struct drm_property *nv_hdcp_topology_property;
|
||||
|
||||
struct nv_drm_device *next;
|
||||
|
||||
|
||||
@@ -87,6 +87,9 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += sync_file_get_fence
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_aperture_remove_conflicting_framebuffers
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_aperture_remove_conflicting_pci_framebuffers
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_fbdev_generic_setup
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_helper_crtc_enable_color_mgmt
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_crtc_enable_color_mgmt
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += drm_sysfs_connector_property_event
|
||||
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_present
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_bus_has_bus_type
|
||||
@@ -145,3 +148,4 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += drm_unlocked_ioctl_flag_present
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_aperture_remove_conflicting_framebuffers_has_driver_arg
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_aperture_remove_conflicting_framebuffers_has_no_primary_arg
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_aperture_remove_conflicting_pci_framebuffers_has_driver_arg
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += drm_mode_create_dp_colorspace_property_has_supported_colorspaces_arg
|
||||
|
||||
@@ -55,7 +55,7 @@ nvidia-modeset-y += $(NVIDIA_MODESET_BINARY_OBJECT_O)
|
||||
# Define nvidia-modeset.ko-specific CFLAGS.
|
||||
#
|
||||
|
||||
NVIDIA_MODESET_CFLAGS += -I$(src)/nvidia-modeset
|
||||
NVIDIA_MODESET_CFLAGS += -I$(src)/nvidia-modeset -I$(src)/common/inc
|
||||
NVIDIA_MODESET_CFLAGS += -UDEBUG -U_DEBUG -DNDEBUG -DNV_BUILD_MODULE_INSTANCES=0
|
||||
|
||||
$(call ASSIGN_PER_OBJ_CFLAGS, $(NVIDIA_MODESET_OBJECTS), $(NVIDIA_MODESET_CFLAGS))
|
||||
|
||||
@@ -290,8 +290,10 @@ static int parse_dsi_properties(const struct device_node *np_dsi, DSI_PANEL_INFO
|
||||
{
|
||||
u32 temp;
|
||||
int ret = 0;
|
||||
#if defined(NV_OF_PROPERTY_FOR_EACH_U32_HAS_INTERNAL_ARGS)
|
||||
const __be32 *p;
|
||||
struct property *prop;
|
||||
#endif
|
||||
struct device_node *np_dsi_panel;
|
||||
|
||||
// Get Panel Node from active-panel phandle
|
||||
@@ -493,7 +495,11 @@ static int parse_dsi_properties(const struct device_node *np_dsi, DSI_PANEL_INFO
|
||||
"nvidia,dsi-lvds-bridge", &temp))
|
||||
dsi->dsi2lvds_bridge_enable = (bool)temp;
|
||||
|
||||
#if defined(NV_OF_PROPERTY_FOR_EACH_U32_HAS_INTERNAL_ARGS)
|
||||
of_property_for_each_u32(np_dsi_panel, "nvidia,dsi-dpd-pads", prop, p, temp)
|
||||
#else
|
||||
of_property_for_each_u32(np_dsi_panel, "nvidia,dsi-dpd-pads", temp)
|
||||
#endif
|
||||
dsi->dpd_dsi_pads |= (u32)temp;
|
||||
|
||||
if (!of_property_read_u32(np_dsi_panel,
|
||||
|
||||
@@ -852,6 +852,8 @@ static int nv_platform_device_display_probe(struct platform_device *plat_dev)
|
||||
nv->mipical_regs->cpu_address = res_addr;
|
||||
nv->mipical_regs->size = res_size;
|
||||
|
||||
pm_vt_switch_required(&plat_dev->dev, NV_TRUE);
|
||||
|
||||
// Enabling power management for the device.
|
||||
pm_runtime_enable(&plat_dev->dev);
|
||||
|
||||
@@ -1073,18 +1075,18 @@ err_free_stack:
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int nv_platform_device_display_remove(struct platform_device *plat_dev)
|
||||
static void nv_platform_device_display_remove(struct platform_device *plat_dev)
|
||||
{
|
||||
nv_linux_state_t *nvl = NULL;
|
||||
nv_state_t *nv;
|
||||
nvidia_stack_t *sp = NULL;
|
||||
int rc;
|
||||
|
||||
nv_printf(NV_DBG_SETUP, "NVRM: removing SOC Display device\n");
|
||||
|
||||
rc = nv_kmem_cache_alloc_stack(&sp);
|
||||
if (rc < 0)
|
||||
return rc;
|
||||
if (WARN_ON(nv_kmem_cache_alloc_stack(&sp) < 0))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
LOCK_NV_LINUX_DEVICES();
|
||||
nvl = platform_get_drvdata(plat_dev);
|
||||
@@ -1162,13 +1164,13 @@ static int nv_platform_device_display_remove(struct platform_device *plat_dev)
|
||||
|
||||
nv_kmem_cache_free_stack(sp);
|
||||
|
||||
return 0;
|
||||
return;
|
||||
|
||||
done:
|
||||
UNLOCK_NV_LINUX_DEVICES();
|
||||
nv_kmem_cache_free_stack(sp);
|
||||
|
||||
return 0;
|
||||
return;
|
||||
}
|
||||
|
||||
static int nv_platform_device_probe(struct platform_device *plat_dev)
|
||||
@@ -1189,24 +1191,34 @@ static int nv_platform_device_probe(struct platform_device *plat_dev)
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int nv_platform_device_remove(struct platform_device *plat_dev)
|
||||
static void nv_platform_device_remove(struct platform_device *plat_dev)
|
||||
{
|
||||
int rc = 0;
|
||||
|
||||
if (plat_dev->dev.of_node)
|
||||
{
|
||||
{
|
||||
rc = nv_platform_device_display_remove(plat_dev);
|
||||
nv_platform_device_display_remove(plat_dev);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
rc = nv_platform_device_display_remove(plat_dev);
|
||||
nv_platform_device_display_remove(plat_dev);
|
||||
}
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
#if defined(NV_PLATFORM_DRIVER_STRUCT_REMOVE_RETURNS_VOID) /* Linux v6.11 */
|
||||
static void nv_platform_device_remove_wrapper(struct platform_device *pdev)
|
||||
{
|
||||
nv_platform_device_remove(pdev);
|
||||
}
|
||||
#else
|
||||
static int nv_platform_device_remove_wrapper(struct platform_device *pdev)
|
||||
{
|
||||
nv_platform_device_remove(pdev);
|
||||
|
||||
return 0;
|
||||
}
|
||||
#endif
|
||||
|
||||
const struct of_device_id nv_platform_device_table[] =
|
||||
{
|
||||
{ .compatible = "nvidia,tegra234-display",},
|
||||
@@ -1228,7 +1240,7 @@ struct platform_driver nv_platform_driver = {
|
||||
#endif
|
||||
},
|
||||
.probe = nv_platform_device_probe,
|
||||
.remove = nv_platform_device_remove,
|
||||
.remove = nv_platform_device_remove_wrapper,
|
||||
};
|
||||
|
||||
int nv_platform_count_devices(void)
|
||||
|
||||
@@ -249,6 +249,8 @@ NV_CONFTEST_TYPE_COMPILE_TESTS += num_registered_fb
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += pci_driver_has_driver_managed_dma
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += vm_area_struct_has_const_vm_flags
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += memory_failure_has_trapno_arg
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += of_property_for_each_u32_has_internal_args
|
||||
NV_CONFTEST_TYPE_COMPILE_TESTS += platform_driver_struct_remove_returns_void
|
||||
|
||||
NV_CONFTEST_GENERIC_COMPILE_TESTS += dom0_kernel_present
|
||||
NV_CONFTEST_GENERIC_COMPILE_TESTS += nvidia_vgpu_kvm_build
|
||||
|
||||
@@ -1 +1 @@
|
||||
rel-36_eng_2024-10-24
|
||||
rel-36_eng_2025-12-11
|
||||
|
||||
@@ -565,6 +565,7 @@ namespace DisplayPort
|
||||
void freeTimeslice(GroupImpl * targetGroup);
|
||||
void flushTimeslotsToHardware();
|
||||
void hdcpRenegotiate(NvU64 cN, NvU64 cKsv);
|
||||
void hdcpActiveGroupsSetECF();
|
||||
bool getHDCPAbortCodesDP12(NvU32 &hdcpAbortCodesDP12);
|
||||
bool getOuiSink(unsigned &ouiId, char * modelName, size_t modelNameBufferSize, NvU8 & chipRevision);
|
||||
bool hdcpValidateKsv(const NvU8 *ksv, NvU32 Size);
|
||||
|
||||
@@ -2141,6 +2141,24 @@ void ConnectorImpl::releaseLinkHandsOff()
|
||||
assessLink();
|
||||
}
|
||||
|
||||
void ConnectorImpl::hdcpActiveGroupsSetECF()
|
||||
{
|
||||
NvU64 ecf = 0x0;
|
||||
// Set the ECF for the groups which are already active.
|
||||
for (ListElement *i = this->activeGroups.begin(); i != this->activeGroups.end(); i = i->next)
|
||||
{
|
||||
GroupImpl * group = (GroupImpl *)i;
|
||||
if (group->hdcpEnabled)
|
||||
{
|
||||
NvU64 countOnes = (((NvU64)1) << group->timeslot.count) - 1;
|
||||
NvU64 mask = countOnes << group->timeslot.begin;
|
||||
ecf |= mask;
|
||||
}
|
||||
}
|
||||
// Restore the ECF and trigger ACT
|
||||
main->configureAndTriggerECF(ecf);
|
||||
}
|
||||
|
||||
//
|
||||
// Timer callback for event management
|
||||
// Uses: fireEvents()
|
||||
@@ -2160,7 +2178,10 @@ void ConnectorImpl::expired(const void * tag)
|
||||
while (!(hdcpEnableTransitionGroups.isEmpty()))
|
||||
{
|
||||
GroupImpl* curStrmEncrEnblGroup = hdcpEnableTransitionGroups.pop();
|
||||
curStrmEncrEnblGroup->hdcpSetEncrypted(true);
|
||||
if (!(curStrmEncrEnblGroup->hdcpEnabled))
|
||||
{
|
||||
curStrmEncrEnblGroup->hdcpSetEncrypted(true, NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_TYPE_1);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -2169,10 +2190,12 @@ void ConnectorImpl::expired(const void * tag)
|
||||
if (authRetries < HDCP_AUTHENTICATION_RETRIES)
|
||||
{
|
||||
HDCPState hdcpState = {0};
|
||||
// Get hdcp state which will be !HDCP_State_Authenticated for the first entry and
|
||||
// subsequently it will reflect the result of last fired configureHDCPRenegotiate
|
||||
main->configureHDCPGetHDCPState(hdcpState);
|
||||
|
||||
unsigned authDelay = (hdcpState.HDCP_State_22_Capable ?
|
||||
HDCP22_AUTHENTICATION_COOLDOWN : HDCP_AUTHENTICATION_COOLDOWN);
|
||||
HDCP22_AUTHENTICATION_COOLDOWN * 2 : HDCP_AUTHENTICATION_COOLDOWN);
|
||||
|
||||
// Don't fire any reauthentication if we're not done with the modeset
|
||||
if (!intransitionGroups.isEmpty())
|
||||
@@ -2190,26 +2213,23 @@ void ConnectorImpl::expired(const void * tag)
|
||||
|
||||
authRetries++;
|
||||
isHDCPAuthTriggered = true;
|
||||
main->configureHDCPRenegotiate();
|
||||
main->configureHDCPGetHDCPState(hdcpState);
|
||||
|
||||
// Skip configureHDCPRenegotiate if HDCP is already enabled from previous
|
||||
// previous call to configureHDCPRenegotiate
|
||||
if (!hdcpState.HDCP_State_Authenticated)
|
||||
{
|
||||
main->configureHDCPRenegotiate();
|
||||
// Get fresh hdcp state after Renegotiate as HDCP1X can be enabled
|
||||
// synchronously by configureHDCPRenegotiate (HDCP2X takes time)
|
||||
main->configureHDCPGetHDCPState(hdcpState);
|
||||
}
|
||||
|
||||
if (hdcpState.HDCP_State_Authenticated)
|
||||
{
|
||||
isHDCPAuthOn = true;
|
||||
authRetries = 0;
|
||||
// Set the ECF for the groups which are already active.
|
||||
for (ListElement *i = this->activeGroups.begin(); i != this->activeGroups.end(); i = i->next)
|
||||
{
|
||||
GroupImpl * group = (GroupImpl *)i;
|
||||
if (group->hdcpEnabled)
|
||||
{
|
||||
NvU64 countOnes = (((NvU64)1) << group->timeslot.count) - 1;
|
||||
NvU64 mask = countOnes << group->timeslot.begin;
|
||||
ecf |= mask;
|
||||
}
|
||||
}
|
||||
// Restore the ECF and trigger ACT
|
||||
main->configureAndTriggerECF(ecf);
|
||||
hdcpActiveGroupsSetECF();
|
||||
// Enable HDCP for Group
|
||||
if (!(bHdcpStrmEncrEnblOnlyOnDemand))
|
||||
{
|
||||
@@ -3260,6 +3280,12 @@ void ConnectorImpl::notifyAttachEnd(bool modesetCancelled)
|
||||
}
|
||||
}
|
||||
|
||||
{ // Set stream type and bEnforceType0Hdcp1xDS upfront before enabling hdcp with hub
|
||||
bool bNeedReNegotiate = false;
|
||||
main->setStreamType(currentModesetDeviceGroup->streamIndex,
|
||||
NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_TYPE_1, &bNeedReNegotiate);
|
||||
}
|
||||
|
||||
//
|
||||
// RM has the requirement of Head being ARMed to do authentication.
|
||||
// Postpone the authentication until the NAE to do the authentication for DP1.2 as solution.
|
||||
@@ -3486,6 +3512,27 @@ void ConnectorImpl::notifyDetachEnd(bool bKeepOdAlive)
|
||||
if (this->policyModesetOrderMitigation && this->modesetOrderMitigation)
|
||||
this->modesetOrderMitigation = false;
|
||||
}
|
||||
else // !activeGroups.isEmpty()
|
||||
{
|
||||
if ((this->linkUseMultistream()) && (hdcpState.HDCP_State_Authenticated))
|
||||
{
|
||||
if (hdcpState.HDCP_State_22_Capable)
|
||||
{
|
||||
main->configureAndTriggerECF(0x0);
|
||||
authRetries = 0;
|
||||
isHDCPAuthOn = false;
|
||||
// numOfStream changed, AKE_Init needed to change dpTypeMask
|
||||
main->configureHDCPRenegotiate();
|
||||
// ReAuth, so schedule callback to check state later.
|
||||
timer->queueCallback(this, &tagHDCPReauthentication, HDCP_AUTHENTICATION_COOLDOWN);
|
||||
}
|
||||
else
|
||||
{
|
||||
hdcpActiveGroupsSetECF();
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
fireEvents();
|
||||
}
|
||||
|
||||
|
||||
@@ -546,7 +546,7 @@ bool EvoMainLink::setStreamType(unsigned streamIndex, NvU8 streamType, bool * bN
|
||||
// 1. Will it stop engaging HWDRM with this fix ?
|
||||
// 2. VPR blanking gets applied and blanks repeater display as well
|
||||
//
|
||||
paramsHdcpCtrl.bEnforceType0Hdcp1xDS = (streamType == NV0073_CTRL_SPECIFIC_HDCP_CTRL_HDCP22_TYPE_1);
|
||||
paramsHdcpCtrl.bEnforceType0Hdcp1xDS = NV_TRUE;
|
||||
|
||||
paramsHdcpCtrl.cmd |= DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _CMD,
|
||||
_SET_TYPE);
|
||||
|
||||
@@ -491,6 +491,16 @@ bool GroupImpl::hdcpSetEncrypted(bool encrypted, NvU8 streamType, NvBool bForce
|
||||
if (this->headIndex == group->headIndex)
|
||||
{
|
||||
group->hdcpEnabled = false;
|
||||
{ // Inform ConnectorEventSink that we have disabled HDCP on this Device
|
||||
Device * d = 0;
|
||||
for (d = ((Group*)this)->enumDevices(0); d != 0; d = ((Group*)this)->enumDevices(d))
|
||||
{
|
||||
if (((DeviceImpl*)d)->isHDCPCap == True)
|
||||
{
|
||||
parent->sink->notifyHDCPCapDone(d, False);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -629,6 +639,16 @@ void GroupImpl::hdcpMSTQSEandSetECF()
|
||||
{
|
||||
DP_ASSERT(group->hdcpEnabled == false);
|
||||
group->hdcpEnabled = true;
|
||||
{ // Inform ConnectorEventSink that we have enabled HDCP on this Device
|
||||
Device * d = 0;
|
||||
for (d = ((Group*)this)->enumDevices(0); d != 0; d = ((Group*)this)->enumDevices(d))
|
||||
{
|
||||
if (((DeviceImpl*)d)->isHDCPCap == True)
|
||||
{
|
||||
parent->sink->notifyHDCPCapDone(d, True);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
#if defined(NV_LINUX) || defined(NV_BSD) || defined(NV_SUNOS) || defined(NV_VMWARE) || defined(NV_QNX) || defined(NV_INTEGRITY) || \
|
||||
(defined(RMCFG_FEATURE_PLATFORM_GSP) && RMCFG_FEATURE_PLATFORM_GSP == 1)
|
||||
|
||||
#define NV_VERSION_STRING "540.4.0"
|
||||
#define NV_VERSION_STRING "540.5.0"
|
||||
|
||||
#else
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2022 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -1279,6 +1279,16 @@ typedef struct NV0073_CTRL_SPECIFIC_HDCP_CTRL_PARAMS {
|
||||
NvBool bEnforceType0Hdcp1xDS;
|
||||
|
||||
NvBool bPendingKsvListReady;
|
||||
|
||||
NvBool isHdcpCapable;
|
||||
NvBool isHdcpAuthOn;
|
||||
NvBool isHdcpRp;
|
||||
NvBool isHdcp2X;
|
||||
NvBool bMaxCascadeExceeded;
|
||||
NvBool bMaxDeviceExceeded;
|
||||
NvBool bHdcp1DevDownstream;
|
||||
NvBool bHdcp2LegacyDevDownstream;
|
||||
NvU8 cascadeDepth;
|
||||
} NV0073_CTRL_SPECIFIC_HDCP_CTRL_PARAMS;
|
||||
|
||||
#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_ERR_UNSUCCESSFUL 0:0
|
||||
@@ -1310,6 +1320,7 @@ typedef struct NV0073_CTRL_SPECIFIC_HDCP_CTRL_PARAMS {
|
||||
#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_SET_TYPE (0x0000009U)
|
||||
#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_FORWARD_KSVLIST_READY (0x000000AU)
|
||||
#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_READ_LINK_STATUS_NO_DISPLAY (0x000000BU)
|
||||
#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_CMD_READ_TOPOLOGY (0x000000CU)
|
||||
|
||||
#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BCAPS_PRESENT 0:0
|
||||
#define NV0073_CTRL_SPECIFIC_HDCP_CTRL_FLAGS_BCAPS_PRESENT_NO (0x0000000U)
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2013-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2013-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -28,5 +28,18 @@
|
||||
|
||||
void nvHandleHotplugEventDeferredWork(void *dataPtr, NvU32 dataU32);
|
||||
void nvHandleDPIRQEventDeferredWork(void *dataPtr, NvU32 dataU32);
|
||||
void nvHandleCpEventDeferredWork(void *dataPtr, NvU32 dataU32);
|
||||
|
||||
typedef enum
|
||||
{
|
||||
hdcpStatusChangeNotif_DontCare = 0,
|
||||
hdcpStatusChangeNotif_EncEnabled,
|
||||
hdcpStatusChangeNotif_RepComplete,
|
||||
hdcpStatusChangeNotif_KsvOk,
|
||||
hdcpStatusChangeNotif_HdcpDisabled,
|
||||
hdcpStatusChangeNotif_HdcpInactive,
|
||||
hdcpStatusChangeNotif_LinkFailed,
|
||||
hdcpStatusChangeNotif_HdcpRestart
|
||||
} HDCPSTATUSCHANGENOTIF, *PHDCPSTATUSCHANGENOTIF;
|
||||
|
||||
#endif /* __NVKMS_EVENT_H__ */
|
||||
|
||||
@@ -30,6 +30,7 @@ typedef struct {
|
||||
struct {
|
||||
enum NvKmsOutputTf tf;
|
||||
enum NvKmsOutputColorimetry colorimetry;
|
||||
enum NvKmsDpyAttributeColorRangeValue outputColorRange;
|
||||
enum NvKmsDpyAttributeCurrentColorSpaceValue colorSpace;
|
||||
enum NvKmsDpyAttributeColorBpcValue colorBpc;
|
||||
enum NvKmsDpyAttributeColorRangeValue colorRange;
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -37,6 +37,7 @@ void nvFreePerOpenDev(struct NvKmsPerOpen *pOpen,
|
||||
struct NvKmsPerOpenDev *pOpenDev);
|
||||
|
||||
void nvSendDpyEventEvo(const NVDpyEvoRec *pDpyEvo, const NvU32 eventType);
|
||||
void nvSendDpyClearEventEvo(const NVDpyEvoRec *pDpyEvo, const NvU32 eventType);
|
||||
|
||||
void nvSendDpyAttributeChangedEventEvo(const NVDpyEvoRec *pDpyEvo,
|
||||
const enum NvKmsDpyAttribute attribute,
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2013-2020 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2013-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -36,6 +36,12 @@ NvBool nvWriteDPCDReg(NVConnectorEvoPtr pConnectorEvo,
|
||||
NvU32 dpcdAddr,
|
||||
NvU8 dpcdData);
|
||||
|
||||
void nvGetContentProtectionState(NVConnectorEvoPtr pConnectorEvo,
|
||||
enum NvKmsContentProtection *cp);
|
||||
|
||||
void nvGetContentProtectionTopology(NVConnectorEvoPtr pConnectorEvo,
|
||||
struct NvKmsHdcpTopology *topology);
|
||||
|
||||
NvBool nvRmRegisterCallback(const NVDevEvoRec *pDevEvo,
|
||||
NVOS10_EVENT_KERNEL_CALLBACK_EX *cb,
|
||||
struct nvkms_ref_ptr *ref_ptr,
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2010-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2010-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -694,6 +694,9 @@ typedef struct {
|
||||
enum NvKmsOutputTf tf;
|
||||
|
||||
enum NvKmsOutputColorimetry colorimetry;
|
||||
|
||||
enum NvKmsDpyAttributeColorRangeValue outputColorRange;
|
||||
|
||||
NvBool skipLayerPendingFlips[NVKMS_MAX_LAYERS_PER_HEAD];
|
||||
|
||||
struct {
|
||||
@@ -703,6 +706,7 @@ typedef struct {
|
||||
NvBool tf : 1;
|
||||
NvBool hdrStaticMetadata : 1;
|
||||
NvBool colorimetry : 1;
|
||||
NvBool outputColorRange : 1;
|
||||
|
||||
NvBool layerPosition[NVKMS_MAX_LAYERS_PER_HEAD];
|
||||
NvBool layerSyncObjects[NVKMS_MAX_LAYERS_PER_HEAD];
|
||||
@@ -1554,6 +1558,8 @@ typedef struct _NVConnectorEvoRec {
|
||||
|
||||
NvEldCase audioDevEldCase[NV_MAX_AUDIO_DEVICE_ENTRIES];
|
||||
|
||||
struct NvKmsHdcpTopology cpTopology;
|
||||
|
||||
NvBool isHdmiEnabled;
|
||||
} NVConnectorEvoRec;
|
||||
|
||||
@@ -1752,6 +1758,8 @@ typedef struct _NVDispHeadStateEvoRec {
|
||||
|
||||
enum NvKmsOutputColorimetry colorimetry;
|
||||
|
||||
enum NvKmsDpyAttributeColorRangeValue outputColorRange;
|
||||
|
||||
struct {
|
||||
enum NvKmsHDROutputState outputState;
|
||||
struct NvKmsHDRStaticMetadata staticMetadata;
|
||||
@@ -1803,6 +1811,8 @@ typedef struct _NVDispApiHeadStateEvoRec {
|
||||
|
||||
enum NvKmsOutputColorimetry colorimetry;
|
||||
|
||||
enum NvKmsDpyAttributeColorRangeValue outputColorRange;
|
||||
|
||||
nvkms_timer_handle_t *hdrToSdrTransitionTimer;
|
||||
|
||||
/*
|
||||
@@ -1847,8 +1857,10 @@ typedef struct _NVDispEvoRec {
|
||||
NVDevEvoPtr pDevEvo;
|
||||
NvU32 hotplugEventHandle;
|
||||
NvU32 DPIRQEventHandle;
|
||||
NvU32 cpEventHandle;
|
||||
NVOS10_EVENT_KERNEL_CALLBACK_EX rmHotplugCallback;
|
||||
NVOS10_EVENT_KERNEL_CALLBACK_EX rmDPIRQCallback;
|
||||
NVOS10_EVENT_KERNEL_CALLBACK_EX rmCpCallback;
|
||||
|
||||
NVDispHeadStateEvoRec headState[NVKMS_MAX_HEADS_PER_DISP];
|
||||
NVDispApiHeadStateEvoRec apiHeadState[NVKMS_MAX_HEADS_PER_DISP];
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -180,6 +180,8 @@ enum NvKmsEventType {
|
||||
NVKMS_EVENT_TYPE_DPY_ATTRIBUTE_CHANGED,
|
||||
NVKMS_EVENT_TYPE_FRAMELOCK_ATTRIBUTE_CHANGED,
|
||||
NVKMS_EVENT_TYPE_FLIP_OCCURRED,
|
||||
NVKMS_EVENT_TYPE_DPY_CP_CHANGED,
|
||||
NVKMS_EVENT_TYPE_DPY_CP_TOPOLOGY_CHANGED,
|
||||
};
|
||||
|
||||
typedef enum {
|
||||
@@ -692,4 +694,31 @@ struct NvKmsSuperframeInfo {
|
||||
|
||||
typedef void (*NVVBlankIntrCallbackProc)(NvU64 param1, NvU64 param2);
|
||||
|
||||
enum NvKmsContentProtection {
|
||||
NVKMS_CP_OFF = 0,
|
||||
NVKMS_CP_HDCP1X_ON = 1,
|
||||
NVKMS_CP_HDCP2X_TYPE0_ON = 2,
|
||||
NVKMS_CP_HDCP2X_TYPE1_ON = 3,
|
||||
};
|
||||
|
||||
#define HDCP_TOPOLOGY_MAX_LINK_COUNT (2)
|
||||
#define HDCP_TOPOLOGY_MAX_DEV_COUNT (255)
|
||||
#define HDCP_TOPOLOGY_KSV_SIZE (5)
|
||||
|
||||
struct NvKmsHdcpTopology {
|
||||
NvBool isHdcpCapable;
|
||||
NvBool isHdcpAuthOn;
|
||||
NvBool isHdcpRp;
|
||||
NvBool isHdcp2X;
|
||||
NvBool maxCascadeExceeded;
|
||||
NvBool maxDeviceExceeded;
|
||||
NvBool isHdcp1DevDownstream;
|
||||
NvBool isHdcp2LegacyDevDownstream;
|
||||
NvU8 cascadeDepth;
|
||||
NvU8 linkCount;
|
||||
NvU8 bksv[HDCP_TOPOLOGY_MAX_LINK_COUNT * HDCP_TOPOLOGY_KSV_SIZE];
|
||||
NvU8 numOfBksv;
|
||||
NvU8 bksvList[HDCP_TOPOLOGY_MAX_DEV_COUNT * HDCP_TOPOLOGY_KSV_SIZE];
|
||||
};
|
||||
|
||||
#endif /* NVKMS_API_TYPES_H */
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -758,6 +758,14 @@ struct NvKmsFlipCommonParams {
|
||||
enum NvKmsOutputColorimetry val;
|
||||
} colorimetry;
|
||||
|
||||
/*
|
||||
* Specifies required output color range value.
|
||||
*/
|
||||
struct {
|
||||
NvBool specified;
|
||||
enum NvKmsDpyAttributeColorRangeValue val;
|
||||
} outputcolorrange;
|
||||
|
||||
struct {
|
||||
struct {
|
||||
NvKmsSurfaceHandle handle[NVKMS_MAX_EYES];
|
||||
@@ -3053,6 +3061,32 @@ struct NvKmsEventFlipOccurred {
|
||||
};
|
||||
|
||||
|
||||
/*!
|
||||
* NVKMS_EVENT_TYPE_DPY_CP_CHANGED
|
||||
*
|
||||
* When a dpy content protection status changes, this event will be generated.
|
||||
*/
|
||||
|
||||
struct NvKmsEventDpyCpChanged {
|
||||
NvKmsDeviceHandle deviceHandle;
|
||||
NvKmsDispHandle dispHandle;
|
||||
NVDpyId dpyId;
|
||||
enum NvKmsContentProtection cp;
|
||||
};
|
||||
|
||||
/*!
|
||||
* NVKMS_EVENT_TYPE_DPY_CP_TOPOLOGY_CHANGED
|
||||
*
|
||||
* When a dpy content protection topology changes, this event will be generated.
|
||||
*/
|
||||
|
||||
struct NvKmsEventDpyCpTopologyChanged {
|
||||
NvKmsDeviceHandle deviceHandle;
|
||||
NvKmsDispHandle dispHandle;
|
||||
NVDpyId dpyId;
|
||||
struct NvKmsHdcpTopology *topology;
|
||||
};
|
||||
|
||||
struct NvKmsEvent {
|
||||
enum NvKmsEventType eventType;
|
||||
union {
|
||||
@@ -3062,6 +3096,8 @@ struct NvKmsEvent {
|
||||
struct NvKmsEventDpyAttributeChanged dpyAttributeChanged;
|
||||
struct NvKmsEventFrameLockAttributeChanged frameLockAttributeChanged;
|
||||
struct NvKmsEventFlipOccurred flipOccurred;
|
||||
struct NvKmsEventDpyCpChanged dpyCpChanged;
|
||||
struct NvKmsEventDpyCpTopologyChanged dpyCpTopologyChanged;
|
||||
} u;
|
||||
};
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -26,6 +26,7 @@
|
||||
#include "nvtypes.h"
|
||||
|
||||
#include "nv-gpu-info.h"
|
||||
#include "nv_dpy_id.h"
|
||||
#include "nvkms-api-types.h"
|
||||
#include "nvkms-format.h"
|
||||
|
||||
@@ -190,6 +191,7 @@ struct NvKmsKapiConnectorInfo {
|
||||
NvU32 numIncompatibleConnectors;
|
||||
NvKmsKapiConnector incompatibleConnectorHandles[NVKMS_KAPI_MAX_CONNECTORS];
|
||||
|
||||
NVDpyIdList dynamicDpyIdList;
|
||||
};
|
||||
|
||||
struct NvKmsKapiStaticDisplayInfo {
|
||||
@@ -208,6 +210,8 @@ struct NvKmsKapiStaticDisplayInfo {
|
||||
NvKmsKapiDisplay possibleCloneHandles[NVKMS_KAPI_MAX_CLONE_DISPLAYS];
|
||||
|
||||
NvU32 headMask;
|
||||
|
||||
NvBool isDpMST;
|
||||
};
|
||||
|
||||
struct NvKmsKapiSyncpt {
|
||||
@@ -249,6 +253,8 @@ struct NvKmsKapiLayerConfig {
|
||||
|
||||
enum NvKmsInputColorSpace inputColorSpace;
|
||||
enum NvKmsInputColorRange inputColorRange;
|
||||
struct NvKmsCscMatrix csc;
|
||||
NvBool cscUseMain;
|
||||
};
|
||||
|
||||
struct NvKmsKapiLayerRequestedConfig {
|
||||
@@ -259,6 +265,7 @@ struct NvKmsKapiLayerRequestedConfig {
|
||||
NvBool srcWHChanged : 1;
|
||||
NvBool dstXYChanged : 1;
|
||||
NvBool dstWHChanged : 1;
|
||||
NvBool cscChanged : 1;
|
||||
} flags;
|
||||
};
|
||||
|
||||
@@ -348,6 +355,16 @@ struct NvKmsKapiEventDisplayChanged {
|
||||
NvKmsKapiDisplay display;
|
||||
};
|
||||
|
||||
struct NvKmsKapiEventDisplayCpChanged {
|
||||
NvKmsKapiDisplay display;
|
||||
enum NvKmsContentProtection cp;
|
||||
};
|
||||
|
||||
struct NvKmsKapiEventDisplayCpTopologyChanged {
|
||||
NvKmsKapiDisplay display;
|
||||
struct NvKmsHdcpTopology *topology;
|
||||
};
|
||||
|
||||
struct NvKmsKapiEventDynamicDisplayConnected {
|
||||
NvKmsKapiDisplay display;
|
||||
};
|
||||
@@ -379,6 +396,8 @@ struct NvKmsKapiEvent {
|
||||
struct NvKmsKapiEventDisplayChanged displayChanged;
|
||||
struct NvKmsKapiEventDynamicDisplayConnected dynamicDisplayConnected;
|
||||
struct NvKmsKapiEventFlipOccurred flipOccurred;
|
||||
struct NvKmsKapiEventDisplayCpChanged displayCpChanged;
|
||||
struct NvKmsKapiEventDisplayCpTopologyChanged displayCpTopologyChanged;
|
||||
} u;
|
||||
};
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -62,6 +62,8 @@ ct_assert(NVKMS_KAPI_LAYER_MAX == NVKMS_MAX_LAYERS_PER_HEAD);
|
||||
#define NVKMS_KAPI_SUPPORTED_EVENTS_MASK \
|
||||
((1 << NVKMS_EVENT_TYPE_DPY_CHANGED) | \
|
||||
(1 << NVKMS_EVENT_TYPE_DYNAMIC_DPY_CONNECTED) | \
|
||||
(1 << NVKMS_EVENT_TYPE_DPY_CP_CHANGED) | \
|
||||
(1 << NVKMS_EVENT_TYPE_DPY_CP_TOPOLOGY_CHANGED) | \
|
||||
(1 << NVKMS_EVENT_TYPE_FLIP_OCCURRED))
|
||||
|
||||
static NvU32 EnumerateGpus(nv_gpu_info_t *gpuInfo)
|
||||
@@ -1170,7 +1172,10 @@ static NvBool GetConnectorInfo
|
||||
)
|
||||
{
|
||||
struct NvKmsQueryConnectorStaticDataParams paramsConnector = { };
|
||||
struct NvKmsQueryConnectorDynamicDataParams paramsDynamicConnector = { };
|
||||
NvBool status = NV_FALSE;
|
||||
NvU64 startTime = 0;
|
||||
NvBool timeout;
|
||||
|
||||
if (device == NULL || info == NULL) {
|
||||
goto done;
|
||||
@@ -1201,6 +1206,44 @@ static NvBool GetConnectorInfo
|
||||
|
||||
info->type = paramsConnector.reply.type;
|
||||
|
||||
|
||||
startTime = nvkms_get_usec();
|
||||
do {
|
||||
nvkms_memset(¶msDynamicConnector, 0, sizeof(paramsDynamicConnector));
|
||||
paramsDynamicConnector.request.deviceHandle = device->hKmsDevice;
|
||||
paramsDynamicConnector.request.dispHandle = device->hKmsDisp;
|
||||
paramsDynamicConnector.request.connectorHandle = connector;
|
||||
|
||||
if (!nvkms_ioctl_from_kapi(device->pKmsOpen,
|
||||
NVKMS_IOCTL_QUERY_CONNECTOR_DYNAMIC_DATA,
|
||||
¶msDynamicConnector,
|
||||
sizeof(paramsDynamicConnector))) {
|
||||
|
||||
nvKmsKapiLogDeviceDebug(
|
||||
device,
|
||||
"Failed to query dynamic data of connector 0x%08x",
|
||||
connector);
|
||||
status = NV_FALSE;
|
||||
|
||||
goto done;
|
||||
}
|
||||
|
||||
timeout = nvkms_get_usec() - startTime >
|
||||
NVKMS_DP_DETECT_COMPLETE_TIMEOUT_USEC;
|
||||
|
||||
if (!paramsDynamicConnector.reply.detectComplete && !timeout) {
|
||||
nvkms_usleep(NVKMS_DP_DETECT_COMPLETE_POLL_INTERVAL_USEC);
|
||||
}
|
||||
} while (!paramsDynamicConnector.reply.detectComplete && !timeout);
|
||||
|
||||
if (!paramsDynamicConnector.reply.detectComplete) {
|
||||
nvKmsKapiLogDeviceDebug(device, "Timed out waiting for DisplayPort"
|
||||
" device detection to complete.");
|
||||
status = NV_FALSE;
|
||||
}
|
||||
|
||||
info->dynamicDpyIdList = paramsDynamicConnector.reply.dynamicDpyIdList;
|
||||
|
||||
done:
|
||||
|
||||
return status;
|
||||
@@ -1253,6 +1296,7 @@ static NvBool GetStaticDisplayInfo
|
||||
|
||||
info->internal = paramsDpyStatic.reply.mobileInternal;
|
||||
info->headMask = paramsDpyStatic.reply.headMask;
|
||||
info->isDpMST = paramsDpyStatic.reply.isDpMST;
|
||||
done:
|
||||
|
||||
return status;
|
||||
@@ -2613,6 +2657,14 @@ static NvBool NvKmsKapiOverlayLayerConfigToKms(
|
||||
layerConfig->minPresentInterval;
|
||||
}
|
||||
|
||||
if (layerRequestedConfig->flags.cscChanged || bFromKmsSetMode) {
|
||||
params->layer[layer].csc.specified = NV_TRUE;
|
||||
params->layer[layer].csc.useMain = layerConfig->cscUseMain;
|
||||
if (!layerConfig->cscUseMain) {
|
||||
params->layer[layer].csc.matrix = layerConfig->csc;
|
||||
}
|
||||
}
|
||||
|
||||
params->layer[layer].sizeIn.val.width = layerConfig->srcWidth;
|
||||
params->layer[layer].sizeIn.val.height = layerConfig->srcHeight;
|
||||
params->layer[layer].sizeIn.specified = TRUE;
|
||||
@@ -2731,6 +2783,16 @@ static NvBool NvKmsKapiPrimaryLayerConfigToKms(
|
||||
changed = TRUE;
|
||||
}
|
||||
|
||||
if (layerRequestedConfig->flags.cscChanged || bFromKmsSetMode) {
|
||||
nvAssert(!layerConfig->cscUseMain);
|
||||
|
||||
params->layer[NVKMS_MAIN_LAYER].csc.specified = NV_TRUE;
|
||||
params->layer[NVKMS_MAIN_LAYER].csc.useMain = FALSE;
|
||||
params->layer[NVKMS_MAIN_LAYER].csc.matrix = layerConfig->csc;
|
||||
|
||||
changed = TRUE;
|
||||
}
|
||||
|
||||
params->layer[NVKMS_MAIN_LAYER].colorSpace.val = layerConfig->inputColorSpace;
|
||||
params->layer[NVKMS_MAIN_LAYER].colorSpace.specified = TRUE;
|
||||
|
||||
@@ -2977,7 +3039,6 @@ static NvBool KmsSetMode(
|
||||
status = nvkms_ioctl_from_kapi_try_pmlock(device->pKmsOpen,
|
||||
NVKMS_IOCTL_SET_MODE,
|
||||
params, sizeof(*params));
|
||||
|
||||
if (!status) {
|
||||
nvKmsKapiLogDeviceDebug(
|
||||
device,
|
||||
@@ -3130,6 +3191,12 @@ static NvBool KmsFlip(
|
||||
flipParams->colorimetry.val = headModeSetConfig->colorimetry;
|
||||
}
|
||||
|
||||
flipParams->outputcolorrange.specified =
|
||||
headRequestedConfig->flags.colorrangeChanged;
|
||||
if (flipParams->outputcolorrange.specified) {
|
||||
flipParams->outputcolorrange.val = headModeSetConfig->outputColorRange;
|
||||
}
|
||||
|
||||
if (headModeSetConfig->vrrEnabled) {
|
||||
params->request.allowVrr = NV_TRUE;
|
||||
}
|
||||
@@ -3227,8 +3294,7 @@ static NvBool ApplyModeSetConfig(
|
||||
bRequiredModeset =
|
||||
headRequestedConfig->flags.activeChanged ||
|
||||
headRequestedConfig->flags.displaysChanged ||
|
||||
headRequestedConfig->flags.modeChanged ||
|
||||
headRequestedConfig->flags.colorrangeChanged;
|
||||
headRequestedConfig->flags.modeChanged;
|
||||
|
||||
/*
|
||||
* NVKMS flip ioctl could not validate flip configuration for an
|
||||
@@ -3294,6 +3360,20 @@ void nvKmsKapiHandleEventQueueChange
|
||||
nvDpyIdToNvU32(kmsEventParams.
|
||||
reply.event.u.dpyChanged.dpyId);
|
||||
break;
|
||||
case NVKMS_EVENT_TYPE_DPY_CP_CHANGED:
|
||||
kapiEvent.u.displayCpChanged.display =
|
||||
nvDpyIdToNvU32(kmsEventParams.
|
||||
reply.event.u.dpyCpChanged.dpyId);
|
||||
kapiEvent.u.displayCpChanged.cp =
|
||||
kmsEventParams.reply.event.u.dpyCpChanged.cp;
|
||||
break;
|
||||
case NVKMS_EVENT_TYPE_DPY_CP_TOPOLOGY_CHANGED:
|
||||
kapiEvent.u.displayCpTopologyChanged.display =
|
||||
nvDpyIdToNvU32(kmsEventParams.
|
||||
reply.event.u.dpyCpTopologyChanged.dpyId);
|
||||
kapiEvent.u.displayCpTopologyChanged.topology =
|
||||
kmsEventParams.reply.event.u.dpyCpTopologyChanged.topology;
|
||||
break;
|
||||
case NVKMS_EVENT_TYPE_DYNAMIC_DPY_CONNECTED:
|
||||
kapiEvent.u.dynamicDisplayConnected.display =
|
||||
nvDpyIdToNvU32(kmsEventParams.
|
||||
|
||||
@@ -552,6 +552,19 @@ void ConnectorEventSink::notifyCableOkStateChange(DisplayPort::Device *dev,
|
||||
void ConnectorEventSink::notifyHDCPCapDone(DisplayPort::Device *dev,
|
||||
bool hdcpCap)
|
||||
{
|
||||
NVDpyEvoPtr pDpyEvo = NULL;
|
||||
pDpyEvo = FindDpyByDevice(pConnectorEvo, dev);
|
||||
if (pDpyEvo)
|
||||
{
|
||||
if (hdcpCap)
|
||||
{
|
||||
nvSendDpyEventEvo(pDpyEvo, NVKMS_EVENT_TYPE_DPY_CP_CHANGED);
|
||||
}
|
||||
else
|
||||
{
|
||||
nvSendDpyClearEventEvo(pDpyEvo, NVKMS_EVENT_TYPE_DPY_CP_CHANGED);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void ConnectorEventSink::notifyMCCSEvent(DisplayPort::Device *dev)
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2008-2019 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2008-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -205,3 +205,32 @@ nvHandleDPIRQEventDeferredWork(void *dataPtr, NvU32 dataU32)
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void
|
||||
nvHandleCpEventDeferredWork(void *dataPtr, NvU32 dataU32)
|
||||
{
|
||||
NVDispEvoPtr pDispEvo = dataPtr;
|
||||
NVDpyIdList dpyIdList = nvEmptyDpyIdList();
|
||||
NVDpyEvoPtr pDpyEvo;
|
||||
NvU32 displayId = dataU32 & 0x00FFFFFFU;
|
||||
NvU32 hdcpStatusChangeNotif = ((dataU32 & 0xFF000000) >> 24);
|
||||
|
||||
dpyIdList = nvAddDpyIdToDpyIdList(nvNvU32ToDpyId(displayId), dpyIdList);
|
||||
FOR_ALL_EVO_DPYS(pDpyEvo, dpyIdList, pDispEvo) {
|
||||
if (hdcpStatusChangeNotif == hdcpStatusChangeNotif_EncEnabled) {
|
||||
nvSendDpyEventEvo(pDpyEvo, NVKMS_EVENT_TYPE_DPY_CP_CHANGED);
|
||||
}
|
||||
else if (hdcpStatusChangeNotif == hdcpStatusChangeNotif_KsvOk ||
|
||||
hdcpStatusChangeNotif == hdcpStatusChangeNotif_RepComplete) {
|
||||
nvSendDpyEventEvo(pDpyEvo, NVKMS_EVENT_TYPE_DPY_CP_TOPOLOGY_CHANGED);
|
||||
}
|
||||
else if (hdcpStatusChangeNotif == hdcpStatusChangeNotif_HdcpDisabled ||
|
||||
hdcpStatusChangeNotif == hdcpStatusChangeNotif_HdcpInactive ||
|
||||
hdcpStatusChangeNotif == hdcpStatusChangeNotif_LinkFailed ||
|
||||
hdcpStatusChangeNotif == hdcpStatusChangeNotif_HdcpRestart) {
|
||||
nvSendDpyClearEventEvo(pDpyEvo, NVKMS_EVENT_TYPE_DPY_CP_CHANGED);
|
||||
nvSendDpyClearEventEvo(pDpyEvo, NVKMS_EVENT_TYPE_DPY_CP_TOPOLOGY_CHANGED);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2010-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2010-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -1336,7 +1336,8 @@ static void ConfigureCsc1C5(NVDevEvoPtr pDevEvo,
|
||||
matrix = LMSToRec2020RGB;
|
||||
} else if (pHeadState->colorimetry == NVKMS_OUTPUT_COLORIMETRY_BT601) {
|
||||
matrix = LMSToRec601RGB;
|
||||
} else if (pHeadState->colorimetry == NVKMS_OUTPUT_COLORIMETRY_BT709) {
|
||||
} else {
|
||||
// For unsupported or default output color spaces also , use 709 matrix
|
||||
matrix = LMSToRec709RGB;
|
||||
}
|
||||
|
||||
@@ -1486,9 +1487,15 @@ static const NvU32* EvoGetFMTMatrixC5(
|
||||
} else {
|
||||
retValue = FMTMatrix[FMT_COEFF_TYPE_REC601_YUV_12BPC_LTD_TO_RGB_16BPC_FULL];
|
||||
}
|
||||
} else {
|
||||
// Unsupported bit depth, fail silently by defaulting to identity.
|
||||
retValue = FMTMatrix[FMT_COEFF_TYPE_IDENTITY];
|
||||
}
|
||||
break;
|
||||
case NVKMS_INPUT_COLORSPACE_BT709:
|
||||
case NVKMS_INPUT_COLORSPACE_NONE:
|
||||
default:
|
||||
// Unsupported or if input color space is not set, use 709 FMT matrix.
|
||||
if (pFormatInfo->yuv.depthPerComponent == 8) {
|
||||
if (specifiedFull) {
|
||||
retValue = FMTMatrix[FMT_COEFF_TYPE_REC709_YUV_8BPC_FULL_TO_RGB_16BPC_FULL];
|
||||
@@ -1507,6 +1514,9 @@ static const NvU32* EvoGetFMTMatrixC5(
|
||||
} else {
|
||||
retValue = FMTMatrix[FMT_COEFF_TYPE_REC709_YUV_12BPC_LTD_TO_RGB_16BPC_FULL];
|
||||
}
|
||||
} else {
|
||||
// Unsupported bit depth, fail silently by defaulting to identity.
|
||||
retValue = FMTMatrix[FMT_COEFF_TYPE_IDENTITY];
|
||||
}
|
||||
break;
|
||||
case NVKMS_INPUT_COLORSPACE_BT2100_PQ:
|
||||
@@ -1528,11 +1538,11 @@ static const NvU32* EvoGetFMTMatrixC5(
|
||||
} else {
|
||||
retValue = FMTMatrix[FMT_COEFF_TYPE_REC2020_YUV_12BPC_LTD_TO_RGB_16BPC_FULL];
|
||||
}
|
||||
} else {
|
||||
// Unsupported bit depth, fail silently by defaulting to identity.
|
||||
retValue = FMTMatrix[FMT_COEFF_TYPE_IDENTITY];
|
||||
}
|
||||
break;
|
||||
default:
|
||||
// Unsupported bit depth, fail silently by defaulting to identity.
|
||||
retValue = FMTMatrix[FMT_COEFF_TYPE_IDENTITY];
|
||||
}
|
||||
} else {
|
||||
// All inputs with RGB colorspace receive an identity FMT.
|
||||
|
||||
@@ -132,6 +132,11 @@ static NvBool UpdateProposedFlipStateOneApiHead(
|
||||
pProposedApiHead->hdr.colorimetry = pParams->colorimetry.val;
|
||||
}
|
||||
|
||||
if (pParams->outputcolorrange.specified) {
|
||||
pProposedApiHead->dirty.hdr = TRUE;
|
||||
pProposedApiHead->hdr.outputColorRange = pParams->outputcolorrange.val;
|
||||
}
|
||||
|
||||
if (pParams->tf.specified) {
|
||||
const NVDpyEvoRec *pDpyEvo =
|
||||
nvGetOneArbitraryDpyEvo(pApiHeadState->activeDpys, pDispEvo);
|
||||
@@ -360,6 +365,7 @@ static void InitNvKmsFlipWorkArea(const NVDevEvoRec *pDevEvo,
|
||||
|
||||
pProposedApiHead->hdr.tf = pApiHeadState->tf;
|
||||
pProposedApiHead->hdr.colorimetry = pApiHeadState->colorimetry;
|
||||
pProposedApiHead->hdr.outputColorRange = pApiHeadState->outputColorRange;
|
||||
pProposedApiHead->hdr.colorSpace =
|
||||
pApiHeadState->attributes.colorSpace;
|
||||
pProposedApiHead->hdr.colorBpc =
|
||||
@@ -407,7 +413,7 @@ static void FlipEvoOneApiHead(NVDispEvoRec *pDispEvo,
|
||||
head,
|
||||
pProposedApiHead->hdr.colorimetry,
|
||||
pProposedApiHead->hdr.colorSpace,
|
||||
pProposedApiHead->hdr.colorRange,
|
||||
pProposedApiHead->hdr.outputColorRange,
|
||||
pUpdateState);
|
||||
}
|
||||
}
|
||||
@@ -430,6 +436,8 @@ static void FlipEvoOneApiHead(NVDispEvoRec *pDispEvo,
|
||||
|
||||
pApiHeadState->colorimetry = pProposedApiHead->hdr.colorimetry;
|
||||
|
||||
pApiHeadState->outputColorRange = pProposedApiHead->hdr.outputColorRange;
|
||||
|
||||
nvUpdateInfoFrames(pDpyEvo);
|
||||
}
|
||||
|
||||
|
||||
@@ -985,6 +985,11 @@ NvBool nvUpdateFlipEvoHwState(
|
||||
pFlipState->colorimetry = pParams->colorimetry.val;
|
||||
}
|
||||
|
||||
if (pParams->outputcolorrange.specified) {
|
||||
pFlipState->dirty.outputColorRange = TRUE;
|
||||
pFlipState->outputColorRange = pParams->outputcolorrange.val;
|
||||
}
|
||||
|
||||
for (layer = 0; layer < pDevEvo->head[head].numLayers; layer++) {
|
||||
if (layer == NVKMS_MAIN_LAYER) {
|
||||
if (!UpdateMainLayerFlipEvoHwState(pOpenDev, pDevEvo, sd, head,
|
||||
@@ -1581,6 +1586,11 @@ static void UpdateHDR(NVDevEvoPtr pDevEvo,
|
||||
dirty = TRUE;
|
||||
}
|
||||
|
||||
if (pFlipState->dirty.outputColorRange) {
|
||||
pHeadState->outputColorRange = pFlipState->outputColorRange;
|
||||
dirty = TRUE;
|
||||
}
|
||||
|
||||
if (dirty) {
|
||||
// Update OCSC / OLUT
|
||||
nvEvoSetLUTContextDma(pDispEvo, head, updateState);
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2013-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2013-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -1352,6 +1352,99 @@ NvBool nvWriteDPCDReg(NVConnectorEvoPtr pConnectorEvo,
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
void nvGetContentProtectionState(NVConnectorEvoPtr pConnectorEvo, enum NvKmsContentProtection *cp)
|
||||
{
|
||||
NVDevEvoPtr pDevEvo = pConnectorEvo->pDispEvo->pDevEvo;
|
||||
NvU32 subDeviceIndex = pConnectorEvo->pDispEvo->displayOwner;
|
||||
NvU32 displayId = nvDpyIdToNvU32(pConnectorEvo->displayId);
|
||||
NV0073_CTRL_SPECIFIC_GET_HDCP_STATE_PARAMS params = {0};
|
||||
NvU32 ret = NVOS_STATUS_SUCCESS;
|
||||
NvBool hdcpAuthOn, hdcp1xCapable, hdcp2xCapable, hdcp2xType1;
|
||||
|
||||
params.subDeviceInstance = subDeviceIndex;
|
||||
params.displayId = displayId;
|
||||
ret = nvRmApiControl(nvEvoGlobal.clientHandle,
|
||||
pDevEvo->displayCommonHandle,
|
||||
NV0073_CTRL_CMD_SPECIFIC_GET_HDCP_STATE,
|
||||
¶ms, sizeof params);
|
||||
if (ret != NVOS_STATUS_SUCCESS)
|
||||
{
|
||||
nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, "CTRL CMD GET_HDCP_STATE failed");
|
||||
*cp = NVKMS_CP_OFF;
|
||||
return;
|
||||
}
|
||||
|
||||
hdcpAuthOn = FLD_TEST_DRF(0073_CTRL_SPECIFIC,
|
||||
_HDCP_STATE, _AUTHENTICATED, _YES, params.flags) ? TRUE : FALSE;
|
||||
hdcp1xCapable = FLD_TEST_DRF(0073_CTRL_SPECIFIC,
|
||||
_HDCP_STATE, _RECEIVER_CAPABLE, _YES, params.flags) ? TRUE : FALSE;
|
||||
hdcp2xCapable = FLD_TEST_DRF(0073_CTRL_SPECIFIC,
|
||||
_HDCP_STATE, _HDCP22_RECEIVER_CAPABLE, _YES, params.flags) ? TRUE : FALSE;
|
||||
hdcp2xType1 = FLD_TEST_DRF(0073_CTRL_SPECIFIC,
|
||||
_HDCP_STATE, _HDCP22_TYPE1, _YES, params.flags) ? TRUE : FALSE;
|
||||
|
||||
if (hdcpAuthOn && hdcp2xCapable && hdcp2xType1) {
|
||||
*cp = NVKMS_CP_HDCP2X_TYPE1_ON;
|
||||
} else if (hdcpAuthOn && hdcp2xCapable) {
|
||||
*cp = NVKMS_CP_HDCP2X_TYPE0_ON;
|
||||
} else if (hdcpAuthOn && hdcp1xCapable) {
|
||||
*cp = NVKMS_CP_HDCP1X_ON;
|
||||
} else {
|
||||
*cp = NVKMS_CP_OFF;
|
||||
}
|
||||
}
|
||||
|
||||
void nvGetContentProtectionTopology(NVConnectorEvoPtr pConnectorEvo,
|
||||
struct NvKmsHdcpTopology *topology)
|
||||
{
|
||||
NVDevEvoPtr pDevEvo = pConnectorEvo->pDispEvo->pDevEvo;
|
||||
NvU32 subDeviceIndex = pConnectorEvo->pDispEvo->displayOwner;
|
||||
NvU32 displayId = nvDpyIdToNvU32(pConnectorEvo->displayId);
|
||||
NV0073_CTRL_SPECIFIC_HDCP_CTRL_PARAMS *params = nvCalloc(1, sizeof(NV0073_CTRL_SPECIFIC_HDCP_CTRL_PARAMS));
|
||||
NvU32 ret = NVOS_STATUS_SUCCESS;
|
||||
|
||||
if (params == NULL) {
|
||||
nvEvoLogDev(pDevEvo, EVO_LOG_ERROR,
|
||||
"Failed to allocate memory for NV0073_CTRL_SPECIFIC_HDCP_CTRL_PARAMS");
|
||||
goto exit1;
|
||||
}
|
||||
nvkms_memset(topology, 0, sizeof(*topology));
|
||||
params->subDeviceInstance = subDeviceIndex;
|
||||
params->displayId = displayId;
|
||||
params->cmd = DRF_DEF(0073_CTRL_SPECIFIC, _HDCP_CTRL, _CMD, _READ_TOPOLOGY);
|
||||
ret = nvRmApiControl(nvEvoGlobal.clientHandle,
|
||||
pDevEvo->displayCommonHandle,
|
||||
NV0073_CTRL_CMD_SPECIFIC_HDCP_CTRL,
|
||||
params, sizeof(*params));
|
||||
if (ret != NVOS_STATUS_SUCCESS)
|
||||
{
|
||||
nvEvoLogDev(pDevEvo, EVO_LOG_ERROR, "CTRL CMD READ_TOPOLOGY failed");
|
||||
goto exit2;
|
||||
}
|
||||
|
||||
topology->isHdcpCapable = params->isHdcpCapable;
|
||||
topology->isHdcpAuthOn = params->isHdcpAuthOn;
|
||||
topology->isHdcpRp = params->isHdcpRp;
|
||||
topology->isHdcp2X = params->isHdcp2X;
|
||||
topology->maxCascadeExceeded = params->bMaxCascadeExceeded;
|
||||
topology->maxDeviceExceeded = params->bMaxDeviceExceeded;
|
||||
topology->isHdcp1DevDownstream = params->bHdcp1DevDownstream;
|
||||
topology->isHdcp2LegacyDevDownstream = params->bHdcp2LegacyDevDownstream;
|
||||
topology->cascadeDepth = params->cascadeDepth;
|
||||
topology->linkCount = params->linkCount;
|
||||
nvkms_memcpy(topology->bksv,
|
||||
params->bKsv,
|
||||
params->linkCount * HDCP_TOPOLOGY_KSV_SIZE);
|
||||
topology->numOfBksv = params->numBksvs;
|
||||
nvkms_memcpy(topology->bksvList,
|
||||
params->bKsvList,
|
||||
params->numBksvs * HDCP_TOPOLOGY_KSV_SIZE);
|
||||
exit2:
|
||||
nvFree(params);
|
||||
exit1:
|
||||
return;
|
||||
}
|
||||
|
||||
static NvBool ReadDPSerializerCaps(NVConnectorEvoPtr pConnectorEvo)
|
||||
{
|
||||
NVDpyIdList oneDpyIdList =
|
||||
@@ -1489,7 +1582,7 @@ static void ReceiveHotplugEvent(void *arg, void *pEventDataVoid, NvU32 hEvent,
|
||||
nvHandleHotplugEventDeferredWork, /* callback */
|
||||
arg, /* argument (this is a ref_ptr to a pDispEvo) */
|
||||
0, /* dataU32 */
|
||||
0);
|
||||
100000 /*sleep 100 ms */);
|
||||
}
|
||||
|
||||
static void ReceiveDPIRQEvent(void *arg, void *pEventDataVoid, NvU32 hEvent,
|
||||
@@ -1505,6 +1598,19 @@ static void ReceiveDPIRQEvent(void *arg, void *pEventDataVoid, NvU32 hEvent,
|
||||
0);
|
||||
}
|
||||
|
||||
static void ReceiveCpEvent(void *arg, void *pEventDataVoid, NvU32 hEvent,
|
||||
NvU32 Data, NV_STATUS Status)
|
||||
{
|
||||
Nv2080HdcpStatusChangeNotification *pEventData = (Nv2080HdcpStatusChangeNotification*)(pEventDataVoid);
|
||||
NvU32 eventData = ((pEventData->hdcpStatusChangeNotif & 0xFFU) << 24) |
|
||||
(pEventData->displayId & 0x00FFFFFFU);
|
||||
(void) nvkms_alloc_timer_with_ref_ptr(
|
||||
nvHandleCpEventDeferredWork, /* callback */
|
||||
arg, /* argument (this is a ref_ptr to a pDispEvo) */
|
||||
eventData, /* dataU32 */
|
||||
0);
|
||||
}
|
||||
|
||||
NvBool nvRmRegisterCallback(const NVDevEvoRec *pDevEvo,
|
||||
NVOS10_EVENT_KERNEL_CALLBACK_EX *cb,
|
||||
struct nvkms_ref_ptr *ref_ptr,
|
||||
@@ -1715,6 +1821,40 @@ enum NvKmsAllocDeviceStatus nvRmAllocDisplays(NVDevEvoPtr pDevEvo)
|
||||
}
|
||||
}
|
||||
|
||||
// Allocate a handler for the Content Protection event, which is signaled
|
||||
// when there is a change in HDCP status
|
||||
FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) {
|
||||
NV2080_CTRL_EVENT_SET_NOTIFICATION_PARAMS setEventParams = { };
|
||||
NvU32 subDevice, ret;
|
||||
|
||||
subDevice = pDevEvo->pSubDevices[pDispEvo->displayOwner]->handle;
|
||||
|
||||
pDispEvo->cpEventHandle =
|
||||
nvGenerateUnixRmHandle(&pDevEvo->handleAllocator);
|
||||
|
||||
if (!RegisterDispCallback(&pDispEvo->rmCpCallback, pDispEvo,
|
||||
pDispEvo->cpEventHandle, ReceiveCpEvent,
|
||||
NV2080_NOTIFIERS_HDCP_STATUS_CHANGE)) {
|
||||
nvEvoLogDev(pDevEvo, EVO_LOG_WARN,
|
||||
"Failed to register Content Protection event");
|
||||
}
|
||||
|
||||
// Enable HDCP Status Change notifications from this subdevice.
|
||||
setEventParams.event = NV2080_NOTIFIERS_HDCP_STATUS_CHANGE;
|
||||
setEventParams.action = NV2080_CTRL_EVENT_SET_NOTIFICATION_ACTION_REPEAT;
|
||||
if ((ret = nvRmApiControl(nvEvoGlobal.clientHandle,
|
||||
subDevice,
|
||||
NV2080_CTRL_CMD_EVENT_SET_NOTIFICATION,
|
||||
&setEventParams,
|
||||
sizeof(setEventParams)))
|
||||
!= NVOS_STATUS_SUCCESS) {
|
||||
nvEvoLogDev(pDevEvo, EVO_LOG_WARN,
|
||||
"Failed to register Content Protection event "
|
||||
"handler: 0x%x\n", ret);
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
FOR_ALL_EVO_DISPLAYS(pDispEvo, sd, pDevEvo) {
|
||||
ProbeBootDisplays(pDispEvo);
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2015-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -2649,7 +2649,7 @@ static NvBool RegisterSurface(struct NvKmsPerOpen *pOpen,
|
||||
|
||||
nvEvoRegisterSurface(pOpenDev->pDevEvo, pOpenDev, pParams,
|
||||
NvHsMapPermissionsReadOnly);
|
||||
return TRUE;
|
||||
return pParams->reply.surfaceHandle != 0;
|
||||
}
|
||||
|
||||
|
||||
@@ -5119,11 +5119,16 @@ static void ConsoleRestoreTimerFired(void *dataPtr, NvU32 dataU32)
|
||||
* NVKMS_EVENT_TYPE_DPY_ATTRIBUTE_CHANGED.
|
||||
* \param[in] NvS64 The NvKmsDpyAttribute value; only used for
|
||||
* NVKMS_EVENT_TYPE_DPY_ATTRIBUTE_CHANGED.
|
||||
* \param[in] NvBool Only valid for NVKMS_EVENT_TYPE_DPY_CP_CHANGED
|
||||
* and NVKMS_EVENT_TYPE_DPY_CP_TOPOLOGY_CHANGED.
|
||||
* When set to NV_TRUE cp is considerd disabled
|
||||
* and topology will be cleared.
|
||||
*/
|
||||
static void SendDpyEventEvo(const NVDpyEvoRec *pDpyEvo,
|
||||
const NvU32 eventType,
|
||||
const enum NvKmsDpyAttribute attribute,
|
||||
const NvS64 value)
|
||||
const NvS64 value,
|
||||
const NvBool clear)
|
||||
{
|
||||
struct NvKmsPerOpen *pOpen;
|
||||
const NVDispEvoRec *pDispEvo = pDpyEvo->pDispEvo;
|
||||
@@ -5153,6 +5158,29 @@ static void SendDpyEventEvo(const NVDpyEvoRec *pDpyEvo,
|
||||
event.u.dpyChanged.dpyId = pDpyEvo->id;
|
||||
break;
|
||||
|
||||
case NVKMS_EVENT_TYPE_DPY_CP_CHANGED:
|
||||
event.u.dpyCpChanged.deviceHandle = deviceHandle;
|
||||
event.u.dpyCpChanged.dispHandle = dispHandle;
|
||||
event.u.dpyCpChanged.dpyId = pDpyEvo->id;
|
||||
if (clear) {
|
||||
event.u.dpyCpChanged.cp = NVKMS_CP_OFF;
|
||||
} else {
|
||||
nvGetContentProtectionState(pDpyEvo->pConnectorEvo, &(event.u.dpyCpChanged.cp));
|
||||
}
|
||||
break;
|
||||
|
||||
case NVKMS_EVENT_TYPE_DPY_CP_TOPOLOGY_CHANGED:
|
||||
event.u.dpyCpTopologyChanged.deviceHandle = deviceHandle;
|
||||
event.u.dpyCpTopologyChanged.dispHandle = dispHandle;
|
||||
event.u.dpyCpTopologyChanged.dpyId = pDpyEvo->id;
|
||||
event.u.dpyCpTopologyChanged.topology = &(pDpyEvo->pConnectorEvo->cpTopology);
|
||||
if (clear) {
|
||||
nvkms_memset(&(pDpyEvo->pConnectorEvo->cpTopology), 0, sizeof(struct NvKmsHdcpTopology ));
|
||||
} else {
|
||||
nvGetContentProtectionTopology(pDpyEvo->pConnectorEvo, &(pDpyEvo->pConnectorEvo->cpTopology));
|
||||
}
|
||||
break;
|
||||
|
||||
case NVKMS_EVENT_TYPE_DYNAMIC_DPY_CONNECTED:
|
||||
event.u.dynamicDpyConnected.deviceHandle = deviceHandle;
|
||||
event.u.dynamicDpyConnected.dispHandle = dispHandle;
|
||||
@@ -5197,7 +5225,17 @@ void nvSendDpyEventEvo(const NVDpyEvoRec *pDpyEvo, const NvU32 eventType)
|
||||
nvAssert(eventType != NVKMS_EVENT_TYPE_DPY_ATTRIBUTE_CHANGED);
|
||||
SendDpyEventEvo(pDpyEvo, eventType,
|
||||
0 /* attribute (unused) */,
|
||||
0 /* value (unused) */ );
|
||||
0 /* value (unused) */,
|
||||
NV_FALSE);
|
||||
}
|
||||
|
||||
void nvSendDpyClearEventEvo(const NVDpyEvoRec *pDpyEvo, const NvU32 eventType)
|
||||
{
|
||||
nvAssert(eventType != NVKMS_EVENT_TYPE_DPY_ATTRIBUTE_CHANGED);
|
||||
SendDpyEventEvo(pDpyEvo, eventType,
|
||||
0 /* attribute (unused) */,
|
||||
0 /* value (unused) */,
|
||||
NV_TRUE);
|
||||
}
|
||||
|
||||
void nvSendDpyAttributeChangedEventEvo(const NVDpyEvoRec *pDpyEvo,
|
||||
@@ -5206,7 +5244,7 @@ void nvSendDpyAttributeChangedEventEvo(const NVDpyEvoRec *pDpyEvo,
|
||||
{
|
||||
SendDpyEventEvo(pDpyEvo,
|
||||
NVKMS_EVENT_TYPE_DPY_ATTRIBUTE_CHANGED,
|
||||
attribute, value);
|
||||
attribute, value, NV_FALSE);
|
||||
}
|
||||
|
||||
void nvSendFrameLockAttributeChangedEventEvo(
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2008-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2008-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2008-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2008-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2008-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2008-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
|
||||
@@ -1,4 +1,4 @@
|
||||
NVIDIA_VERSION = 540.4.0
|
||||
NVIDIA_VERSION = 540.5.0
|
||||
|
||||
# This file.
|
||||
VERSION_MK_FILE := $(lastword $(MAKEFILE_LIST))
|
||||
|
||||
Reference in New Issue
Block a user