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git://nv-tegra.nvidia.com/tegra/kernel-src/nv-kernel-display-driver.git
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2 Commits
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jetson_38.
| Author | SHA1 | Date | |
|---|---|---|---|
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deeba4ac74 | ||
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d633398383 |
114
commitFile.txt
114
commitFile.txt
@@ -9,7 +9,7 @@ ec5f1eb408e0b650158e0310fb1ddd8e9b323a6f - CONTRIBUTING.md
|
||||
af3ee56442f16029cb9b13537477c384226b22fc - CODE_OF_CONDUCT.md
|
||||
07bd07999f296d935386a8edf719d0e296f63227 - kernel-open/Kbuild
|
||||
45b68e3eacda04dcadce48a8238574302a71a3ca - kernel-open/Makefile
|
||||
70bd025d834add7e40a0ee69e48612a289df1f07 - kernel-open/conftest.sh
|
||||
99f4563141af1278f13cb23a6e6c24d21d583d7b - kernel-open/conftest.sh
|
||||
0b1508742a1c5a04b6c3a4be1b48b506f4180848 - kernel-open/dkms.conf
|
||||
19a5da412ce1557b721b8550a4a80196f6162ba6 - kernel-open/common/inc/os_dsi_panel_props.h
|
||||
4750735d6f3b334499c81d499a06a654a052713d - kernel-open/common/inc/nv-caps.h
|
||||
@@ -17,11 +17,11 @@ af3ee56442f16029cb9b13537477c384226b22fc - CODE_OF_CONDUCT.md
|
||||
60ef64c0f15526ae2d786e5cec07f28570f0663b - kernel-open/common/inc/conftest.h
|
||||
880e45b68b19fdb91ac94991f0e6d7fc3b406b1f - kernel-open/common/inc/nv-pci-types.h
|
||||
6d2f660ef0942edf664874f260266ec81cd0ff08 - kernel-open/common/inc/nvtypes.h
|
||||
d580300f41118dacc5569fffa9f47e78c5883141 - kernel-open/common/inc/nv-modeset-interface.h
|
||||
c45b2faf17ca2a205c56daa11e3cb9d864be2238 - kernel-open/common/inc/nv-modeset-interface.h
|
||||
5bc7a748c7d3dfa6559ca4f9fe6199e17098ec8f - kernel-open/common/inc/nv-lock.h
|
||||
b249abc0a7d0c9889008e98cb2f8515a9d310b85 - kernel-open/common/inc/nvgputypes.h
|
||||
e4a4f57abb8769d204468b2f5000c81f5ea7c92f - kernel-open/common/inc/nv-procfs.h
|
||||
3906bee59dc2433131bf58d12bdbeb7fedb8465f - kernel-open/common/inc/nv.h
|
||||
8b19b93e958aca626899f035334a4c96f8776eb6 - kernel-open/common/inc/nv.h
|
||||
ede1f77acb43e28391bceac058e00a7a8d799b0d - kernel-open/common/inc/nvmisc.h
|
||||
ae374d3e438f8d3b60df8c4602618c58564b73f9 - kernel-open/common/inc/rm-gpu-ops.h
|
||||
3f7b20e27e6576ee1f2f0557d269697a0b8af7ec - kernel-open/common/inc/nv-firmware-registry.h
|
||||
@@ -35,28 +35,28 @@ a3d1e51c0f4217f1dc4cb0c48aa0eafd054d4e5e - kernel-open/common/inc/nv-procfs-util
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||||
81592e5c17bebad04cd11d73672c859baa070329 - kernel-open/common/inc/nv-chardev-numbers.h
|
||||
61cf8f3fd32142dc402f6802b5d4c9af6c875c35 - kernel-open/common/inc/nv-firmware.h
|
||||
d5253e7e4abd3ad8d72375260aa80037adcd8973 - kernel-open/common/inc/nv_dpy_id.h
|
||||
f4f6ef99266975becbd50ee25030e61dedbeba6d - kernel-open/common/inc/nv-platform.h
|
||||
61a9589e4a8ec122e5a6c2258658d493ee747897 - kernel-open/common/inc/nv-platform.h
|
||||
b986bc6591ba17a74ad81ec4c93347564c6d5165 - kernel-open/common/inc/nvkms-format.h
|
||||
4f487eccd762f3ca645a685d5c333ff569e7987c - kernel-open/common/inc/nv-kthread-q-os.h
|
||||
4015c4557ea0790a2bdf5695832c89e31d75aee9 - kernel-open/common/inc/nvlimits.h
|
||||
143051f69a53db0e7c5d2f846a9c14d666e264b4 - kernel-open/common/inc/nv-kref.h
|
||||
56f432032bef4683c2801f46bec5065923475fb1 - kernel-open/common/inc/nv-kthread-q.h
|
||||
b4c5d759f035b540648117b1bff6b1701476a398 - kernel-open/common/inc/nvCpuUuid.h
|
||||
5d7fdbf9c5edea6088b471e27a9ce87a500d8f7e - kernel-open/common/inc/nv-linux.h
|
||||
67a9707c568e167bae4404c7785ed614babb7b82 - kernel-open/common/inc/nv-linux.h
|
||||
7c7888550b12eeb98128ea9ac771b897327f538e - kernel-open/common/inc/nv-hypervisor.h
|
||||
f9cb3701681994ff6f32833892d900b0da2b89f6 - kernel-open/common/inc/nv-pgprot.h
|
||||
b8700a911ac85770bf25d70b9692308af63966bd - kernel-open/common/inc/nvstatuscodes.h
|
||||
3a5f4f105672921b857fec7f2b577d9d525afe37 - kernel-open/common/inc/nv-timer.h
|
||||
5cd0b3f9c7f544e9064efc9b5ba4f297e5494315 - kernel-open/common/inc/nv-time.h
|
||||
7a78f354e0b68f03d6ab566d5b755e299456f361 - kernel-open/common/inc/os_gpio.h
|
||||
3d5aa82afa27ba6edd0ebbf500e8b07a8d1dd788 - kernel-open/common/inc/nv-proto.h
|
||||
154abd192eb950fecffcca470ee80b27f224fd79 - kernel-open/common/inc/nv-proto.h
|
||||
2eb11e523a3ecba2dcd68f3146e1e666a44256ae - kernel-open/common/inc/nv-ioctl.h
|
||||
1328058925b64e97588d670fe70466b31af7c7c1 - kernel-open/common/inc/nv-mm.h
|
||||
fba1f7a11efe4362f60cbf3ec71a9a2a3b28a9d8 - kernel-open/common/inc/nv-pci.h
|
||||
25d89847c11449b329941a26f04aec955cfaf150 - kernel-open/common/inc/nv-pci.h
|
||||
95bf694a98ba78d5a19e66463b8adda631e6ce4c - kernel-open/common/inc/nvstatus.h
|
||||
d74a8d4a9ae3d36e92b39bc7c74b27df44626b1c - kernel-open/common/inc/nv_mig_types.h
|
||||
b3258444b6a2c2399f5f00c7cac5b470c41caeaa - kernel-open/common/inc/nv-hash.h
|
||||
29309411e2bf1c2e6492a104dcb9f53705c2e9aa - kernel-open/common/inc/nvkms-kapi.h
|
||||
4c856c1324060dcb5a9e72e5e82c7a60f6324733 - kernel-open/common/inc/nvkms-kapi.h
|
||||
44cb5bc2bc87a5c3447bcb61f2ce5aef08c07fa7 - kernel-open/common/inc/nv_uvm_interface.h
|
||||
1e7eec6561b04d2d21c3515987aaa116e9401c1f - kernel-open/common/inc/nv-kernel-interface-api.h
|
||||
c54c62de441828282db9a4f5b35c2fa5c97d94f1 - kernel-open/common/inc/nvkms-api-types.h
|
||||
@@ -76,11 +76,11 @@ cda75171ca7d8bf920aab6d56ef9aadec16fd15d - kernel-open/common/inc/os/nv_memory_t
|
||||
70b67003fda6bdb8a01fa1e41c3b0e25136a856c - kernel-open/common/inc/os/nv_memory_area.h
|
||||
11b09260232a88aa1f73f109fdfab491a7b73576 - kernel-open/nvidia/nv-nano-timer.c
|
||||
dcf4427b83cce7737f2b784d410291bf7a9612dc - kernel-open/nvidia/nv-reg.h
|
||||
271c7df4c4e1933b597e5b862c7790458278d3e0 - kernel-open/nvidia/nv-imp.c
|
||||
0b8ff957fb14f20ba86f61e556d1ab15bf5acd74 - kernel-open/nvidia/nv-imp.c
|
||||
6b09b5ef8a37f78c8e82074b06b40ef593c81807 - kernel-open/nvidia/libspdm_rsa.c
|
||||
b8d361216db85fe897cbced2a9600507b7708c61 - kernel-open/nvidia/libspdm_hkdf_sha.c
|
||||
66e2bfc490fb77e0b72a8192b719d3dc74d25d59 - kernel-open/nvidia/nv-pat.c
|
||||
3abdd4528338680e0e85d2d7758cc7ba5b21ba79 - kernel-open/nvidia/nv-vm.c
|
||||
26a30f2d26c2a97a6e2ee457d97d32f48b0bf25b - kernel-open/nvidia/nv-vm.c
|
||||
b8a770cea0629c57d8b0b3d7414d7b0f043ee8cf - kernel-open/nvidia/libspdm_ecc.c
|
||||
4c183eb39251cd78d90868ec6f75ebc7a37e6644 - kernel-open/nvidia/os-usermap.c
|
||||
8c30b6230439edcbec62636cc93be512bca8637f - kernel-open/nvidia/nv-usermap.c
|
||||
@@ -92,14 +92,14 @@ ef8fd76c55625aeaa71c9b789c4cf519ef6116b2 - kernel-open/nvidia/libspdm_hkdf.c
|
||||
f16e6a33b5004566333fb8b99504a0fb95d51226 - kernel-open/nvidia/nv-gpio.c
|
||||
8ed2c3b93eeaa52342d944e794180fd5d386688a - kernel-open/nvidia/libspdm_rsa_ext.c
|
||||
2e5d18118835c19c5ca7edee9bceeae613b9d7f9 - kernel-open/nvidia/nv-procfs.c
|
||||
ef2f1033d97fa5509d75feb223af5880c0384719 - kernel-open/nvidia/nv.c
|
||||
3e820e66f556be10c0d9728d4187e43c30658736 - kernel-open/nvidia/nv.c
|
||||
65fe797fb5d4af2db67544ddb79d49ab1b7ca859 - kernel-open/nvidia/nv-dsi-parse-panel-props.c
|
||||
e3efae4ed920545062a2d06064df8be1a2a42135 - kernel-open/nvidia/nv-caps-imex.h
|
||||
8c64e75aaaa9ac6f17aae7ed62db23eb2e5b9953 - kernel-open/nvidia/nv_uvm_interface.c
|
||||
4563589496a93a2720e25807ca1be2565f03554c - kernel-open/nvidia/nv-bpmp.c
|
||||
aea97021d9aa023a357f009fcddc710f710ceb5e - kernel-open/nvidia/libspdm_x509.c
|
||||
f29e5bc1c7bd2c670780cdbb7275900a69f4d205 - kernel-open/nvidia/internal_crypt_lib.h
|
||||
22418fb7ae38c7f153af94edf2f5bd1cbcacb889 - kernel-open/nvidia/nv-modeset-interface.c
|
||||
13dc24fb41516c777328d4db64fa39a9e2c40191 - kernel-open/nvidia/nv-modeset-interface.c
|
||||
6ae527b69eebb44224b05e8cb3546757532d8a16 - kernel-open/nvidia/nv-dma.c
|
||||
fe204e3820d206b5b0c34a51084f39b97310305a - kernel-open/nvidia/nv-ipc-soc.c
|
||||
60d6ff5becc0ddbcf4b489b9d88c1dec8ccc67be - kernel-open/nvidia/nv-platform-pm.c
|
||||
@@ -108,7 +108,7 @@ c762aa186dc72ed0b9183492f9bd187c301d33d3 - kernel-open/nvidia/nv-kthread-q.c
|
||||
70bece14e12b9ffc92816ee8159a4ce596579d78 - kernel-open/nvidia/os-pci.c
|
||||
a677049bb56fa5ebe22fe43b0c4a12acd58a6677 - kernel-open/nvidia/nv-p2p.c
|
||||
e4d12f027cb5f74124da71bbbc23bcb33651834a - kernel-open/nvidia/nv-pci-table.c
|
||||
8b66b2577aa817d8b06712a3f4b92228708d1194 - kernel-open/nvidia/nv-pci.c
|
||||
415b8f457c01417f32c998ae310b5a42dd5805cb - kernel-open/nvidia/nv-pci.c
|
||||
6dfc57ac42bed97c6ff81d82e493f05b369e0b84 - kernel-open/nvidia/nvspdm_cryptlib_extensions.h
|
||||
bba706cfbc04b3a880b5e661066f92e765fad663 - kernel-open/nvidia/nv-caps-imex.c
|
||||
ed3c83f62e4ccc4b53d886eedd4b47518a361393 - kernel-open/nvidia/nv-dmabuf.c
|
||||
@@ -123,20 +123,20 @@ c50865d3070a0c3476ce24ff1ab4cc4e3f9ea4be - kernel-open/nvidia/detect-self-hosted
|
||||
3b27e4eaa97bd6fa71f1a075b50af69b1ec16454 - kernel-open/nvidia/libspdm_ec.c
|
||||
dd9e367cba9e0672c998ec6d570be38084a365ab - kernel-open/nvidia/libspdm_rand.c
|
||||
d8b8077adb7fd70eb9528d421bdef98c4378b57a - kernel-open/nvidia/nv-msi.c
|
||||
10ac1099331f83762a66fefe4b606628049acc47 - kernel-open/nvidia/nv-platform.c
|
||||
1cabb1e7fa825216c09f9d2f103657b0ac2dc85a - kernel-open/nvidia/nv-platform.c
|
||||
dd819a875c584bc469082fcf519779ea00b1d952 - kernel-open/nvidia/libspdm_aead_aes_gcm.c
|
||||
74958745f83b14c04aaa60248bf5c86ceef6b5cb - kernel-open/nvidia/nv-acpi.c
|
||||
4d19a1756af848d25fd2fd8cc691dcbcf0afb776 - kernel-open/nvidia/os-registry.c
|
||||
80f9ac558a57c60cbf70f3ecaf73c71e60c98885 - kernel-open/nvidia/nv-rsync.c
|
||||
7f5d251db1db4a179a67efea0178fbfda94f95d0 - kernel-open/nvidia/nv_gpu_ops.h
|
||||
642c3a7d10b263ab9a63073f83ad843566927b58 - kernel-open/nvidia/libspdm_hmac_sha.c
|
||||
13a85a087f33d9403626bd0fb7097c0359f0ec2d - kernel-open/nvidia/nv-clk.c
|
||||
7d53c2d27580d1b2cc56246d9972f3f310a3cd34 - kernel-open/nvidia/nv-clk.c
|
||||
0f28ebcdb723e836c923e40642429838fa9e86dc - kernel-open/nvidia/nvidia-sources.Kbuild
|
||||
99540efd2dfa6907b84e628e12370eefb0222850 - kernel-open/nvidia/nv-mmap.c
|
||||
11ac7a3a3b4def7fa31a289f5f8461ad90eca06b - kernel-open/nvidia/nv-tracepoint.h
|
||||
a14b9115cff1e5e7491737083588a5646c8c227b - kernel-open/nvidia/nv-report-err.h
|
||||
011f975d4f94f7b734efa23d3c8075321eaaf0e8 - kernel-open/nvidia/nv-memdbg.c
|
||||
c0cf3914fcda832f27472ba2fdb9c0f831f05733 - kernel-open/nvidia/nvidia.Kbuild
|
||||
1ba353673c266cb47ebcd07707e8ce125353e751 - kernel-open/nvidia/nvidia.Kbuild
|
||||
ac976b92e83f19125d6b3f7e95d9523e430b9b09 - kernel-open/nvidia/nv-p2p.h
|
||||
9b036018501d9b8543aabe7ec35dbe33023bb3e0 - kernel-open/nvidia/nv-host1x.c
|
||||
11778961efc78ef488be5387fa3de0c1b761c0d9 - kernel-open/nvidia/libspdm_sha.c
|
||||
@@ -168,10 +168,10 @@ f00a605cac7ffc7f309e3952c5d4cea7cbfc0b7e - kernel-open/nvidia-drm/nvidia-drm-gem
|
||||
763833186eabf1a0501434426c18161febf624d4 - kernel-open/nvidia-drm/nvidia-drm-fb.h
|
||||
4bada3ff7bfee8b7e222fc4cafb2ac97c67d7898 - kernel-open/nvidia-drm/nvidia-drm-gem-nvkms-memory.h
|
||||
99a2e922a448b4d76318ec151378c8bbf5971595 - kernel-open/nvidia-drm/nvidia-drm-helper.c
|
||||
ace74442a1a573cee5ed1f67801ab1bdc142b4ae - kernel-open/nvidia-drm/nvidia-drm.c
|
||||
ae6efc1bbec8a5e948b7244f4801f0b4b398f203 - kernel-open/nvidia-drm/nvidia-drm.c
|
||||
94c28482252c983fd97532634ffafea0bf77337a - kernel-open/nvidia-drm/nvidia-drm-ioctl.h
|
||||
a4f77f8ce94f63f3ca2a970c1935d8da48ab5ccc - kernel-open/nvidia-drm/nvidia-drm-format.c
|
||||
6ea6eeaae58c4ced3fb2d6bc1128b895165e5a9a - kernel-open/nvidia-drm/nvidia-drm-drv.h
|
||||
b78e4f40234f908e722f172485e4466d80b7b501 - kernel-open/nvidia-drm/nvidia-drm-drv.h
|
||||
4154c5562cebd2747bd15fb302c19cb0cefe1c9c - kernel-open/nvidia-drm/nvidia-drm-connector.h
|
||||
c762aa186dc72ed0b9183492f9bd187c301d33d3 - kernel-open/nvidia-drm/nv-kthread-q.c
|
||||
e4d12f027cb5f74124da71bbbc23bcb33651834a - kernel-open/nvidia-drm/nv-pci-table.c
|
||||
@@ -180,7 +180,7 @@ e4d12f027cb5f74124da71bbbc23bcb33651834a - kernel-open/nvidia-drm/nv-pci-table.c
|
||||
aa388c0d44060b8586967240927306006531cdb7 - kernel-open/nvidia-drm/nvidia-drm-helper.h
|
||||
d0b4f4383a7d29be40dd22e36faa96dae12d2364 - kernel-open/nvidia-drm/nvidia-drm-os-interface.h
|
||||
63a2fec1f2c425e084bdc07ff05bda62ed6b6ff1 - kernel-open/nvidia-drm/nvidia-drm-gem-user-memory.c
|
||||
0e2d8b82e79dfd18fff7ce45e42e501e2e7a06c2 - kernel-open/nvidia-drm/nvidia-drm-drv.c
|
||||
a46422076a6a3e439349fbda4fc46e4add29b8e5 - kernel-open/nvidia-drm/nvidia-drm-drv.c
|
||||
19031f2eaaaeb0fa1da61681fa6048c3e303848b - kernel-open/nvidia-drm/nvidia-drm-gem.c
|
||||
71ea2d5b02bf8fb3e8cf6b7c84686e2edbc244d0 - kernel-open/nvidia-drm/nvidia-drm-encoder.c
|
||||
7d409e3f0255d17457bffbf318e2f9ea160680a5 - kernel-open/nvidia-drm/nv-pci-table.h
|
||||
@@ -197,13 +197,13 @@ eff6a0b72274c8824b7a79e9aee261da3a6fb4f1 - kernel-open/nvidia-drm/nvidia-drm-gem
|
||||
995d8447f8539bd736cc09d62983ae8ebc7e3436 - kernel-open/nvidia-drm/nv_common_utils.h
|
||||
40b5613d1fbbe6b74bff67a5d07974ad321f75f0 - kernel-open/nvidia-drm/nvidia-drm-utils.h
|
||||
d924c494620760887546f428f87387d8ed5b99a6 - kernel-open/nvidia-drm/nvidia-drm-fb.c
|
||||
b5d956b3533912fa45fc241cf5fca7042aa8544d - kernel-open/nvidia-drm/nvidia-drm-crtc.c
|
||||
5eb8385042f3efa5c2e14d168cdb40b211467552 - kernel-open/nvidia-drm/nvidia-drm-crtc.c
|
||||
62a9b9b30fd7417d9ab085b2bfc731aadd9826f9 - kernel-open/nvidia-drm/nvidia-drm-os-interface.c
|
||||
ca86fee8bd52e6c84e376199c5f3890078bc2031 - kernel-open/nvidia-modeset/nvidia-modeset-os-interface.h
|
||||
73d346cb00350ecef5cb841316f24021d8b15e8d - kernel-open/nvidia-modeset/nvidia-modeset-linux.c
|
||||
885370cd7fc5f4d9d685d9d8d3e21460fd30cb38 - kernel-open/nvidia-modeset/nvkms.h
|
||||
04ea084a5c5d496cc43103d1997053246a2fa94c - kernel-open/nvidia-modeset/nvidia-modeset-linux.c
|
||||
b2a5ddfd8dcb3000b9d102bd55b5b560730e81d5 - kernel-open/nvidia-modeset/nvkms.h
|
||||
c762aa186dc72ed0b9183492f9bd187c301d33d3 - kernel-open/nvidia-modeset/nv-kthread-q.c
|
||||
8ef1c6aa1976e45bdf9c3eded10434daa5b79341 - kernel-open/nvidia-modeset/nvidia-modeset.Kbuild
|
||||
da6fd16e29300170aba8a652ea6296241f66243b - kernel-open/nvidia-modeset/nvidia-modeset.Kbuild
|
||||
2ea1436104463c5e3d177e8574c3b4298976d37e - kernel-open/nvidia-modeset/nvkms-ioctl.h
|
||||
13d4f9648118dd25b790be0d8d72ebaa12cc8d0e - src/common/sdk/nvidia/inc/rs_access.h
|
||||
579be4859587206460d8729804aab19180fb69bb - src/common/sdk/nvidia/inc/nvtypes.h
|
||||
@@ -459,7 +459,7 @@ bb7955387f6a286927e7922019676ca0aba713e6 - src/common/sdk/nvidia/inc/ctrl/ctrl00
|
||||
35367f08b96510a5312653b5197d6bb34c0a3d00 - src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073event.h
|
||||
a0cf9dfb520e3320cd9c154c01cd2f1a7bbbd864 - src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dp.h
|
||||
c2066c407f81538047c435fffca2705c28107663 - src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073specific.h
|
||||
ee2aba431a65f58defe5ecf3300457f86fde9203 - src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
|
||||
d727b328e995a7d969ec036f2d5b52264568a7bf - src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073system.h
|
||||
52f251090780737f14eb993150f3ae73be303921 - src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073dpu.h
|
||||
77eb4fab61225663a3f49b868c983d5d532ca184 - src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073svp.h
|
||||
6ca26c7149455e43f32e8b83b74f4a34a24a2d29 - src/common/sdk/nvidia/inc/ctrl/ctrl0073/ctrl0073base.h
|
||||
@@ -849,7 +849,7 @@ c5f16fdf43ca3d2845d120c219d1da11257072b0 - src/nvidia/nv-kernel.ld
|
||||
dcf4427b83cce7737f2b784d410291bf7a9612dc - src/nvidia/arch/nvalloc/unix/include/nv-reg.h
|
||||
4750735d6f3b334499c81d499a06a654a052713d - src/nvidia/arch/nvalloc/unix/include/nv-caps.h
|
||||
3c61881e9730a8a1686e422358cdfff59616b670 - src/nvidia/arch/nvalloc/unix/include/nv_escape.h
|
||||
aa399178ed2525bd2c9cf9d097e5c51ef96d1264 - src/nvidia/arch/nvalloc/unix/include/nv.h
|
||||
7fc52a43b242a8a921c2707589fa07c8c44da11c - src/nvidia/arch/nvalloc/unix/include/nv.h
|
||||
81592e5c17bebad04cd11d73672c859baa070329 - src/nvidia/arch/nvalloc/unix/include/nv-chardev-numbers.h
|
||||
e69045379ed58dc0110d16d17eb39a6f600f0d1d - src/nvidia/arch/nvalloc/unix/include/nv-ioctl-lockless-diag.h
|
||||
d1b1a1bc1fa30c1a966e95447f7831a06340d2d0 - src/nvidia/arch/nvalloc/unix/include/nv-priv.h
|
||||
@@ -864,14 +864,14 @@ b3ecb82f142a50bdc37eafaeb86d67f10fbcf73f - src/nvidia/arch/nvalloc/unix/include/
|
||||
af45762b6eeae912cc2602acf7dc31d30775ade7 - src/nvidia/arch/nvalloc/unix/include/nv-kernel-rmapi-ops.h
|
||||
107d1ecb8a128044260915ea259b1e64de3defea - src/nvidia/arch/nvalloc/unix/include/nv-ioctl-numbers.h
|
||||
3a26838c4edd3525daa68ac6fc7b06842dc6fc07 - src/nvidia/arch/nvalloc/unix/include/nv-gpu-info.h
|
||||
aa6a617b459fba57cd11dec4c669e30aae309405 - src/nvidia/arch/nvalloc/unix/src/os.c
|
||||
98a5a3bd7b94e69f4e7d2c3a1769583c17ef5b57 - src/nvidia/arch/nvalloc/unix/src/os.c
|
||||
a659a503a6fcffdcacd2b76ae6b1f156b4b9216c - src/nvidia/arch/nvalloc/unix/src/osmemdesc.c
|
||||
b5ae9b8d551a3e5489605c13686fb6cce4579598 - src/nvidia/arch/nvalloc/unix/src/power-management-tegra.c
|
||||
a17aae37486b325442e447489b64add3694ab8b0 - src/nvidia/arch/nvalloc/unix/src/osunix.c
|
||||
b5b409625fde1b640e4e93276e35248f0fccfa4c - src/nvidia/arch/nvalloc/unix/src/gcc_helper.c
|
||||
07f9c0995f1fbbba9eb819321996b57c1d2b86cd - src/nvidia/arch/nvalloc/unix/src/exports-stubs.c
|
||||
00e1da5b996760d70515c7d400462ebbc9dc4cba - src/nvidia/arch/nvalloc/unix/src/osinit.c
|
||||
be6bfb5b135e7f728ecff7aaac52e6cfa4f4f5ce - src/nvidia/arch/nvalloc/unix/src/osapi.c
|
||||
d8815125dbf79831b8fe55367bba60e7115243cc - src/nvidia/arch/nvalloc/unix/src/osinit.c
|
||||
b1e9f004152562aebd967505fcc1f52b774aef15 - src/nvidia/arch/nvalloc/unix/src/osapi.c
|
||||
a7383deea9dcab093323d8dde1ede73f85f93343 - src/nvidia/arch/nvalloc/unix/src/rmobjexportimport.c
|
||||
b1a6d0a1ca4307b8e8d9cf136c94ef7c9efbae4c - src/nvidia/arch/nvalloc/unix/src/registry.c
|
||||
915ee6dbffff92a86d68ac38549b25aa1e146872 - src/nvidia/arch/nvalloc/unix/src/os-hypervisor-stubs.c
|
||||
@@ -892,14 +892,14 @@ b9903d23010ea9d63117c27d5fe0cfba09849fa4 - src/nvidia/generated/g_context_dma_nv
|
||||
c5cad88aa7de5a04a3b6f9836f355347448d6a7b - src/nvidia/generated/g_rmconfig_util.h
|
||||
db1d1e047d00780efbe4c1c1ae6e4fecd3ab49e8 - src/nvidia/generated/g_os_desc_mem_nvoc.h
|
||||
1ec59322d0874153252a387dcb50bf6d7328d56e - src/nvidia/generated/g_system_mem_nvoc.c
|
||||
5d15a2256b4b06cca30e9d52e13f58c1bdecc7f6 - src/nvidia/generated/g_gpu_nvoc.c
|
||||
21e57b9c63e847eeb5a29c218db2c5c37db83298 - src/nvidia/generated/g_gpu_nvoc.c
|
||||
4613f3d42dbc899b278fca71c3aaae79159d7dbe - src/nvidia/generated/g_gpu_user_shared_data_nvoc.c
|
||||
b55573cb02ff8129aa4f5aa050ac53d1f4fcfdb2 - src/nvidia/generated/g_rs_resource_nvoc.h
|
||||
16c8d551a3a908ec194d39c88c5603cea436c9b7 - src/nvidia/generated/g_binary_api_nvoc.c
|
||||
a232e1da560db2322a921a9f0dc260ad703af2b4 - src/nvidia/generated/g_mem_nvoc.h
|
||||
c503ca5954b8f6ebdba96904a1616a55ce08a2d3 - src/nvidia/generated/g_device_nvoc.c
|
||||
e7cc58e9f8173583bd253fa73df56324e48aa5ad - src/nvidia/generated/g_io_vaspace_nvoc.h
|
||||
1f8b0acd13f5b75addebbc3303de6e56f2a87960 - src/nvidia/generated/g_rpc-structures.h
|
||||
b93ab0b9e39ca3c5b397cbdba58e4d9894d4130f - src/nvidia/generated/g_rpc-structures.h
|
||||
afda2b8579ed309e23be0ad1a835ee84fcbe535f - src/nvidia/generated/g_client_nvoc.h
|
||||
e97edab623386f7d1534b4f053a66fc8659167f6 - src/nvidia/generated/g_event_nvoc.h
|
||||
f4b2bffbdbb2b0b398e8dfe3420e46b2bf27839c - src/nvidia/generated/g_hal_nvoc.h
|
||||
@@ -910,7 +910,7 @@ abc769851bd523ee08cf829bf3864cf5475066ec - src/nvidia/generated/g_subdevice_nvoc
|
||||
255c404719b18c2a3aec2a47948c0fbcf4affd4b - src/nvidia/generated/rmconfig.h
|
||||
c7fda8cbe109ad2736694ce9ec0e2ab93d0e3f2c - src/nvidia/generated/g_mem_list_nvoc.h
|
||||
f9bdef39159a8475626a0edcbc3a53505a0ff80a - src/nvidia/generated/g_os_hal.h
|
||||
8a05682a80229723be9cc37bcf9509b6091e8a83 - src/nvidia/generated/g_mem_desc_nvoc.h
|
||||
dc7bbba203ee5ff91b6f14eb3abfad8c15854e1d - src/nvidia/generated/g_mem_desc_nvoc.h
|
||||
1702c9d021149c0f5c73ebeda7bea29e246af31d - src/nvidia/generated/g_nv_name_released.h
|
||||
2e0c45e4186d44774286a71daf797c980c2ddf7a - src/nvidia/generated/g_objtmr_nvoc.c
|
||||
9b78bc02a8fe0ec297167bb4bdb7f8255b94198b - src/nvidia/generated/g_disp_capabilities_nvoc.h
|
||||
@@ -936,8 +936,8 @@ d09bde39b1f12490ea0a696d6915d521c9f13953 - src/nvidia/generated/g_rpc-message-he
|
||||
f8b984c6bc09554753cfe6692dde2eb3171abc57 - src/nvidia/generated/g_disp_channel_nvoc.h
|
||||
4931b316fc042705a5f094c8c23b0038f980b404 - src/nvidia/generated/g_generic_engine_nvoc.h
|
||||
2a28557874bd51f567ef42c75fd4e3b09d8ad44d - src/nvidia/generated/g_gpu_arch_nvoc.c
|
||||
1f2a1faecdfa5bf3b23f3549b55a7b674ce06b63 - src/nvidia/generated/g_mem_mgr_nvoc.h
|
||||
561b0c5d638133350d2999ad1f66459155c889da - src/nvidia/generated/g_gpu_arch_nvoc.h
|
||||
a17058fe665949f1e3861fe092e29b229cefbe62 - src/nvidia/generated/g_mem_mgr_nvoc.h
|
||||
7aa02b964507a8269d35dc56170955025b98bd1a - src/nvidia/generated/g_gpu_arch_nvoc.h
|
||||
0b9296f7797325b80ff0900f19a3763b564eb26b - src/nvidia/generated/g_context_dma_nvoc.h
|
||||
4210ff36876e84e0adf1e9d4afb6654c7e6e5060 - src/nvidia/generated/g_resserv_nvoc.h
|
||||
3613b4ec9b285a4e29edefa833704789c887c189 - src/nvidia/generated/g_tmr_nvoc.c
|
||||
@@ -975,7 +975,7 @@ cc7ec616b034ec01da1c5176b6c62759c3f31a06 - src/nvidia/generated/g_subdevice_nvoc
|
||||
3b0e038829647cfe0d8807579db33416a420d1d2 - src/nvidia/generated/g_chips2halspec.h
|
||||
a1fad555b8ad36437992afdd6e3e08d236167ac7 - src/nvidia/generated/g_journal_nvoc.h
|
||||
d210a82e3dda39239201cfc1c2fcb2e971915c1e - src/nvidia/generated/g_device_nvoc.h
|
||||
f2752ea5d78a8dc2d90e92bb019def5fc3021fff - src/nvidia/generated/g_gpu_nvoc.h
|
||||
836f88914b046eadad9435786e1b474ee6690f5f - src/nvidia/generated/g_gpu_nvoc.h
|
||||
ea0d27b0f05818e2e44be7d04b31f8843e1d05b7 - src/nvidia/generated/g_io_vaspace_nvoc.c
|
||||
10529db24fb0501aa7f2aae25e0a87247ab5405c - src/nvidia/generated/g_resource_nvoc.h
|
||||
5d47bed309c731bfee4144f61093192e7efcaa55 - src/nvidia/generated/g_disp_channel_nvoc.c
|
||||
@@ -989,11 +989,11 @@ aa76beb8b33254fae884434b688093f9c7f12c87 - src/nvidia/generated/g_hal_private.h
|
||||
41bc858f6aca964a8977ad96911ecf1e8b46385d - src/nvidia/generated/g_hal_archimpl.h
|
||||
f87916eae53dbea2f6bdbe80a0e53ecc2071d9fd - src/nvidia/generated/g_lock_test_nvoc.c
|
||||
6b8597803d509372152e3915f15139186294add5 - src/nvidia/generated/g_gpu_class_list.c
|
||||
4aa67ec31a594b3280816de4aab2caa790983ce8 - src/nvidia/generated/g_kern_disp_nvoc.h
|
||||
d86e06d3022d34524459db10876053d664d80a73 - src/nvidia/generated/g_os_nvoc.h
|
||||
2101385d1332db9a2902370a6b3c6117ca8b2737 - src/nvidia/generated/g_kern_disp_nvoc.h
|
||||
d71ff42bc0fc0faf1999a6cbe88c4492a47e200e - src/nvidia/generated/g_os_nvoc.h
|
||||
e58abb783f7561d0af925c2fca392c5165fcb199 - src/nvidia/generated/g_kern_disp_nvoc.c
|
||||
d6a34926ab710156c9c4b2d9f12a44e6dafd43d1 - src/nvidia/generated/g_tmr_nvoc.h
|
||||
9b14b18f67e7e8e9d605b8b07bcfa53a42928dc6 - src/nvidia/generated/g_disp_objs_nvoc.h
|
||||
c4c67b0e0284656b32c7b4547e22d521c442124a - src/nvidia/generated/g_disp_objs_nvoc.h
|
||||
8e49b4d77641c98c6101dbc88a79290ceca6271a - src/nvidia/generated/g_rs_server_nvoc.h
|
||||
af206c390549eff5d690ad07f3e58cd417f07f5f - src/nvidia/generated/g_hal_register.h
|
||||
be659882e731b6a2019639265af46239c5c96ebf - src/nvidia/generated/g_hal_nvoc.c
|
||||
@@ -1005,7 +1005,7 @@ db76e8669776fbfa901c60d9b9908af2fabc4703 - src/nvidia/generated/g_virt_mem_mgr_n
|
||||
fb464cf839a1e76ac2a27346c7cd46ca921f1f56 - src/nvidia/generated/g_traceable_nvoc.c
|
||||
8588d6f88ab5e8682952063fe0e2c840b334c622 - src/nvidia/generated/g_eng_desc_nvoc.h
|
||||
de99523103dd7df0934cbe7aa21179ec7f241817 - src/nvidia/generated/g_os_desc_mem_nvoc.c
|
||||
03d2ae9f7011fcb3fe763e2789f7840c02c3ca66 - src/nvidia/generated/g_disp_objs_nvoc.c
|
||||
aa43dd8bdbdc71dc64d65e948221c7d5235588e7 - src/nvidia/generated/g_disp_objs_nvoc.c
|
||||
9b6cc3a5e9e35139e9245cbe753fe9a552a488c0 - src/nvidia/generated/g_syncpoint_mem_nvoc.h
|
||||
ae311b0968df9e9c9c2cec89e3060c472fc70a4c - src/nvidia/generated/g_mem_nvoc.c
|
||||
dc7a782be9a0096701771cb9b2dc020c2f814e6d - src/nvidia/generated/g_system_nvoc.h
|
||||
@@ -1039,7 +1039,7 @@ c314121149d3b28e58a62e2ccf81bf6904d1e4bc - src/nvidia/inc/libraries/utils/nvmacr
|
||||
72dcc09b77608263573bd34adf09393328eddf86 - src/nvidia/inc/libraries/utils/nvrange.h
|
||||
b598ccd2721892b6915d4be432f1fc332477b666 - src/nvidia/inc/libraries/utils/nvbitvector.h
|
||||
9aa5870d052a45c2489a6ea1a4f2e30fbc52d6be - src/nvidia/inc/libraries/utils/nv_enum.h
|
||||
357a7fd76af55cebcbc96a230064e23e50c03f57 - src/nvidia/inc/libraries/utils/nvprintf.h
|
||||
4849eb6c567e3ba952c22e702461c1a84ec88c6a - src/nvidia/inc/libraries/utils/nvprintf.h
|
||||
1b265cb4fcc628862e4b27ae63a897871987eb76 - src/nvidia/inc/libraries/utils/nvassert.h
|
||||
39113db75fdab5a42f9d8653ed1c90018b8b1df4 - src/nvidia/inc/libraries/containers/map.h
|
||||
11ce1423312f4c34df19672e45678d0531cc299d - src/nvidia/inc/libraries/containers/ringbuf.h
|
||||
@@ -1136,7 +1136,7 @@ bffae4da6a1f9b7dc7c879587fd674b49b46dac1 - src/nvidia/inc/kernel/core/core.h
|
||||
37f267155ddfc3db38f110dbb0397f0463d055ff - src/nvidia/inc/kernel/core/strict.h
|
||||
b00302aec7e4f4e3b89a2f699f8b1f18fc17b1ba - src/nvidia/inc/kernel/core/hal_mgr.h
|
||||
2d741243a6ae800052ddd478cc6aa7ad0b18f112 - src/nvidia/inc/kernel/core/prelude.h
|
||||
7e8435a73f777a70e0824aa3c5eca8799943fe78 - src/nvidia/inc/kernel/core/thread_state.h
|
||||
ebc7c06d9e94218af4cf6b0c03e83650e391e5bc - src/nvidia/inc/kernel/core/thread_state.h
|
||||
b5859c7862fb3eeb266f7213845885789801194a - src/nvidia/inc/kernel/core/system.h
|
||||
07f45cd5fab5814e21b9e84425564b43776118fd - src/nvidia/inc/kernel/gpu/gpu_resource_desc.h
|
||||
7010ff346c27b6453c091f5577672b8b1821808d - src/nvidia/inc/kernel/gpu/gpu_access.h
|
||||
@@ -1250,7 +1250,7 @@ c1e5733847085bede6eb128eff3bad14549a31db - src/nvidia/src/kernel/diagnostics/nvl
|
||||
d10c5031c3bc00ae1243729c39496df38d2c9ae3 - src/nvidia/src/kernel/os/os_init.c
|
||||
2255d1ae2d942c3fed9a4b0a41020d0e49cb8648 - src/nvidia/src/kernel/os/os_timer.c
|
||||
b887b661ffbe6c223c60f544b1fab32690cd8c75 - src/nvidia/src/kernel/os/os_sanity.c
|
||||
318538da49f206fdfe22af5ec2635d4d177216f4 - src/nvidia/src/kernel/os/os_stubs.c
|
||||
f228bc86fd9149675cb554d6f596d81fdd4c3770 - src/nvidia/src/kernel/os/os_stubs.c
|
||||
8800bf3ec679a1c3d36b89992b3f2f95365ec834 - src/nvidia/src/kernel/rmapi/entry_points.c
|
||||
348c34e13f006f1320536876cb7393d8232e61de - src/nvidia/src/kernel/rmapi/rpc_common.c
|
||||
8f033323f3ae264a79f779abb163442deb17e88a - src/nvidia/src/kernel/rmapi/rmapi.c
|
||||
@@ -1288,7 +1288,7 @@ a16bffcad38862470b4424fa9a1b0d4013304600 - src/nvidia/src/kernel/core/hal_mgr.c
|
||||
4d3f32dbc4cbe3d4d1301079eaf21005f74dea90 - src/nvidia/src/kernel/core/locks_common.c
|
||||
e7195ca43692b6fbf6a3533437650c596cee88db - src/nvidia/src/kernel/core/locks_minimal.c
|
||||
ee0bf4f81d33e9a7b6bbb2be27bb3973c8cb5b18 - src/nvidia/src/kernel/core/system.c
|
||||
3edd97e49797ae6e3152a8b800c9444ee8d42330 - src/nvidia/src/kernel/core/thread_state.c
|
||||
905a0f08067503374c757ed34d1ea87379ab4a71 - src/nvidia/src/kernel/core/thread_state.c
|
||||
afa03f17393b28b9fc791bf09c4d35833447808d - src/nvidia/src/kernel/core/hal/hal.c
|
||||
d3922085d63a7edf02b582fe0b6e3acba6124c25 - src/nvidia/src/kernel/core/hal/hals_all.c
|
||||
8eac3ea49f9a53063f7106211e5236372d87bdaf - src/nvidia/src/kernel/core/hal/info_block.c
|
||||
@@ -1308,7 +1308,7 @@ bc508781e640dbf756d9c9e43e75227d05b413c7 - src/nvidia/src/kernel/gpu/device_shar
|
||||
84c2c6a59313d36aa70c8a01cfedf1d1e7a3d931 - src/nvidia/src/kernel/gpu/gpu_access.c
|
||||
d0d744c416a52404a52c35ede015629990934003 - src/nvidia/src/kernel/gpu/gpu_engine_type.c
|
||||
12c1f9494317c34b1b9bfcc58bf7bee81b08c98e - src/nvidia/src/kernel/gpu/gpu_t234d_kernel.c
|
||||
f4b1e5dfefeae6021e6ca20e73d0fcaec1b5e95e - src/nvidia/src/kernel/gpu/gpu_rmapi.c
|
||||
ea626b20043182e3b374cb05d02c75b482fcd3a3 - src/nvidia/src/kernel/gpu/gpu_rmapi.c
|
||||
099da8d641fb4481f9a4c625588dd4aa4ce20bcd - src/nvidia/src/kernel/gpu/subdevice/subdevice.c
|
||||
6fab19f1f68bdb8d2b969efc6f030e2066bc6b5e - src/nvidia/src/kernel/gpu/subdevice/subdevice_ctrl_gpu_kernel.c
|
||||
b4e503b320119fecdb22dfda1268ce31e1a7ecd7 - src/nvidia/src/kernel/gpu/subdevice/generic_engine.c
|
||||
@@ -1324,14 +1324,14 @@ c67baeb5df33080d99f322786759fc3f5436301d - src/nvidia/src/kernel/gpu/disp/disp_c
|
||||
8fafebf746bfcde2c53435be386a8a0846973b0c - src/nvidia/src/kernel/gpu/disp/disp_object_kern_ctrl_minimal.c
|
||||
6437dd659a38c62cd81fb59f229bd94e59f37e71 - src/nvidia/src/kernel/gpu/disp/disp_sf_user.c
|
||||
0fbfb9dd91147f04bea1060788efc1121078c159 - src/nvidia/src/kernel/gpu/disp/kern_disp.c
|
||||
8900f684ba65090d30b80c48ed94a680e8e08eff - src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c
|
||||
5aa67b54fcd16f648d7a72b9c2c4ff3fb6d3a5be - src/nvidia/src/kernel/gpu/disp/disp_common_kern_ctrl_minimal.c
|
||||
56027ec220553e1febe42f37fd70757cbb034dcb - src/nvidia/src/kernel/gpu/disp/disp_objs.c
|
||||
b95080033ecc8736a0cdf9476cec7563c4a2af0f - src/nvidia/src/kernel/gpu/disp/vblank_callback/vblank.c
|
||||
caba45a10f43e7817f491e7856ef30dd49782f6e - src/nvidia/src/kernel/gpu/disp/head/kernel_head.c
|
||||
f59763139d9993ae545ded8057706cc4d65afc0c - src/nvidia/src/kernel/gpu/disp/head/arch/v04/kernel_head_0401.c
|
||||
eb00ffa5a892558d39db15f473e2c308acfd86d9 - src/nvidia/src/kernel/gpu/disp/arch/v04/kern_disp_0404.c
|
||||
2b19caf7def14190c99dc4e41983b4a3e3334f22 - src/nvidia/src/kernel/gpu/disp/arch/v04/kern_disp_0401.c
|
||||
70637a3e70e70693082d085476ca5c92f6d944eb - src/nvidia/src/kernel/gpu/disp/arch/v04/kern_disp_0402.c
|
||||
6d99d644a8294d08b0fdebf183306bbdadf819e3 - src/nvidia/src/kernel/gpu/disp/arch/v04/kern_disp_0402.c
|
||||
57fec208154cd0d25838a688f6457598baf2de7a - src/nvidia/src/kernel/gpu/disp/arch/v02/kern_disp_0204.c
|
||||
64aa574198449e9556328d1c08f08b3bde5bfad0 - src/nvidia/src/kernel/gpu/disp/arch/v05/kern_disp_0501.c
|
||||
d911e6ae9f7b96e6f441208d38701a8d833e7455 - src/nvidia/src/kernel/gpu/disp/arch/v03/kern_disp_0300.c
|
||||
@@ -1343,25 +1343,25 @@ f6e518524581b772f8fdbc80418a2018570940ca - src/nvidia/src/kernel/gpu/timer/timer
|
||||
10a8bfd47ce609763c07a0d61be2f71f9f91889e - src/nvidia/src/kernel/gpu/mem_mgr/mem_ctrl.c
|
||||
bfc82499a8b9b8ce10411f6c391b0e575dc7c0d6 - src/nvidia/src/kernel/gpu/mem_mgr/context_dma.c
|
||||
a62f423d6cf69e96b0523a233ec00353d63ee8bd - src/nvidia/src/kernel/gpu/mem_mgr/mem_utils.c
|
||||
7bd464742552f52a6e509659fde2a914e8194f26 - src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c
|
||||
92611eb4f3bed31064a9efbb54a1ece7ffcfc2af - src/nvidia/src/kernel/gpu/mem_mgr/mem_desc.c
|
||||
4a95b73f744807d96510b0ad7181eae5b12839ce - src/nvidia/src/kernel/gpu/mem_mgr/arch/turing/mem_mgr_tu102_base.c
|
||||
c3ce2ab15dcf7b0ae2dd89a62d73d16c0aba9687 - src/nvidia/src/kernel/gpu/dce_client/dce_client_rpc.c
|
||||
ce09583697a98a2d0e8466dd45764f15945f55c2 - src/nvidia/src/kernel/gpu/dce_client/dce_client_rpc.c
|
||||
cebb9eee63e23bb934881b3313e422b50fb38abb - src/nvidia/src/kernel/gpu/dce_client/dce_client.c
|
||||
d5d8ff429d3bda7103bafcb2dca94678efc8ddd8 - src/nvidia/src/kernel/gpu_mgr/gpu_group.c
|
||||
2b49d8a3413a1731bc4fb0bab3f32ff272a71a8c - src/nvidia/src/kernel/gpu_mgr/gpu_db.c
|
||||
37d1e3dd86e6409b8e461f90386e013194c9e4d1 - src/nvidia/src/kernel/gpu_mgr/gpu_mgmt_api.c
|
||||
fe618e428d9a172a0fd9412f5a20df64d7270418 - src/nvidia/src/kernel/gpu_mgr/gpu_mgr.c
|
||||
593bbc5b93b620019144fadf1281a180ec050012 - src/nvidia/src/kernel/mem_mgr/syncpoint_mem.c
|
||||
3ab3bfc528f187ba551c45889a471c39c5e1649c - src/nvidia/src/kernel/mem_mgr/standard_mem.c
|
||||
54c1d1a44474a7027c5290551e60f13678226301 - src/nvidia/src/kernel/mem_mgr/standard_mem.c
|
||||
44069d6ebbd94a11267e6cc0179ab167f91faec4 - src/nvidia/src/kernel/mem_mgr/virt_mem_mgr.c
|
||||
5a5e689cf264134ae8c4300d986c209c04167743 - src/nvidia/src/kernel/mem_mgr/vaspace.c
|
||||
5b9048e62581a3fbb0227d1a46c4ee8d8397bf5b - src/nvidia/src/kernel/mem_mgr/mem_mgr_internal.h
|
||||
630200d06b6588d7fa8c5b1ea16146e8281163d7 - src/nvidia/src/kernel/mem_mgr/io_vaspace.c
|
||||
d2bf2a33ee9ee9bfbe360506a34b9b4a91c9c6fa - src/nvidia/src/kernel/mem_mgr/system_mem.c
|
||||
04876ed2dedf0ac3228ec6261a0f3f79609e44a5 - src/nvidia/src/kernel/mem_mgr/system_mem.c
|
||||
873de51b330501a86ec7656fcf3f615034c49f8e - src/nvidia/src/kernel/mem_mgr/os_desc_mem.c
|
||||
ed8376f04af08af8da7d47c6340ff38a8910de87 - src/nvidia/src/kernel/mem_mgr/mem.c
|
||||
08762b3172f6309f1aeab895761193fa19cb176f - src/nvidia/interface/nv_sriov_defines.h
|
||||
96444cd1b6576851f5833c09c0e62c4dfa32e884 - src/nvidia/interface/nvrm_registry.h
|
||||
024b112ea410ee1b1badb585b03fdbabb64ade34 - src/nvidia/interface/nvrm_registry.h
|
||||
3f7b20e27e6576ee1f2f0557d269697a0b8af7ec - src/nvidia/interface/nv-firmware-registry.h
|
||||
d02ee5bb3f19dffd8b5c30dc852cea243bcdf399 - src/nvidia/interface/acpidsmguids.h
|
||||
60c7cafce7bd5240e8409e3c5b71214262347efc - src/nvidia/interface/acpigenfuncs.h
|
||||
@@ -1426,21 +1426,21 @@ a233bdcd5daa0582acf2cd5b0f339ad54d09bf13 - src/nvidia-modeset/include/dp/nvdp-ti
|
||||
2b91423ff88ca398324088d4f910e81f6944123a - src/nvidia-modeset/include/dp/nvdp-connector.h
|
||||
aa8aa13c6fc48ff5ef621f243e94dcc01a46dea3 - src/nvidia-modeset/kapi/include/nvkms-kapi-notifiers.h
|
||||
c0de6efe1d5c57da324118f108ea0570a6923036 - src/nvidia-modeset/kapi/include/nvkms-kapi-internal.h
|
||||
1ec3df41f465a332cae8d3bb97e575c9a2b936f4 - src/nvidia-modeset/kapi/src/nvkms-kapi.c
|
||||
b01351ece15ce0d54a19ad0d7ffa056963d72488 - src/nvidia-modeset/kapi/src/nvkms-kapi.c
|
||||
a4d52bb238ce94f3427f25bd169e58d5d5f4abd1 - src/nvidia-modeset/kapi/src/nvkms-kapi-notifiers.c
|
||||
ce42ceac4c4cf9d249d66ab57ae2f435cd9623fc - src/nvidia-modeset/kapi/src/nvkms-kapi-sync.c
|
||||
80c2c9a2a05beb0202239db8b0dd7080ff21c194 - src/nvidia-modeset/kapi/interface/nvkms-kapi-private.h
|
||||
29309411e2bf1c2e6492a104dcb9f53705c2e9aa - src/nvidia-modeset/kapi/interface/nvkms-kapi.h
|
||||
4c856c1324060dcb5a9e72e5e82c7a60f6324733 - src/nvidia-modeset/kapi/interface/nvkms-kapi.h
|
||||
11af2aeea97398b58f628fe4685b5dfcfda5791b - src/nvidia-modeset/src/nvkms-modeset.c
|
||||
016fd1b111731c6d323425d52bfe1a04d8bcade7 - src/nvidia-modeset/src/nvkms-headsurface-swapgroup.c
|
||||
a1dc7758c9eb3b3b05692f3a0484e27f57f9c5a1 - src/nvidia-modeset/src/nvkms-evo.c
|
||||
18276364b78968887b210b7541406e723319b068 - src/nvidia-modeset/src/nvkms-hw-flip.c
|
||||
37a6d00e8721a9c4134810f8be3e7168f8cbb226 - src/nvidia-modeset/src/nvkms-evo.c
|
||||
4758c601621603597bd2387c4f08b3fdc17e375d - src/nvidia-modeset/src/nvkms-hw-flip.c
|
||||
5e3188c2d9b580ff69e45842f841f5c92c0c6edb - src/nvidia-modeset/src/nvkms-headsurface-ioctl.c
|
||||
e1a3c31638416a0132c5301fe5dd4b1c93f14376 - src/nvidia-modeset/src/nvkms-cursor3.c
|
||||
d48ff2da5fac6f8cd0522a25b947b5b8c01812ba - src/nvidia-modeset/src/nvkms-rm.c
|
||||
30ad7839985dea46e6b6d43499210a3056da51ad - src/nvidia-modeset/src/nvkms-utils-flip.c
|
||||
2c24667a18374ae967917df219f3775d9a79ae04 - src/nvidia-modeset/src/nvkms-headsurface-3d.c
|
||||
a6723443f9069e8160dd7a4e9413a1c3a5a97489 - src/nvidia-modeset/src/nvkms-evo3.c
|
||||
fb8b4aa1e36f23e1927be3dbd351ab0357aeb735 - src/nvidia-modeset/src/nvkms-evo3.c
|
||||
9ce404d122bbdcd5f626f2c2b7ff08a9bfcf4045 - src/nvidia-modeset/src/nvkms-flip.c
|
||||
e5c96eb6b9884daf4a8d0d467b009008a45065b9 - src/nvidia-modeset/src/g_nvkms-evo-states.c
|
||||
094c2169412cb577a6e9db9420da084264119284 - src/nvidia-modeset/src/nvkms-hal.c
|
||||
@@ -1474,7 +1474,7 @@ be49ea18102a44914e0d7686c51430df18336383 - src/nvidia-modeset/src/nvkms-frameloc
|
||||
f754a27436fd1e1fa103de6110224c21ad7ea9f4 - src/nvidia-modeset/src/nvkms-pow.c
|
||||
e8c6d2eedfba19f8f06dd57f629588615cf1a2e9 - src/nvidia-modeset/src/nvkms-evo1.c
|
||||
d15f314bea66574e0ffc72966b86bae8366412f5 - src/nvidia-modeset/src/nvkms-console-restore.c
|
||||
f6e217845650e0e33591016a17df3b26ea6cdc7b - src/nvidia-modeset/src/nvkms-modepool.c
|
||||
0699860902369359e5ff1a0ef46b87e955d4bb7a - src/nvidia-modeset/src/nvkms-modepool.c
|
||||
403e6dbff0a607c2aecf3204c56633bd7b612ae2 - src/nvidia-modeset/src/nvkms-stereo.c
|
||||
fd6ecacc4f273c88960148c070dd17d93f49909b - src/nvidia-modeset/src/nvkms-lut.c
|
||||
771fee54d1123871e380db6f3227b4946b6be647 - src/nvidia-modeset/src/dp/nvdp-timer.cpp
|
||||
@@ -1501,7 +1501,7 @@ ce728856b76bfa428b199fd3b97e0cbc24ef54cd - src/nvidia-modeset/src/shaders/g_hopp
|
||||
02bb8bc0f5d228d4a9a383d797daffd8936c4ad7 - src/nvidia-modeset/src/shaders/g_ampere_shader_info.h
|
||||
9f35175e44247d4facb26a60614d40fcdb74416f - src/nvidia-modeset/src/shaders/g_shader_names.h
|
||||
ca86fee8bd52e6c84e376199c5f3890078bc2031 - src/nvidia-modeset/os-interface/include/nvidia-modeset-os-interface.h
|
||||
885370cd7fc5f4d9d685d9d8d3e21460fd30cb38 - src/nvidia-modeset/os-interface/include/nvkms.h
|
||||
b2a5ddfd8dcb3000b9d102bd55b5b560730e81d5 - src/nvidia-modeset/os-interface/include/nvkms.h
|
||||
51b367a6e289cc8957388745988315024f97506e - src/nvidia-modeset/interface/nvkms-api.h
|
||||
b986bc6591ba17a74ad81ec4c93347564c6d5165 - src/nvidia-modeset/interface/nvkms-format.h
|
||||
2ea1436104463c5e3d177e8574c3b4298976d37e - src/nvidia-modeset/interface/nvkms-ioctl.h
|
||||
|
||||
@@ -1055,7 +1055,6 @@ typedef struct nv_alloc_s {
|
||||
NvBool unencrypted : 1;
|
||||
NvBool coherent : 1;
|
||||
NvBool carveout : 1;
|
||||
NvBool no_reclaim : 1;
|
||||
} flags;
|
||||
unsigned int cache_type;
|
||||
unsigned int num_pages;
|
||||
@@ -1472,6 +1471,7 @@ typedef struct nv_linux_state_s {
|
||||
struct reset_control *nvdisplay_reset;
|
||||
struct reset_control *dsi_core_reset;
|
||||
struct reset_control *mipi_cal_reset;
|
||||
struct reset_control *hdacodec_reset;
|
||||
|
||||
/*
|
||||
* nv_imp_icc_path represents the interconnect path across which display
|
||||
|
||||
@@ -58,12 +58,6 @@ typedef struct {
|
||||
*/
|
||||
void (*suspend)(NvU32 gpu_id);
|
||||
void (*resume)(NvU32 gpu_id);
|
||||
|
||||
/* Remove callback, called when a device is going away completely. */
|
||||
void (*remove)(NvU32 gpu_id);
|
||||
|
||||
/* Probe callback, called when a device is being hotplugged. */
|
||||
void (*probe)(const nv_gpu_info_t *gpu_info);
|
||||
} nvidia_modeset_callbacks_t;
|
||||
|
||||
/*
|
||||
|
||||
@@ -38,5 +38,4 @@ int nvidia_dev_get_pci_info(const NvU8 *, struct pci_dev **, NvU64 *, NvU64 *);
|
||||
nv_linux_state_t * find_pci(NvU32, NvU8, NvU8, NvU8);
|
||||
NvBool nv_pci_is_valid_topology_for_direct_pci(nv_state_t *, struct pci_dev *);
|
||||
NvBool nv_pci_has_common_pci_switch(nv_state_t *nv, struct pci_dev *);
|
||||
void nv_pci_tegra_boost_sys_uproc(struct device *dev);
|
||||
#endif
|
||||
|
||||
@@ -45,16 +45,4 @@ void nv_soc_free_irqs(nv_state_t *nv);
|
||||
|
||||
#define NV_SUPPORTS_PLATFORM_DISPLAY_DEVICE (NV_SUPPORTS_PLATFORM_DEVICE && NV_SUPPORTS_DCE_CLIENT_IPC)
|
||||
|
||||
#if defined(CONFIG_OF)
|
||||
NV_STATUS nv_platform_get_screen_info_dt(
|
||||
NvU64 *pPhysicalAddress,
|
||||
NvU32 *pFbWidth,
|
||||
NvU32 *pFbHeight,
|
||||
NvU32 *pFbDepth,
|
||||
NvU32 *pFbPitch,
|
||||
NvU64 *pFbSize
|
||||
);
|
||||
|
||||
#endif // CONFIG_OF
|
||||
|
||||
#endif
|
||||
|
||||
@@ -76,8 +76,6 @@ NV_STATUS nv_set_system_power_state (nv_power_state_t, nv_pm_action_depth_t)
|
||||
|
||||
void nvidia_modeset_suspend (NvU32 gpuId);
|
||||
void nvidia_modeset_resume (NvU32 gpuId);
|
||||
void nvidia_modeset_remove (NvU32 gpuId);
|
||||
void nvidia_modeset_probe (const nv_linux_state_t *nvl);
|
||||
NvBool nv_is_uuid_in_gpu_exclusion_list (const char *);
|
||||
|
||||
NV_STATUS nv_parse_per_device_option_string(nvidia_stack_t *sp);
|
||||
|
||||
@@ -143,8 +143,6 @@ typedef enum _TEGRASOC_WHICH_CLK
|
||||
TEGRASOC_WHICH_CLK_SPPLL0_DIV10,
|
||||
TEGRASOC_WHICH_CLK_SPPLL0_DIV25,
|
||||
TEGRASOC_WHICH_CLK_SPPLL1_VCO,
|
||||
TEGRASOC_WHICH_CLK_SPPLL0,
|
||||
TEGRASOC_WHICH_CLK_SPPLL1,
|
||||
TEGRASOC_WHICH_CLK_VPLL0_REF,
|
||||
TEGRASOC_WHICH_CLK_VPLL0,
|
||||
TEGRASOC_WHICH_CLK_VPLL1,
|
||||
@@ -230,9 +228,6 @@ typedef enum _TEGRASOC_WHICH_CLK
|
||||
TEGRASOC_WHICH_CLK_MIPI_CAL,
|
||||
TEGRASOC_WHICH_CLK_UART_FST_MIPI_CAL,
|
||||
TEGRASOC_WHICH_CLK_SOR0_DIV,
|
||||
TEGRASOC_WHICH_CLK_SOR1_DIV,
|
||||
TEGRASOC_WHICH_CLK_SOR2_DIV,
|
||||
TEGRASOC_WHICH_CLK_SOR3_DIV,
|
||||
TEGRASOC_WHICH_CLK_DISP_ROOT,
|
||||
TEGRASOC_WHICH_CLK_HUB_ROOT,
|
||||
TEGRASOC_WHICH_CLK_PLLA_DISP,
|
||||
@@ -601,12 +596,6 @@ typedef struct nv_state_t
|
||||
NvU32 dispNisoStreamId;
|
||||
} iommus;
|
||||
|
||||
struct {
|
||||
NvU32 max_dispclk_rate_using_disppllkhz;
|
||||
NvU32 max_dispclk_rate_using_sppll0clkoutakhz;
|
||||
NvU32 max_hubclk_rate_using_sppll0clkoutbkhz;
|
||||
} clocks;
|
||||
|
||||
/* Console is managed by drm drivers or NVKMS */
|
||||
NvBool client_managed_console;
|
||||
} nv_state_t;
|
||||
@@ -675,24 +664,23 @@ typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64, nvgpuGpuMemor
|
||||
* flags
|
||||
*/
|
||||
|
||||
#define NV_FLAG_OPEN 0x0001
|
||||
#define NV_FLAG_EXCLUDE 0x0002
|
||||
#define NV_FLAG_CONTROL 0x0004
|
||||
#define NV_FLAG_PCI_P2P_UNSUPPORTED_CHIPSET 0x0008
|
||||
#define NV_FLAG_SOC_DISPLAY 0x0010
|
||||
#define NV_FLAG_USES_MSI 0x0020
|
||||
#define NV_FLAG_USES_MSIX 0x0040
|
||||
#define NV_FLAG_PASSTHRU 0x0080
|
||||
#define NV_FLAG_SUSPENDED 0x0100
|
||||
#define NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT 0x0200
|
||||
#define NV_FLAG_OPEN 0x0001
|
||||
#define NV_FLAG_EXCLUDE 0x0002
|
||||
#define NV_FLAG_CONTROL 0x0004
|
||||
#define NV_FLAG_PCI_P2P_UNSUPPORTED_CHIPSET 0x0008
|
||||
#define NV_FLAG_SOC_DISPLAY 0x0010
|
||||
#define NV_FLAG_USES_MSI 0x0020
|
||||
#define NV_FLAG_USES_MSIX 0x0040
|
||||
#define NV_FLAG_PASSTHRU 0x0080
|
||||
#define NV_FLAG_SUSPENDED 0x0100
|
||||
/* To be set when an FLR needs to be triggered after device shut down. */
|
||||
#define NV_FLAG_TRIGGER_FLR 0x0400
|
||||
#define NV_FLAG_PERSISTENT_SW_STATE 0x0800
|
||||
#define NV_FLAG_IN_RECOVERY 0x1000
|
||||
#define NV_FLAG_PCI_REMOVE_IN_PROGRESS 0x2000
|
||||
#define NV_FLAG_UNBIND_LOCK 0x4000
|
||||
#define NV_FLAG_TRIGGER_FLR 0x0400
|
||||
#define NV_FLAG_PERSISTENT_SW_STATE 0x0800
|
||||
#define NV_FLAG_IN_RECOVERY 0x1000
|
||||
#define NV_FLAG_PCI_REMOVE_IN_PROGRESS 0x2000
|
||||
#define NV_FLAG_UNBIND_LOCK 0x4000
|
||||
/* To be set when GPU is not present on the bus, to help device teardown */
|
||||
#define NV_FLAG_IN_SURPRISE_REMOVAL 0x8000
|
||||
#define NV_FLAG_IN_SURPRISE_REMOVAL 0x8000
|
||||
|
||||
typedef enum
|
||||
{
|
||||
@@ -740,20 +728,6 @@ typedef enum
|
||||
NV_MEMORY_TYPE_DEVICE_MMIO, /* All kinds of MMIO referred by NVRM e.g. BARs and MCFG of device */
|
||||
} nv_memory_type_t;
|
||||
|
||||
typedef struct nv_allocation_request_s
|
||||
{
|
||||
NvU32 count;
|
||||
NvU64 page_size;
|
||||
NvBool alloc_type_contiguous;
|
||||
NvU32 cache_type;
|
||||
NvBool alloc_type_zeroed;
|
||||
NvBool unencrypted;
|
||||
NvBool no_reclaim;
|
||||
NvS32 node_id;
|
||||
NvU64 *pte_array;
|
||||
void **private;
|
||||
} nv_allocation_request_t;
|
||||
|
||||
#define NV_PRIMARY_VGA(nv) ((nv)->primary_vga)
|
||||
|
||||
#define NV_IS_CTL_DEVICE(nv) ((nv)->flags & NV_FLAG_CONTROL)
|
||||
@@ -763,9 +737,6 @@ typedef struct nv_allocation_request_s
|
||||
#define NV_IS_DEVICE_IN_SURPRISE_REMOVAL(nv) \
|
||||
(((nv)->flags & NV_FLAG_IN_SURPRISE_REMOVAL) != 0)
|
||||
|
||||
#define NV_HAS_CONSOLE_IN_SYSMEM_CARVEOUT(nv) \
|
||||
(((nv)->flags & NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT) != 0)
|
||||
|
||||
/*
|
||||
* For console setup by EFI GOP, the base address is BAR1.
|
||||
* For console setup by VBIOS, the base address is BAR2 + 16MB.
|
||||
@@ -925,7 +896,7 @@ nv_state_t* NV_API_CALL nv_get_ctl_state (void);
|
||||
void NV_API_CALL nv_set_dma_address_size (nv_state_t *, NvU32 );
|
||||
|
||||
NV_STATUS NV_API_CALL nv_alias_pages (nv_state_t *, NvU32, NvU64, NvU32, NvU32, NvU64, NvU64 *, NvBool, void **);
|
||||
NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, nv_allocation_request_t *);
|
||||
NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvU64, NvBool, NvU32, NvBool, NvBool, NvS32, NvU64 *, void **);
|
||||
NV_STATUS NV_API_CALL nv_free_pages (nv_state_t *, NvU32, NvBool, NvU32, void *);
|
||||
|
||||
NV_STATUS NV_API_CALL nv_register_user_pages (nv_state_t *, NvU64, NvU64 *, void *, void **, NvBool);
|
||||
@@ -1063,7 +1034,6 @@ NV_STATUS NV_API_CALL nv_i2c_transfer(nv_state_t *, NvU32, NvU8, nv_i2c_msg_t *,
|
||||
void NV_API_CALL nv_i2c_unregister_clients(nv_state_t *);
|
||||
NV_STATUS NV_API_CALL nv_i2c_bus_status(nv_state_t *, NvU32, NvS32 *, NvS32 *);
|
||||
NV_STATUS NV_API_CALL nv_imp_get_import_data (TEGRA_IMP_IMPORT_DATA *);
|
||||
NV_STATUS NV_API_CALL nv_imp_get_uefi_data (nv_state_t *nv, NvU32 *iso_bw_kbps, NvU32 *floor_bw_kbps);
|
||||
NV_STATUS NV_API_CALL nv_imp_enable_disable_rfl (nv_state_t *nv, NvBool bEnable);
|
||||
NV_STATUS NV_API_CALL nv_imp_icc_set_bw (nv_state_t *nv, NvU32 avg_bw_kbps, NvU32 floor_bw_kbps);
|
||||
NV_STATUS NV_API_CALL nv_get_num_dpaux_instances(nv_state_t *nv, NvU32 *num_instances);
|
||||
|
||||
@@ -598,17 +598,13 @@ typedef enum NvKmsKapiRegisterWaiterResultRec {
|
||||
NVKMS_KAPI_REG_WAITER_ALREADY_SIGNALLED,
|
||||
} NvKmsKapiRegisterWaiterResult;
|
||||
|
||||
typedef void NvKmsKapiSuspendResumeCallbackFunc(NvBool suspend);
|
||||
|
||||
struct NvKmsKapiGpuInfo {
|
||||
nv_gpu_info_t gpuInfo;
|
||||
MIGDeviceId migDevice;
|
||||
};
|
||||
|
||||
struct NvKmsKapiCallbacks {
|
||||
void (*suspendResume)(NvBool suspend);
|
||||
void (*remove)(NvU32 gpuId);
|
||||
void (*probe)(const struct NvKmsKapiGpuInfo *gpu_info);
|
||||
};
|
||||
|
||||
struct NvKmsKapiFunctionsTable {
|
||||
|
||||
/*!
|
||||
@@ -1477,12 +1473,12 @@ struct NvKmsKapiFunctionsTable {
|
||||
);
|
||||
|
||||
/*!
|
||||
* Set the pointer to the callback function table.
|
||||
* Set the callback function for suspending and resuming the display system.
|
||||
*/
|
||||
void
|
||||
(*setCallbacks)
|
||||
(*setSuspendResumeCallback)
|
||||
(
|
||||
const struct NvKmsKapiCallbacks *callbacks
|
||||
NvKmsKapiSuspendResumeCallbackFunc *function
|
||||
);
|
||||
|
||||
/*!
|
||||
|
||||
@@ -2464,22 +2464,6 @@ compile_test() {
|
||||
compile_check_conftest "$CODE" "NV_PM_RUNTIME_AVAILABLE" "" "generic"
|
||||
;;
|
||||
|
||||
pm_domain_available)
|
||||
#
|
||||
# Determine whether dev_pm_genpd_suspend() exists.
|
||||
#
|
||||
# This was added to the kernel in commit fc51989062138
|
||||
# ("PM: domains: Rename pm_genpd_syscore_poweroff|poweron()")
|
||||
# in v5.11-rc1 (2020-11-10),
|
||||
#
|
||||
CODE="
|
||||
#include <linux/pm_domain.h>
|
||||
void pm_domain_conftest(void) {
|
||||
dev_pm_genpd_suspend();
|
||||
}"
|
||||
compile_check_conftest "$CODE" "NV_PM_DOMAIN_AVAILABLE" "" "functions"
|
||||
;;
|
||||
|
||||
dma_direct_map_resource)
|
||||
#
|
||||
# Determine whether dma_is_direct() exists.
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* Copyright (c) 2015-2025, NVIDIA CORPORATION. All rights reserved.
|
||||
* Copyright (c) 2015-2022, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
@@ -201,15 +201,6 @@ plane_req_config_disable(struct NvKmsKapiLayerRequestedConfig *req_config)
|
||||
req_config->flags.srcWHChanged = NV_TRUE;
|
||||
req_config->flags.dstXYChanged = NV_TRUE;
|
||||
req_config->flags.dstWHChanged = NV_TRUE;
|
||||
req_config->flags.cscChanged = NV_TRUE;
|
||||
req_config->flags.inputTfChanged = NV_TRUE;
|
||||
req_config->flags.outputTfChanged = NV_TRUE;
|
||||
req_config->flags.inputColorSpaceChanged = NV_TRUE;
|
||||
req_config->flags.inputColorRangeChanged = NV_TRUE;
|
||||
req_config->flags.hdrMetadataChanged = NV_TRUE;
|
||||
req_config->flags.matrixOverridesChanged = NV_TRUE;
|
||||
req_config->flags.ilutChanged = NV_TRUE;
|
||||
req_config->flags.tmoChanged = NV_TRUE;
|
||||
}
|
||||
|
||||
static inline void
|
||||
|
||||
@@ -104,7 +104,6 @@ static int nv_drm_revoke_modeset_permission(struct drm_device *dev,
|
||||
NvU32 dpyId);
|
||||
static int nv_drm_revoke_sub_ownership(struct drm_device *dev);
|
||||
|
||||
static DEFINE_MUTEX(dev_list_mutex);
|
||||
static struct nv_drm_device *dev_list = NULL;
|
||||
|
||||
static const char* nv_get_input_colorspace_name(
|
||||
@@ -2096,22 +2095,13 @@ void nv_drm_register_drm_device(const struct NvKmsKapiGpuInfo *gpu_info)
|
||||
#elif defined(NV_DRM_FBDEV_GENERIC_AVAILABLE)
|
||||
drm_fbdev_generic_setup(dev, 32);
|
||||
#endif
|
||||
|
||||
/*
|
||||
* The fbdev setup functions above may override the
|
||||
* `pm_vt_switch_required` state of our PCI device. For now, a VT switch
|
||||
* is required during suspend and resume.
|
||||
*/
|
||||
pm_vt_switch_required(dev->dev, true);
|
||||
}
|
||||
#endif /* defined(NV_DRM_FBDEV_AVAILABLE) */
|
||||
|
||||
/* Add NVIDIA-DRM device into list */
|
||||
|
||||
mutex_lock(&dev_list_mutex);
|
||||
nv_dev->next = dev_list;
|
||||
dev_list = nv_dev;
|
||||
mutex_unlock(&dev_list_mutex);
|
||||
|
||||
return; /* Success */
|
||||
|
||||
@@ -2149,81 +2139,22 @@ int nv_drm_probe_devices(void)
|
||||
}
|
||||
#endif
|
||||
|
||||
static struct nv_drm_device*
|
||||
nv_drm_pop_device(void)
|
||||
{
|
||||
struct nv_drm_device *nv_dev;
|
||||
|
||||
mutex_lock(&dev_list_mutex);
|
||||
|
||||
nv_dev = dev_list;
|
||||
if (nv_dev) {
|
||||
dev_list = nv_dev->next;
|
||||
nv_dev->next = NULL;
|
||||
}
|
||||
|
||||
mutex_unlock(&dev_list_mutex);
|
||||
return nv_dev;
|
||||
}
|
||||
|
||||
static struct nv_drm_device*
|
||||
nv_drm_find_and_remove_device(NvU32 gpuId)
|
||||
{
|
||||
struct nv_drm_device **pPrev = &dev_list;
|
||||
struct nv_drm_device *nv_dev;
|
||||
|
||||
mutex_lock(&dev_list_mutex);
|
||||
nv_dev = *pPrev;
|
||||
|
||||
while (nv_dev) {
|
||||
if (nv_dev->gpu_info.gpu_id == gpuId) {
|
||||
/* Remove it from the linked list */
|
||||
*pPrev = nv_dev->next;
|
||||
nv_dev->next = NULL;
|
||||
break;
|
||||
}
|
||||
|
||||
pPrev = &nv_dev->next;
|
||||
nv_dev = *pPrev;
|
||||
}
|
||||
|
||||
mutex_unlock(&dev_list_mutex);
|
||||
return nv_dev;
|
||||
}
|
||||
|
||||
static void nv_drm_dev_destroy(struct nv_drm_device *nv_dev)
|
||||
{
|
||||
struct drm_device *dev = nv_dev->dev;
|
||||
|
||||
nv_drm_dev_unload(dev);
|
||||
drm_dev_put(dev);
|
||||
nv_drm_free(nv_dev);
|
||||
}
|
||||
|
||||
/*
|
||||
* Unregister a single NVIDIA DRM device.
|
||||
*/
|
||||
void nv_drm_remove(NvU32 gpuId)
|
||||
{
|
||||
struct nv_drm_device *nv_dev = nv_drm_find_and_remove_device(gpuId);
|
||||
|
||||
if (nv_dev) {
|
||||
NV_DRM_DEV_LOG_INFO(nv_dev, "Removing device");
|
||||
drm_dev_unplug(nv_dev->dev);
|
||||
nv_drm_dev_destroy(nv_dev);
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Unregister all NVIDIA DRM devices.
|
||||
*/
|
||||
void nv_drm_remove_devices(void)
|
||||
{
|
||||
struct nv_drm_device *nv_dev;
|
||||
while (dev_list != NULL) {
|
||||
struct nv_drm_device *next = dev_list->next;
|
||||
struct drm_device *dev = dev_list->dev;
|
||||
|
||||
while ((nv_dev = nv_drm_pop_device())) {
|
||||
drm_dev_unregister(nv_dev->dev);
|
||||
nv_drm_dev_destroy(nv_dev);
|
||||
drm_dev_unregister(dev);
|
||||
nv_drm_dev_unload(dev);
|
||||
drm_dev_put(dev);
|
||||
|
||||
nv_drm_free(dev_list);
|
||||
|
||||
dev_list = next;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -2245,10 +2176,11 @@ void nv_drm_remove_devices(void)
|
||||
*/
|
||||
void nv_drm_suspend_resume(NvBool suspend)
|
||||
{
|
||||
static DEFINE_MUTEX(nv_drm_suspend_mutex);
|
||||
static NvU32 nv_drm_suspend_count = 0;
|
||||
struct nv_drm_device *nv_dev;
|
||||
|
||||
mutex_lock(&dev_list_mutex);
|
||||
mutex_lock(&nv_drm_suspend_mutex);
|
||||
|
||||
/*
|
||||
* Count the number of times the driver is asked to suspend. Suspend all DRM
|
||||
@@ -2298,7 +2230,7 @@ void nv_drm_suspend_resume(NvBool suspend)
|
||||
#endif /* NV_DRM_ATOMIC_MODESET_AVAILABLE */
|
||||
|
||||
done:
|
||||
mutex_unlock(&dev_list_mutex);
|
||||
mutex_unlock(&nv_drm_suspend_mutex);
|
||||
}
|
||||
|
||||
#endif /* NV_DRM_AVAILABLE */
|
||||
|
||||
@@ -31,7 +31,6 @@ struct NvKmsKapiGpuInfo;
|
||||
|
||||
int nv_drm_probe_devices(void);
|
||||
|
||||
void nv_drm_remove(NvU32 gpuId);
|
||||
void nv_drm_remove_devices(void);
|
||||
|
||||
void nv_drm_suspend_resume(NvBool suspend);
|
||||
|
||||
@@ -33,12 +33,6 @@ static struct NvKmsKapiFunctionsTable nvKmsFuncsTable = {
|
||||
|
||||
const struct NvKmsKapiFunctionsTable* const nvKms = &nvKmsFuncsTable;
|
||||
|
||||
const struct NvKmsKapiCallbacks nv_drm_kapi_callbacks = {
|
||||
.suspendResume = nv_drm_suspend_resume,
|
||||
.remove = nv_drm_remove,
|
||||
.probe = nv_drm_register_drm_device,
|
||||
};
|
||||
|
||||
#endif
|
||||
|
||||
int nv_drm_init(void)
|
||||
@@ -51,7 +45,7 @@ int nv_drm_init(void)
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
nvKms->setCallbacks(&nv_drm_kapi_callbacks);
|
||||
nvKms->setSuspendResumeCallback(nv_drm_suspend_resume);
|
||||
return nv_drm_probe_devices();
|
||||
#else
|
||||
return 0;
|
||||
@@ -61,7 +55,7 @@ int nv_drm_init(void)
|
||||
void nv_drm_exit(void)
|
||||
{
|
||||
#if defined(NV_DRM_AVAILABLE)
|
||||
nvKms->setCallbacks(NULL);
|
||||
nvKms->setSuspendResumeCallback(NULL);
|
||||
nv_drm_remove_devices();
|
||||
#endif
|
||||
}
|
||||
|
||||
@@ -126,15 +126,6 @@ module_param_named(config_file, nvkms_conf, charp, 0400);
|
||||
|
||||
static atomic_t nvkms_alloc_called_count;
|
||||
|
||||
#define NV_SUPPORTS_PLATFORM_DEVICE_PUT NV_IS_EXPORT_SYMBOL_GPL_platform_device_put
|
||||
|
||||
#if defined(NV_LINUX_NVHOST_H_PRESENT) && NV_SUPPORTS_PLATFORM_DEVICE_PUT
|
||||
#if defined(NV_LINUX_HOST1X_NEXT_H_PRESENT) || defined(CONFIG_TEGRA_GRHOST)
|
||||
#define NVKMS_NVHOST_SYNCPT_SUPPORTED
|
||||
struct platform_device *nvhost_platform_device = NULL;
|
||||
#endif
|
||||
#endif
|
||||
|
||||
NvBool nvkms_test_fail_alloc_core_channel(
|
||||
enum FailAllocCoreChannelMethod method
|
||||
)
|
||||
@@ -206,18 +197,21 @@ NvBool nvkms_kernel_supports_syncpts(void)
|
||||
* support for syncpts; callers must also check that the hardware
|
||||
* supports syncpts.
|
||||
*/
|
||||
#if defined(NVKMS_NVHOST_SYNCPT_SUPPORTED)
|
||||
#if (defined(CONFIG_TEGRA_GRHOST) || defined(NV_LINUX_HOST1X_NEXT_H_PRESENT))
|
||||
return NV_TRUE;
|
||||
#else
|
||||
return NV_FALSE;
|
||||
#endif
|
||||
}
|
||||
|
||||
#define NVKMS_SYNCPT_STUBS_NEEDED
|
||||
|
||||
/*************************************************************************
|
||||
* NVKMS interface for nvhost unit for sync point APIs.
|
||||
*************************************************************************/
|
||||
#if defined(NV_LINUX_NVHOST_H_PRESENT) && defined(CONFIG_TEGRA_GRHOST)
|
||||
|
||||
#if defined(NVKMS_NVHOST_SYNCPT_SUPPORTED) && defined(CONFIG_TEGRA_GRHOST)
|
||||
#undef NVKMS_SYNCPT_STUBS_NEEDED
|
||||
|
||||
#include <linux/nvhost.h>
|
||||
|
||||
@@ -225,21 +219,17 @@ NvBool nvkms_syncpt_op(
|
||||
enum NvKmsSyncPtOp op,
|
||||
NvKmsSyncPtOpParams *params)
|
||||
{
|
||||
if (nvhost_platform_device == NULL) {
|
||||
nvkms_log(NVKMS_LOG_LEVEL_ERROR, NVKMS_LOG_PREFIX,
|
||||
"Failed to get default nvhost device");
|
||||
return NV_FALSE;
|
||||
}
|
||||
struct platform_device *pdev = nvhost_get_default_device();
|
||||
|
||||
switch (op) {
|
||||
|
||||
case NVKMS_SYNCPT_OP_ALLOC:
|
||||
params->alloc.id = nvhost_get_syncpt_client_managed(
|
||||
nvhost_platform_device, params->alloc.syncpt_name);
|
||||
pdev, params->alloc.syncpt_name);
|
||||
break;
|
||||
|
||||
case NVKMS_SYNCPT_OP_PUT:
|
||||
nvhost_syncpt_put_ref_ext(nvhost_platform_device, params->put.id);
|
||||
nvhost_syncpt_put_ref_ext(pdev, params->put.id);
|
||||
break;
|
||||
|
||||
case NVKMS_SYNCPT_OP_FD_TO_ID_AND_THRESH: {
|
||||
@@ -273,7 +263,7 @@ NvBool nvkms_syncpt_op(
|
||||
|
||||
case NVKMS_SYNCPT_OP_ID_AND_THRESH_TO_FD:
|
||||
nvhost_syncpt_create_fence_single_ext(
|
||||
nvhost_platform_device,
|
||||
pdev,
|
||||
params->id_and_thresh_to_fd.id,
|
||||
params->id_and_thresh_to_fd.thresh,
|
||||
"nvkms-fence",
|
||||
@@ -282,7 +272,7 @@ NvBool nvkms_syncpt_op(
|
||||
|
||||
case NVKMS_SYNCPT_OP_READ_MINVAL:
|
||||
params->read_minval.minval =
|
||||
nvhost_syncpt_read_minval(nvhost_platform_device, params->read_minval.id);
|
||||
nvhost_syncpt_read_minval(pdev, params->read_minval.id);
|
||||
break;
|
||||
|
||||
}
|
||||
@@ -290,7 +280,7 @@ NvBool nvkms_syncpt_op(
|
||||
return NV_TRUE;
|
||||
}
|
||||
|
||||
#elif defined(NVKMS_NVHOST_SYNCPT_SUPPORTED) && defined(NV_LINUX_HOST1X_NEXT_H_PRESENT)
|
||||
#elif defined(NV_LINUX_HOST1X_NEXT_H_PRESENT) && defined(NV_LINUX_NVHOST_H_PRESENT)
|
||||
|
||||
#include <linux/dma-fence.h>
|
||||
#include <linux/file.h>
|
||||
@@ -306,20 +296,24 @@ NvBool nvkms_syncpt_op(
|
||||
|
||||
#include <linux/nvhost.h>
|
||||
|
||||
#undef NVKMS_SYNCPT_STUBS_NEEDED
|
||||
|
||||
NvBool nvkms_syncpt_op(
|
||||
enum NvKmsSyncPtOp op,
|
||||
NvKmsSyncPtOpParams *params)
|
||||
{
|
||||
struct host1x_syncpt *host1x_sp;
|
||||
struct platform_device *pdev;
|
||||
struct host1x *host1x;
|
||||
|
||||
if (nvhost_platform_device == NULL) {
|
||||
pdev = nvhost_get_default_device();
|
||||
if (pdev == NULL) {
|
||||
nvkms_log(NVKMS_LOG_LEVEL_ERROR, NVKMS_LOG_PREFIX,
|
||||
"Failed to get default nvhost device");
|
||||
return NV_FALSE;
|
||||
"Failed to get nvhost default pdev");
|
||||
return NV_FALSE;
|
||||
}
|
||||
|
||||
host1x = nvhost_get_host1x(nvhost_platform_device);
|
||||
host1x = nvhost_get_host1x(pdev);
|
||||
if (host1x == NULL) {
|
||||
nvkms_log(NVKMS_LOG_LEVEL_ERROR, NVKMS_LOG_PREFIX,
|
||||
"Failed to get host1x");
|
||||
@@ -433,7 +427,9 @@ NvBool nvkms_syncpt_op(
|
||||
|
||||
return NV_TRUE;
|
||||
}
|
||||
#else
|
||||
#endif
|
||||
|
||||
#ifdef NVKMS_SYNCPT_STUBS_NEEDED
|
||||
/* Unsupported STUB for nvkms_syncpt APIs */
|
||||
NvBool nvkms_syncpt_op(
|
||||
enum NvKmsSyncPtOp op,
|
||||
@@ -815,20 +811,6 @@ static void nvkms_resume(NvU32 gpuId)
|
||||
nvKmsKapiSuspendResume(NV_FALSE /* suspend */);
|
||||
}
|
||||
|
||||
static void nvkms_remove(NvU32 gpuId)
|
||||
{
|
||||
nvKmsKapiRemove(gpuId);
|
||||
|
||||
// Eventually, this function should also terminate all NVKMS clients and
|
||||
// free the NVDevEvoRec. Until that is implemented, all NVKMS clients must
|
||||
// be closed before a device is removed.
|
||||
}
|
||||
|
||||
static void nvkms_probe(const nv_gpu_info_t *gpu_info)
|
||||
{
|
||||
nvKmsKapiProbe(gpu_info);
|
||||
}
|
||||
|
||||
|
||||
/*************************************************************************
|
||||
* Interface with resman.
|
||||
@@ -837,9 +819,7 @@ static void nvkms_probe(const nv_gpu_info_t *gpu_info)
|
||||
static nvidia_modeset_rm_ops_t __rm_ops = { 0 };
|
||||
static nvidia_modeset_callbacks_t nvkms_rm_callbacks = {
|
||||
.suspend = nvkms_suspend,
|
||||
.resume = nvkms_resume,
|
||||
.remove = nvkms_remove,
|
||||
.probe = nvkms_probe,
|
||||
.resume = nvkms_resume
|
||||
};
|
||||
|
||||
static int nvkms_alloc_rm(void)
|
||||
@@ -2086,14 +2066,6 @@ static int __init nvkms_init(void)
|
||||
|
||||
atomic_set(&nvkms_alloc_called_count, 0);
|
||||
|
||||
#if defined(NVKMS_NVHOST_SYNCPT_SUPPORTED)
|
||||
/*
|
||||
* nvhost_get_default_device() might return NULL; don't check it
|
||||
* until we use it.
|
||||
*/
|
||||
nvhost_platform_device = nvhost_get_default_device();
|
||||
#endif
|
||||
|
||||
ret = nvkms_alloc_rm();
|
||||
|
||||
if (ret != 0) {
|
||||
@@ -2155,10 +2127,6 @@ static void __exit nvkms_exit(void)
|
||||
struct nvkms_timer_t *timer, *tmp_timer;
|
||||
unsigned long flags = 0;
|
||||
|
||||
#if defined(NVKMS_NVHOST_SYNCPT_SUPPORTED)
|
||||
platform_device_put(nvhost_platform_device);
|
||||
#endif
|
||||
|
||||
nvkms_proc_exit();
|
||||
|
||||
down(&nvkms_lock);
|
||||
|
||||
@@ -101,4 +101,3 @@ NV_CONFTEST_FUNCTION_COMPILE_TESTS += ktime_get_raw_ts64
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += acpi_video_backlight_use_native
|
||||
NV_CONFTEST_FUNCTION_COMPILE_TESTS += acpi_video_register_backlight
|
||||
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_present_timer_delete_sync
|
||||
NV_CONFTEST_SYMBOL_COMPILE_TESTS += is_export_symbol_gpl_platform_device_put
|
||||
|
||||
@@ -104,8 +104,6 @@ NvBool nvKmsKapiGetFunctionsTableInternal
|
||||
);
|
||||
|
||||
void nvKmsKapiSuspendResume(NvBool suspend);
|
||||
void nvKmsKapiRemove(NvU32 gpuId);
|
||||
void nvKmsKapiProbe(const nv_gpu_info_t *gpu_info);
|
||||
|
||||
NvBool nvKmsGetBacklight(NvU32 display_id, void *drv_priv, NvU32 *brightness);
|
||||
NvBool nvKmsSetBacklight(NvU32 display_id, void *drv_priv, NvU32 brightness);
|
||||
|
||||
@@ -75,8 +75,6 @@ static const char *osMapClk[] = {
|
||||
[TEGRASOC_WHICH_CLK_SPPLL0_DIV10] = "sppll0_div10_clk",
|
||||
[TEGRASOC_WHICH_CLK_SPPLL0_DIV25] = "sppll0_div25_clk",
|
||||
[TEGRASOC_WHICH_CLK_SPPLL1_VCO] = "sppll1_vco_clk",
|
||||
[TEGRASOC_WHICH_CLK_SPPLL0] = "sppll0",
|
||||
[TEGRASOC_WHICH_CLK_SPPLL1] = "sppll1",
|
||||
[TEGRASOC_WHICH_CLK_VPLL0_REF] = "vpll0_ref_clk",
|
||||
[TEGRASOC_WHICH_CLK_VPLL0] = "vpll0_clk",
|
||||
[TEGRASOC_WHICH_CLK_VPLL1] = "vpll1_clk",
|
||||
@@ -161,10 +159,7 @@ static const char *osMapClk[] = {
|
||||
[TEGRASOC_WHICH_CLK_AZA_BIT] = "aza_bit_clk",
|
||||
[TEGRASOC_WHICH_CLK_MIPI_CAL] = "mipi_cal_clk",
|
||||
[TEGRASOC_WHICH_CLK_UART_FST_MIPI_CAL] = "uart_fst_mipi_cal_clk",
|
||||
[TEGRASOC_WHICH_CLK_SOR0_DIV] = "sor0_div",
|
||||
[TEGRASOC_WHICH_CLK_SOR1_DIV] = "sor1_div",
|
||||
[TEGRASOC_WHICH_CLK_SOR2_DIV] = "sor2_div",
|
||||
[TEGRASOC_WHICH_CLK_SOR3_DIV] = "sor3_div",
|
||||
[TEGRASOC_WHICH_CLK_SOR0_DIV] = "sor0_div_clk",
|
||||
[TEGRASOC_WHICH_CLK_DISP_ROOT] = "disp_root",
|
||||
[TEGRASOC_WHICH_CLK_HUB_ROOT] = "hub_root",
|
||||
[TEGRASOC_WHICH_CLK_PLLA_DISP] = "plla_disp",
|
||||
@@ -247,6 +242,7 @@ NV_STATUS NV_API_CALL nv_clk_get_handles(
|
||||
if (j == TEGRASOC_WHICH_CLK_MAX)
|
||||
{
|
||||
nv_printf(NV_DBG_ERRORS,"NVRM: nv_clk_get_handles, failed to find TEGRA_SOC_WHICH_CLK for %s\n", clks[i].id);
|
||||
return NV_ERR_OBJECT_NOT_FOUND;
|
||||
}
|
||||
}
|
||||
#else
|
||||
|
||||
@@ -60,62 +60,6 @@
|
||||
#define ICC_SUPPORT_FUNCTIONS_PRESENT \
|
||||
defined(NV_DT_BINDINGS_INTERCONNECT_TEGRA_ICC_ID_H_PRESENT)
|
||||
|
||||
/*!
|
||||
* @brief Returns IMP-relevant data passed by UEFI GOP Driver
|
||||
*
|
||||
* @param[in] nv Per GPU Linux state
|
||||
* @param[out] iso_bw_kbps ISO BW set by UEFI
|
||||
* @param[out] floor_bw_kbps DRAM Floor BW set by UEFI
|
||||
*
|
||||
* @returns NV_OK if successful,
|
||||
* NV_ERR_GENERIC if there is an error in parsing DT,
|
||||
* NV_ERR_NOT_SUPPORTED if the functionality is not available.
|
||||
*/
|
||||
NV_STATUS NV_API_CALL
|
||||
nv_imp_get_uefi_data
|
||||
(
|
||||
nv_state_t *nv,
|
||||
NvU32 *iso_bw_kbps,
|
||||
NvU32 *floor_bw_kbps
|
||||
)
|
||||
{
|
||||
nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv);
|
||||
NV_STATUS status = NV_OK;
|
||||
NvU32 value = 0;
|
||||
int ret = 0;
|
||||
|
||||
*iso_bw_kbps = 0;
|
||||
*floor_bw_kbps = 0;
|
||||
#if NV_SUPPORTS_PLATFORM_DISPLAY_DEVICE
|
||||
ret = of_property_read_u32(nvl->dev->of_node, "nvidia,iso-bandwidth-kbps", &value);
|
||||
if (ret != 0)
|
||||
{
|
||||
nv_printf(NV_DBG_ERRORS, "NVRM: Unable to read nvidia,iso-bandwidth-kbps\n");
|
||||
status = NV_ERR_GENERIC;
|
||||
goto done;
|
||||
}
|
||||
else
|
||||
{
|
||||
*iso_bw_kbps = value;
|
||||
}
|
||||
|
||||
ret = of_property_read_u32(nvl->dev->of_node, "nvidia,dram-floor-kbps", &value);
|
||||
if (ret != 0)
|
||||
{
|
||||
nv_printf(NV_DBG_ERRORS, "NVRM: Unable to read nvidia,dram-floor-kbps\n");
|
||||
status = NV_ERR_GENERIC;
|
||||
goto done;
|
||||
}
|
||||
else
|
||||
{
|
||||
*floor_bw_kbps = value;
|
||||
}
|
||||
#endif
|
||||
|
||||
done:
|
||||
return status;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Returns IMP-relevant data collected from other modules
|
||||
*
|
||||
|
||||
@@ -71,40 +71,6 @@ void nvidia_modeset_resume(NvU32 gpuId)
|
||||
}
|
||||
}
|
||||
|
||||
void nvidia_modeset_remove(NvU32 gpuId)
|
||||
{
|
||||
if (nv_modeset_callbacks && nv_modeset_callbacks->remove)
|
||||
{
|
||||
nv_modeset_callbacks->remove(gpuId);
|
||||
}
|
||||
}
|
||||
|
||||
static void nvidia_modeset_get_gpu_info(nv_gpu_info_t *gpu_info,
|
||||
const nv_linux_state_t *nvl)
|
||||
{
|
||||
nv_state_t *nv = NV_STATE_PTR(nvl);
|
||||
|
||||
gpu_info->gpu_id = nv->gpu_id;
|
||||
|
||||
gpu_info->pci_info.domain = nv->pci_info.domain;
|
||||
gpu_info->pci_info.bus = nv->pci_info.bus;
|
||||
gpu_info->pci_info.slot = nv->pci_info.slot;
|
||||
gpu_info->pci_info.function = nv->pci_info.function;
|
||||
|
||||
gpu_info->os_device_ptr = nvl->dev;
|
||||
}
|
||||
|
||||
void nvidia_modeset_probe(const nv_linux_state_t *nvl)
|
||||
{
|
||||
if (nv_modeset_callbacks && nv_modeset_callbacks->probe)
|
||||
{
|
||||
nv_gpu_info_t gpu_info;
|
||||
|
||||
nvidia_modeset_get_gpu_info(&gpu_info, nvl);
|
||||
nv_modeset_callbacks->probe(&gpu_info);
|
||||
}
|
||||
}
|
||||
|
||||
static NvU32 nvidia_modeset_enumerate_gpus(nv_gpu_info_t *gpu_info)
|
||||
{
|
||||
nv_linux_state_t *nvl;
|
||||
@@ -116,6 +82,8 @@ static NvU32 nvidia_modeset_enumerate_gpus(nv_gpu_info_t *gpu_info)
|
||||
|
||||
for (nvl = nv_linux_devices; nvl != NULL; nvl = nvl->next)
|
||||
{
|
||||
nv_state_t *nv = NV_STATE_PTR(nvl);
|
||||
|
||||
/*
|
||||
* The gpu_info[] array has NV_MAX_GPUS elements. Fail if there
|
||||
* are more GPUs than that.
|
||||
@@ -127,7 +95,15 @@ static NvU32 nvidia_modeset_enumerate_gpus(nv_gpu_info_t *gpu_info)
|
||||
break;
|
||||
}
|
||||
|
||||
nvidia_modeset_get_gpu_info(&gpu_info[count], nvl);
|
||||
gpu_info[count].gpu_id = nv->gpu_id;
|
||||
|
||||
gpu_info[count].pci_info.domain = nv->pci_info.domain;
|
||||
gpu_info[count].pci_info.bus = nv->pci_info.bus;
|
||||
gpu_info[count].pci_info.slot = nv->pci_info.slot;
|
||||
gpu_info[count].pci_info.function = nv->pci_info.function;
|
||||
|
||||
gpu_info[count].os_device_ptr = nvl->dev;
|
||||
|
||||
count++;
|
||||
}
|
||||
|
||||
|
||||
@@ -604,19 +604,19 @@ static const struct nv_pci_tegra_devfreq_data gb10b_tegra_devfreq_table[] = {
|
||||
{
|
||||
.clk_name = "gpc0clk",
|
||||
.icc_name = "gpu-write",
|
||||
.gpc_fuse_field = BIT(0),
|
||||
.gpc_fuse_field = BIT(3),
|
||||
.devfreq_clk = TEGRASOC_DEVFREQ_CLK_GPC,
|
||||
},
|
||||
{
|
||||
.clk_name = "gpc1clk",
|
||||
.icc_name = "gpu-write",
|
||||
.gpc_fuse_field = BIT(1),
|
||||
.gpc_fuse_field = BIT(4),
|
||||
.devfreq_clk = TEGRASOC_DEVFREQ_CLK_GPC,
|
||||
},
|
||||
{
|
||||
.clk_name = "gpc2clk",
|
||||
.icc_name = "gpu-write",
|
||||
.gpc_fuse_field = BIT(2),
|
||||
.gpc_fuse_field = BIT(5),
|
||||
.devfreq_clk = TEGRASOC_DEVFREQ_CLK_GPC,
|
||||
},
|
||||
{
|
||||
@@ -651,11 +651,17 @@ nv_pci_gb10b_devfreq_target(struct device *dev, unsigned long *freq, u32 flags)
|
||||
u32 kBps;
|
||||
#endif
|
||||
|
||||
/*
|
||||
* If the device is suspended, skip the frequency scaling
|
||||
* because the clocks may be unavailable.
|
||||
* Otherwise, set the clocks to the target frequency.
|
||||
*/
|
||||
//
|
||||
// When GPU is suspended(railgated), the PM runtime suspend callback should
|
||||
// suspend all devfreq devices, and devfreq cycle should not be triggered.
|
||||
//
|
||||
// However, users are still able to change the devfreq governor from the
|
||||
// sysfs interface and indirectly invoke the update_devfreq function, which
|
||||
// will further call the target callback function.
|
||||
//
|
||||
// Early stop the process here before clk_set_rate/clk_get_rate, since these
|
||||
// calls served by BPMP will awake the GPU.
|
||||
//
|
||||
if (pm_runtime_suspended(&pdev->dev))
|
||||
{
|
||||
return 0;
|
||||
@@ -732,22 +738,8 @@ nv_pci_tegra_devfreq_get_cur_freq(struct device *dev, unsigned long *freq)
|
||||
{
|
||||
struct nv_pci_tegra_devfreq_dev *tdev = to_tegra_devfreq_dev(dev);
|
||||
|
||||
//
|
||||
// When GPU is suspended(railgated), the PM runtime suspend callback should
|
||||
// suspend all devfreq devices, and devfreq cycle should not be triggered.
|
||||
//
|
||||
// However, users are still able to change the devfreq governor from the
|
||||
// sysfs interface and indirectly invoke the update_devfreq function, which
|
||||
// will further call the get_dev_status callback function.
|
||||
//
|
||||
if (pm_runtime_active(dev->parent))
|
||||
{
|
||||
*freq = clk_get_rate(tdev->clk);
|
||||
}
|
||||
else
|
||||
{
|
||||
*freq = tdev->devfreq->previous_freq;
|
||||
}
|
||||
*freq = clk_get_rate(tdev->clk);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -765,19 +757,18 @@ nv_pci_tegra_devfreq_get_dev_status(struct device *dev,
|
||||
NV_STATUS status;
|
||||
|
||||
//
|
||||
// GPU can be under suspending/suspended/resuming state defined the runtime
|
||||
// PM (RPM) framework. When device is under either of these states, DVFS based
|
||||
// on GPU load information should be disabled.
|
||||
// When GPU is suspended(railgated), the PM runtime suspend callback should
|
||||
// suspend all devfreq devices, and devfreq cycle should not be triggered.
|
||||
//
|
||||
// Complete load-based DVFS cycle involve GPU load query through rmapi and
|
||||
// clock scaling through BPMP MRQ_CLK mailbox request, which will awake the
|
||||
// GPU and contradict the suspended state.
|
||||
// However, users are still able to change the devfreq governor from the
|
||||
// sysfs interface and indirectly invoke the update_devfreq function, which
|
||||
// will further call the get_dev_status callback function.
|
||||
//
|
||||
if (!pm_runtime_active(&pdev->dev))
|
||||
if (pm_runtime_suspended(&pdev->dev))
|
||||
{
|
||||
stat->total_time = 100;
|
||||
stat->busy_time = 0;
|
||||
stat->current_frequency = tdev->devfreq->previous_freq;
|
||||
stat->current_frequency = clk_get_rate(tdev->clk);
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -1045,6 +1036,10 @@ nv_pci_gb10b_add_devfreq_device(struct nv_pci_tegra_devfreq_dev *tdev)
|
||||
goto err_nv_pci_gb10b_add_devfreq_device_opp;
|
||||
}
|
||||
|
||||
#if defined(NV_DEVFREQ_HAS_SUSPEND_FREQ)
|
||||
tdev->devfreq->suspend_freq = tdev->devfreq->scaling_max_freq;
|
||||
#endif
|
||||
|
||||
#if NV_HAS_COOLING_SUPPORTED
|
||||
err = nv_pci_tegra_init_cooling_device(tdev);
|
||||
if (err)
|
||||
@@ -1189,6 +1184,7 @@ nv_pci_gb10b_register_devfreq(struct pci_dev *pdev)
|
||||
nvl->gpc_devfreq_dev->devfreq = NULL;
|
||||
goto error_slave_teardown;
|
||||
}
|
||||
|
||||
if (nvl->sys_devfreq_dev != NULL)
|
||||
{
|
||||
list_add_tail(&nvl->sys_devfreq_dev->gpc_cluster, &nvl->gpc_devfreq_dev->gpc_cluster);
|
||||
@@ -1210,6 +1206,7 @@ nv_pci_gb10b_register_devfreq(struct pci_dev *pdev)
|
||||
nvl->nvd_devfreq_dev->devfreq = NULL;
|
||||
goto error_slave_teardown;
|
||||
}
|
||||
|
||||
if (nvl->sys_devfreq_dev != NULL)
|
||||
{
|
||||
list_add_tail(&nvl->sys_devfreq_dev->nvd_cluster, &nvl->nvd_devfreq_dev->nvd_cluster);
|
||||
@@ -1262,10 +1259,6 @@ nv_pci_gb10b_suspend_devfreq(struct device *dev)
|
||||
|
||||
if (nvl->gpc_devfreq_dev != NULL && nvl->gpc_devfreq_dev->devfreq != NULL)
|
||||
{
|
||||
mutex_lock(&nvl->gpc_devfreq_dev->devfreq->lock);
|
||||
nvl->gpc_devfreq_dev->devfreq->suspend_freq = nvl->gpc_devfreq_dev->devfreq->previous_freq;
|
||||
mutex_unlock(&nvl->gpc_devfreq_dev->devfreq->lock);
|
||||
|
||||
err = devfreq_suspend_device(nvl->gpc_devfreq_dev->devfreq);
|
||||
if (err)
|
||||
{
|
||||
@@ -1282,10 +1275,6 @@ nv_pci_gb10b_suspend_devfreq(struct device *dev)
|
||||
|
||||
if (nvl->nvd_devfreq_dev != NULL && nvl->nvd_devfreq_dev->devfreq != NULL)
|
||||
{
|
||||
mutex_lock(&nvl->nvd_devfreq_dev->devfreq->lock);
|
||||
nvl->nvd_devfreq_dev->devfreq->suspend_freq = nvl->nvd_devfreq_dev->devfreq->previous_freq;
|
||||
mutex_unlock(&nvl->nvd_devfreq_dev->devfreq->lock);
|
||||
|
||||
err = devfreq_suspend_device(nvl->nvd_devfreq_dev->devfreq);
|
||||
if (err)
|
||||
{
|
||||
@@ -1317,17 +1306,6 @@ nv_pci_gb10b_resume_devfreq(struct device *dev)
|
||||
{
|
||||
return err;
|
||||
}
|
||||
/*
|
||||
* During GPU runtime suspended state, switching the devfreq governor
|
||||
* which doesn't poll for GPU utilization could lead to devfreq
|
||||
* frequency not being updated after runtime resume.
|
||||
*
|
||||
* Manually trigger the devfreq update here to ensure the
|
||||
* frequency is compliant with the devfreq governor.
|
||||
*/
|
||||
mutex_lock(&nvl->gpc_devfreq_dev->devfreq->lock);
|
||||
update_devfreq(nvl->gpc_devfreq_dev->devfreq);
|
||||
mutex_unlock(&nvl->gpc_devfreq_dev->devfreq->lock);
|
||||
}
|
||||
|
||||
if (nvl->nvd_devfreq_dev != NULL && nvl->nvd_devfreq_dev->devfreq != NULL)
|
||||
@@ -1337,9 +1315,6 @@ nv_pci_gb10b_resume_devfreq(struct device *dev)
|
||||
{
|
||||
return err;
|
||||
}
|
||||
mutex_lock(&nvl->nvd_devfreq_dev->devfreq->lock);
|
||||
update_devfreq(nvl->nvd_devfreq_dev->devfreq);
|
||||
mutex_unlock(&nvl->nvd_devfreq_dev->devfreq->lock);
|
||||
}
|
||||
|
||||
return err;
|
||||
@@ -1552,39 +1527,6 @@ nv_pci_get_tegra_igpu_data(struct pci_dev *pdev)
|
||||
return NULL;
|
||||
}
|
||||
|
||||
void nv_pci_tegra_boost_sys_uproc(struct device *dev)
|
||||
{
|
||||
#if defined(CONFIG_PM_DEVFREQ)
|
||||
nv_linux_state_t *nvl = pci_get_drvdata(to_pci_dev(dev));
|
||||
const struct nv_pci_tegra_devfreq_data *tdata;
|
||||
struct clk *clk = NULL;
|
||||
unsigned long max_freq;
|
||||
int i;
|
||||
|
||||
for (i = 0; i < nvl->devfreq_table_size; i++)
|
||||
{
|
||||
tdata = &nvl->devfreq_table[i];
|
||||
|
||||
/*
|
||||
* Don't boost the GPC, NVD clocks but only the uprocclk
|
||||
* and sysclk. This saves power consumption of GPU rail
|
||||
* and reduces impact to GPU suspend/resume latency.
|
||||
*/
|
||||
if (strstr(tdata->clk_name, "uproc") || strstr(tdata->clk_name, "sys"))
|
||||
{
|
||||
clk = devm_clk_get(dev, tdata->clk_name);
|
||||
}
|
||||
else
|
||||
{
|
||||
continue;
|
||||
}
|
||||
|
||||
max_freq = clk_round_rate(clk, ULONG_MAX);
|
||||
clk_set_rate(clk, max_freq);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
|
||||
static int
|
||||
nv_pci_tegra_register_devfreq(struct pci_dev *pdev)
|
||||
{
|
||||
@@ -2119,8 +2061,6 @@ nv_pci_probe
|
||||
|
||||
nv_kmem_cache_free_stack(sp);
|
||||
|
||||
nvidia_modeset_probe(nvl);
|
||||
|
||||
return 0;
|
||||
|
||||
goto err_free_all;
|
||||
@@ -2155,7 +2095,8 @@ failed:
|
||||
return -1;
|
||||
}
|
||||
|
||||
static void nv_pci_remove_helper(struct pci_dev *pci_dev, bool block_if_gpu_in_use)
|
||||
static void
|
||||
nv_pci_remove(struct pci_dev *pci_dev)
|
||||
{
|
||||
nv_linux_state_t *nvl = NULL;
|
||||
nv_state_t *nv;
|
||||
@@ -2163,6 +2104,9 @@ static void nv_pci_remove_helper(struct pci_dev *pci_dev, bool block_if_gpu_in_u
|
||||
NvU8 regs_bar_index = nv_bar_index_to_os_bar_index(pci_dev,
|
||||
NV_GPU_BAR_INDEX_REGS);
|
||||
|
||||
nv_printf(NV_DBG_SETUP, "NVRM: removing GPU %04x:%02x:%02x.%x\n",
|
||||
NV_PCI_DOMAIN_NUMBER(pci_dev), NV_PCI_BUS_NUMBER(pci_dev),
|
||||
NV_PCI_SLOT_NUMBER(pci_dev), PCI_FUNC(pci_dev->devfn));
|
||||
|
||||
#ifdef NV_PCI_SRIOV_SUPPORT
|
||||
if (pci_dev->is_virtfn)
|
||||
@@ -2175,9 +2119,15 @@ static void nv_pci_remove_helper(struct pci_dev *pci_dev, bool block_if_gpu_in_u
|
||||
}
|
||||
#endif /* NV_PCI_SRIOV_SUPPORT */
|
||||
|
||||
if (nv_kmem_cache_alloc_stack(&sp) != 0)
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
nvl = pci_get_drvdata(pci_dev);
|
||||
if (!nvl || (nvl->pci_dev != pci_dev))
|
||||
{
|
||||
nv_kmem_cache_free_stack(sp);
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -2208,25 +2158,8 @@ static void nv_pci_remove_helper(struct pci_dev *pci_dev, bool block_if_gpu_in_u
|
||||
*/
|
||||
nv_linux_stop_open_q(nvl);
|
||||
|
||||
nvidia_modeset_remove(nv->gpu_id);
|
||||
|
||||
LOCK_NV_LINUX_DEVICES();
|
||||
down(&nvl->ldata_lock);
|
||||
|
||||
if (!block_if_gpu_in_use && (NV_ATOMIC_READ(nvl->usage_count) != 0))
|
||||
{
|
||||
up(&nvl->ldata_lock);
|
||||
UNLOCK_NV_LINUX_DEVICES();
|
||||
return;
|
||||
}
|
||||
|
||||
if (nv_kmem_cache_alloc_stack(&sp) != 0)
|
||||
{
|
||||
up(&nvl->ldata_lock);
|
||||
UNLOCK_NV_LINUX_DEVICES();
|
||||
return;
|
||||
}
|
||||
|
||||
nv->flags |= NV_FLAG_PCI_REMOVE_IN_PROGRESS;
|
||||
|
||||
rm_notify_gpu_removal(sp, nv);
|
||||
@@ -2249,6 +2182,7 @@ static void nv_pci_remove_helper(struct pci_dev *pci_dev, bool block_if_gpu_in_u
|
||||
*/
|
||||
while (NV_ATOMIC_READ(nvl->usage_count) != 0)
|
||||
{
|
||||
|
||||
/*
|
||||
* While waiting, release the locks so that other threads can make
|
||||
* forward progress.
|
||||
@@ -2267,7 +2201,7 @@ static void nv_pci_remove_helper(struct pci_dev *pci_dev, bool block_if_gpu_in_u
|
||||
nv_printf(NV_DBG_ERRORS,
|
||||
"NVRM: Failed removal of device %04x:%02x:%02x.%x!\n",
|
||||
NV_PCI_DOMAIN_NUMBER(pci_dev), NV_PCI_BUS_NUMBER(pci_dev),
|
||||
NV_PCI_SLOT_NUMBER(pci_dev), PCI_FUNC(pci_dev->devfn));
|
||||
NV_PCI_SLOT_NUMBER(pci_dev), PCI_FUNC(pci_dev->devfn));
|
||||
WARN_ON(1);
|
||||
goto done;
|
||||
}
|
||||
@@ -2358,44 +2292,26 @@ done:
|
||||
nv_kmem_cache_free_stack(sp);
|
||||
}
|
||||
|
||||
static void
|
||||
nv_pci_remove(struct pci_dev *pci_dev)
|
||||
{
|
||||
|
||||
nv_printf(NV_DBG_SETUP, "NVRM: removing GPU %04x:%02x:%02x.%x\n",
|
||||
NV_PCI_DOMAIN_NUMBER(pci_dev), NV_PCI_BUS_NUMBER(pci_dev),
|
||||
NV_PCI_SLOT_NUMBER(pci_dev), PCI_FUNC(pci_dev->devfn));
|
||||
|
||||
nv_pci_remove_helper(pci_dev, true);
|
||||
}
|
||||
|
||||
static void
|
||||
nv_pci_shutdown(struct pci_dev *pci_dev)
|
||||
{
|
||||
nv_linux_state_t *nvl = pci_get_drvdata(pci_dev);
|
||||
|
||||
if (!nvl || (nvl->pci_dev != pci_dev))
|
||||
{
|
||||
return;
|
||||
}
|
||||
|
||||
if (nvl->is_forced_shutdown)
|
||||
if ((nvl != NULL) && nvl->is_forced_shutdown)
|
||||
{
|
||||
nvl->is_forced_shutdown = NV_FALSE;
|
||||
return;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_PM_DEVFREQ)
|
||||
nv_pci_tegra_unregister_devfreq(pci_dev);
|
||||
#endif
|
||||
|
||||
nv_pci_remove_helper(pci_dev, false);
|
||||
|
||||
if (pci_get_drvdata(pci_dev) != NULL)
|
||||
if (nvl != NULL)
|
||||
{
|
||||
nvl->nv_state.is_shutdown = NV_TRUE;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_PM_DEVFREQ)
|
||||
nv_pci_tegra_unregister_devfreq(pci_dev);
|
||||
#endif
|
||||
|
||||
/* pci_clear_master is not defined for !CONFIG_PCI */
|
||||
#ifdef CONFIG_PCI
|
||||
pci_clear_master(pci_dev);
|
||||
|
||||
@@ -25,7 +25,6 @@
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/of_address.h>
|
||||
|
||||
#include "nv-platform.h"
|
||||
#include "nv-linux.h"
|
||||
@@ -564,6 +563,26 @@ NV_STATUS NV_API_CALL nv_soc_device_reset(nv_state_t *nv)
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
|
||||
if (nvl->hdacodec_reset != NULL)
|
||||
{
|
||||
/*
|
||||
* HDACODEC reset control is shared between display driver and audio driver.
|
||||
* Since reset_control_reset toggles the reset signal, we prefer to use
|
||||
* reset_control_deassert. Additionally, since Audio driver uses
|
||||
* reset_control_bulk_deassert() which internally calls reset_control_deassert,
|
||||
* we must use reset_control_deassert, because consumers must not use
|
||||
* reset_control_reset on shared reset lines when reset_control_deassert has
|
||||
* been used.
|
||||
*/
|
||||
rc = reset_control_deassert(nvl->hdacodec_reset);
|
||||
if (rc != 0)
|
||||
{
|
||||
status = NV_ERR_GENERIC;
|
||||
nv_printf(NV_DBG_ERRORS, "NVRM: hdacodec reset_control_deassert failed, rc: %d\n", rc);
|
||||
goto out;
|
||||
}
|
||||
}
|
||||
}
|
||||
out:
|
||||
return status;
|
||||
@@ -692,60 +711,6 @@ fail:
|
||||
return status;
|
||||
}
|
||||
|
||||
#define DISP_CLK_NUM_PARENTS 2
|
||||
// This function gets called only for Tegra
|
||||
static NV_STATUS nv_platform_get_disp_clocks_max_rate(struct platform_device *plat_dev,
|
||||
nv_state_t *nv)
|
||||
{
|
||||
struct device_node *np = plat_dev->dev.of_node;
|
||||
u32 value = 0;
|
||||
u32 disp_clk_rates[DISP_CLK_NUM_PARENTS];
|
||||
NV_STATUS status = NV_OK;
|
||||
int ret = 0;
|
||||
|
||||
nv->clocks.max_dispclk_rate_using_disppllkhz = 0;
|
||||
nv->clocks.max_dispclk_rate_using_sppll0clkoutakhz = 0;
|
||||
nv->clocks.max_hubclk_rate_using_sppll0clkoutbkhz = 0;
|
||||
|
||||
/* Parse disp clock max rates for each possible parent passed by UEFI */
|
||||
ret = of_property_read_u32_array(np, "nvidia,max-disp-clk-rate-khz", disp_clk_rates, DISP_CLK_NUM_PARENTS);
|
||||
if (ret == 0)
|
||||
{
|
||||
nv->clocks.max_dispclk_rate_using_disppllkhz = disp_clk_rates[0];
|
||||
nv->clocks.max_dispclk_rate_using_sppll0clkoutakhz = disp_clk_rates[1];
|
||||
}
|
||||
else if (ret == -EINVAL)
|
||||
{
|
||||
nv_printf(NV_DBG_INFO, "NVRM: nv_platform_get_disp_clocks_max_rate, nvidia,max-disp-clk-rate-khz not specified under display node\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
nv_printf(NV_DBG_ERRORS, "NVRM: nv_platform_get_disp_clocks_max_rate, nvidia,max-disp-clk-rate-khz has invalid value\n");
|
||||
status = NV_ERR_GENERIC;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
/* Parse hub clock max rate for its parent passed by UEFI */
|
||||
ret = of_property_read_u32(np, "nvidia,max-hub-clk-rate-khz", &value);
|
||||
if (ret == 0)
|
||||
{
|
||||
nv->clocks.max_hubclk_rate_using_sppll0clkoutbkhz = value;
|
||||
}
|
||||
else if (ret == -EINVAL)
|
||||
{
|
||||
nv_printf(NV_DBG_INFO, "NVRM: nv_platform_get_disp_clocks_max_rate, nvidia,max-hub-clk-rate-khz not specified under display node\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
nv_printf(NV_DBG_ERRORS, "NVRM: nv_platform_get_disp_clocks_max_rate, nvidia,max-hub-clk-rate-khz has invalid value\n");
|
||||
status = NV_ERR_GENERIC;
|
||||
goto fail;
|
||||
}
|
||||
|
||||
fail:
|
||||
return status;
|
||||
}
|
||||
|
||||
static int nv_platform_register_mapping_devs(struct platform_device *plat_dev,
|
||||
nv_state_t *nv)
|
||||
{
|
||||
@@ -944,14 +909,6 @@ static int nv_platform_device_display_probe(struct platform_device *plat_dev)
|
||||
goto err_release_mem_region_regs;
|
||||
}
|
||||
|
||||
// Parse Display Clocks max rates passed by UEFI through DT
|
||||
status = nv_platform_get_disp_clocks_max_rate(plat_dev, nv);
|
||||
if (status != NV_OK)
|
||||
{
|
||||
nv_printf(NV_DBG_ERRORS, "NVRM: nv_platform_device_display_probe: parsing display clocks max rates failed\n");
|
||||
goto err_release_mem_region_regs;
|
||||
}
|
||||
|
||||
rc = nv_platform_register_mapping_devs(plat_dev, nv);
|
||||
if (rc != 0)
|
||||
{
|
||||
@@ -1206,6 +1163,26 @@ static int nv_platform_device_display_probe(struct platform_device *plat_dev)
|
||||
nv_printf(NV_DBG_ERRORS, "NVRM: mipi_cal devm_reset_control_get failed, err: %ld\n", PTR_ERR(nvl->mipi_cal_reset));
|
||||
nvl->mipi_cal_reset = NULL;
|
||||
}
|
||||
|
||||
/*
|
||||
* In T23x, HDACODEC is part of the same power domain as NVDisplay, so
|
||||
* unpowergating the DISP domain also results in the HDACODEC reset
|
||||
* being de-asserted. However, in T26x, HDACODEC is being moved
|
||||
* out to a separate always-on domain, so we need to explicitly de-assert
|
||||
* the HDACODEC reset in RM. We don't have good way to differentiate
|
||||
* between T23x vs T264x at this place. So if there is failure to read
|
||||
* "hdacodec_reset" from DT silently ignore it for now. In long term we
|
||||
* should really look into using the devm_reset_control_bulk* APIs and
|
||||
* see if this is feasible if we're ultimately just getting and
|
||||
* asserting/deasserting all of the resets specified in DT together all of
|
||||
* the time, and if there's no scenarios in which we need to only use a
|
||||
* specific set of reset(s) at a given point.
|
||||
*/
|
||||
nvl->hdacodec_reset = devm_reset_control_get(nvl->dev, "hdacodec_reset");
|
||||
if (IS_ERR(nvl->hdacodec_reset))
|
||||
{
|
||||
nvl->hdacodec_reset = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
status = nv_imp_icc_get(nv);
|
||||
@@ -1517,18 +1494,6 @@ static int nv_platform_device_remove_wrapper(struct platform_device *pdev)
|
||||
}
|
||||
#endif
|
||||
|
||||
static void nv_platform_device_shutdown(struct platform_device *pdev)
|
||||
{
|
||||
nv_linux_state_t *nvl = platform_get_drvdata(pdev);
|
||||
|
||||
if (nvl != NULL && !nvl->is_forced_shutdown)
|
||||
{
|
||||
nv_state_t *nv = NV_STATE_PTR(nvl);
|
||||
|
||||
nvidia_modeset_remove(nv->gpu_id);
|
||||
}
|
||||
}
|
||||
|
||||
const struct of_device_id nv_platform_device_table[] =
|
||||
{
|
||||
{ .compatible = "nvidia,tegra234-display",},
|
||||
@@ -1553,7 +1518,6 @@ struct platform_driver nv_platform_driver = {
|
||||
},
|
||||
.probe = nv_platform_device_probe,
|
||||
.remove = nv_platform_device_remove_wrapper,
|
||||
.shutdown = nv_platform_device_shutdown,
|
||||
};
|
||||
|
||||
int nv_platform_count_devices(void)
|
||||
@@ -1734,175 +1698,3 @@ NvBool nv_get_hdcp_enabled(nv_state_t *nv)
|
||||
|
||||
return NV_FALSE;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_OF)
|
||||
|
||||
// Global framebuffer cache structure
|
||||
typedef struct {
|
||||
NvBool dt_parsed;
|
||||
NvBool dt_success;
|
||||
NvU64 physical_address;
|
||||
NvU32 fb_width;
|
||||
NvU32 fb_height;
|
||||
NvU32 fb_depth;
|
||||
NvU32 fb_pitch;
|
||||
NvU64 fb_size;
|
||||
} screen_info_cache_t;
|
||||
|
||||
// Global framebuffer cache instance
|
||||
static screen_info_cache_t g_screen_info_cache = {
|
||||
.dt_parsed = NV_FALSE,
|
||||
.dt_success = NV_FALSE,
|
||||
.physical_address = 0,
|
||||
.fb_width = 0,
|
||||
.fb_height = 0,
|
||||
.fb_depth = 0,
|
||||
.fb_pitch = 0,
|
||||
.fb_size = 0
|
||||
};
|
||||
|
||||
NV_STATUS nv_platform_get_screen_info_dt(
|
||||
NvU64 *pPhysicalAddress,
|
||||
NvU32 *pFbWidth,
|
||||
NvU32 *pFbHeight,
|
||||
NvU32 *pFbDepth,
|
||||
NvU32 *pFbPitch,
|
||||
NvU64 *pFbSize
|
||||
)
|
||||
{
|
||||
//
|
||||
// Try to get the framebuffer information from device tree simple-framebuffer node.
|
||||
// This is particularly useful for Tegra platforms where the bootloader
|
||||
// sets up a simple framebuffer via device tree.
|
||||
//
|
||||
|
||||
struct device_node *fb_node;
|
||||
struct device_node *mem_node;
|
||||
struct resource res;
|
||||
u32 width, height, stride;
|
||||
const char *format;
|
||||
int ret;
|
||||
|
||||
if (g_screen_info_cache.dt_parsed)
|
||||
{
|
||||
if (g_screen_info_cache.dt_success)
|
||||
{
|
||||
*pPhysicalAddress = g_screen_info_cache.physical_address;
|
||||
*pFbWidth = g_screen_info_cache.fb_width;
|
||||
*pFbHeight = g_screen_info_cache.fb_height;
|
||||
*pFbDepth = g_screen_info_cache.fb_depth;
|
||||
*pFbPitch = g_screen_info_cache.fb_pitch;
|
||||
*pFbSize = g_screen_info_cache.fb_size;
|
||||
return NV_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return NV_ERR_NOT_SUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
g_screen_info_cache.dt_parsed = NV_TRUE;
|
||||
|
||||
// Look for simple-framebuffer node in chosen
|
||||
fb_node = of_find_node_by_path("/chosen/framebuffer");
|
||||
if (fb_node == NULL)
|
||||
{
|
||||
// Alternative path for some platforms
|
||||
for_each_compatible_node(fb_node, NULL, "simple-framebuffer")
|
||||
{
|
||||
nv_printf(NV_DBG_INFO, "NVRM: Found simple-framebuffer compatible node: %s\n",
|
||||
fb_node->full_name ? fb_node->full_name : "unknown");
|
||||
if (of_property_read_bool(fb_node, "status") &&
|
||||
!strcmp(of_get_property(fb_node, "status", NULL), "disabled"))
|
||||
{
|
||||
nv_printf(NV_DBG_INFO, "NVRM: Skipping disabled framebuffer node\n");
|
||||
of_node_put(fb_node);
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
nv_printf(NV_DBG_INFO, "NVRM: Found framebuffer node in /chosen/framebuffer\n");
|
||||
}
|
||||
|
||||
if (fb_node != NULL)
|
||||
{
|
||||
nv_printf(NV_DBG_INFO, "NVRM: Processing framebuffer node: %s\n",
|
||||
fb_node->full_name ? fb_node->full_name : "unknown");
|
||||
// Get memory region
|
||||
mem_node = of_parse_phandle(fb_node, "memory-region", 0);
|
||||
if (mem_node != NULL)
|
||||
{
|
||||
nv_printf(NV_DBG_INFO, "NVRM: Found memory-region: %s\n",
|
||||
mem_node->full_name ? mem_node->full_name : "unknown");
|
||||
ret = of_address_to_resource(mem_node, 0, &res);
|
||||
of_node_put(mem_node);
|
||||
if (ret == 0)
|
||||
{
|
||||
nv_printf(NV_DBG_INFO, "NVRM: Memory region: start=0x%llx, size=0x%llx\n",
|
||||
(NvU64)res.start, (NvU64)resource_size(&res));
|
||||
// Get display parameters
|
||||
if (!of_property_read_u32(fb_node, "width", &width) &&
|
||||
!of_property_read_u32(fb_node, "height", &height) &&
|
||||
!of_property_read_u32(fb_node, "stride", &stride) &&
|
||||
!of_property_read_string(fb_node, "format", &format))
|
||||
{
|
||||
// Calculate depth from format
|
||||
u32 depth = 32; // default
|
||||
if (!strcmp(format, "r5g6b5") || !strcmp(format, "r5g5b5a1") ||
|
||||
!strcmp(format, "x1r5g5b5") || !strcmp(format, "a1r5g5b5"))
|
||||
{
|
||||
depth = 16;
|
||||
}
|
||||
else if (!strcmp(format, "r8g8b8"))
|
||||
{
|
||||
depth = 24;
|
||||
}
|
||||
nv_printf(NV_DBG_INFO, "NVRM: Found simple-framebuffer in DT: %dx%d@%d, addr=0x%llx, size=0x%llx, stride=%d, format=%s\n",
|
||||
width, height, depth, (NvU64)res.start, (NvU64)resource_size(&res), stride, format);
|
||||
|
||||
g_screen_info_cache.dt_success = NV_TRUE;
|
||||
|
||||
g_screen_info_cache.physical_address = res.start;
|
||||
g_screen_info_cache.fb_width = width;
|
||||
g_screen_info_cache.fb_height = height;
|
||||
g_screen_info_cache.fb_depth = depth;
|
||||
g_screen_info_cache.fb_pitch = stride;
|
||||
g_screen_info_cache.fb_size = resource_size(&res);
|
||||
|
||||
*pPhysicalAddress = g_screen_info_cache.physical_address;
|
||||
*pFbWidth = g_screen_info_cache.fb_width;
|
||||
*pFbHeight = g_screen_info_cache.fb_height;
|
||||
*pFbDepth = g_screen_info_cache.fb_depth;
|
||||
*pFbPitch = g_screen_info_cache.fb_pitch;
|
||||
*pFbSize = g_screen_info_cache.fb_size;
|
||||
|
||||
of_node_put(fb_node);
|
||||
return NV_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
nv_printf(NV_DBG_ERRORS, "NVRM: Failed to read display parameters from DT\n");
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
nv_printf(NV_DBG_ERRORS, "NVRM: Failed to convert memory region to resource: %d\n", ret);
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
nv_printf(NV_DBG_ERRORS, "NVRM: No memory-region property found\n");
|
||||
}
|
||||
of_node_put(fb_node);
|
||||
}
|
||||
else
|
||||
{
|
||||
nv_printf(NV_DBG_ERRORS, "NVRM: No simple-framebuffer node found - fb_node is NULL\n");
|
||||
}
|
||||
|
||||
return NV_ERR_NOT_SUPPORTED;
|
||||
}
|
||||
#endif // CONFIG_OF
|
||||
|
||||
@@ -278,12 +278,6 @@ static unsigned int nv_compute_gfp_mask(
|
||||
if (at->order > 0)
|
||||
gfp_mask |= __GFP_COMP;
|
||||
|
||||
if (at->flags.no_reclaim)
|
||||
{
|
||||
gfp_mask &= ~(__GFP_RETRY_MAYFAIL | __GFP_RECLAIM);
|
||||
gfp_mask |= __GFP_NORETRY;
|
||||
}
|
||||
|
||||
return gfp_mask;
|
||||
}
|
||||
|
||||
|
||||
@@ -3717,7 +3717,15 @@ void NV_API_CALL nv_free_kernel_mapping(
|
||||
|
||||
NV_STATUS NV_API_CALL nv_alloc_pages(
|
||||
nv_state_t *nv,
|
||||
nv_allocation_request_t *alloc_request
|
||||
NvU32 page_count,
|
||||
NvU64 page_size,
|
||||
NvBool contiguous,
|
||||
NvU32 cache_type,
|
||||
NvBool zeroed,
|
||||
NvBool unencrypted,
|
||||
NvS32 node_id,
|
||||
NvU64 *pte_array,
|
||||
void **priv_data
|
||||
)
|
||||
{
|
||||
nv_alloc_t *at;
|
||||
@@ -3726,16 +3734,6 @@ NV_STATUS NV_API_CALL nv_alloc_pages(
|
||||
NvBool will_remap = NV_FALSE;
|
||||
NvU32 i;
|
||||
struct device *dev = NULL;
|
||||
NvU32 page_count = alloc_request->count;
|
||||
NvU64 page_size = alloc_request->page_size;
|
||||
NvBool contiguous = alloc_request->alloc_type_contiguous;
|
||||
NvU32 cache_type = alloc_request->cache_type;
|
||||
NvBool zeroed = alloc_request->alloc_type_zeroed;
|
||||
NvBool unencrypted = alloc_request->unencrypted;
|
||||
NvBool no_reclaim = alloc_request->no_reclaim;
|
||||
NvS32 node_id = alloc_request->node_id;
|
||||
NvU64 *pte_array = alloc_request->pte_array;
|
||||
void **priv_data = alloc_request->private;
|
||||
|
||||
nv_printf(NV_DBG_MEMINFO, "NVRM: VM: nv_alloc_pages: %d pages, nodeid %d\n", page_count, node_id);
|
||||
nv_printf(NV_DBG_MEMINFO, "NVRM: VM: contig %d cache_type %d\n",
|
||||
@@ -3778,8 +3776,6 @@ NV_STATUS NV_API_CALL nv_alloc_pages(
|
||||
at->node_id = node_id;
|
||||
}
|
||||
|
||||
at->flags.no_reclaim = no_reclaim;
|
||||
|
||||
if (at->flags.contig)
|
||||
{
|
||||
status = nv_alloc_contig_pages(nv, at);
|
||||
@@ -4424,15 +4420,13 @@ nvidia_suspend(
|
||||
}
|
||||
nv = NV_STATE_PTR(nvl);
|
||||
|
||||
#if defined(NV_PM_RUNTIME_AVAILABLE) && defined(NV_PM_DOMAIN_AVAILABLE)
|
||||
#if defined(NV_PM_RUNTIME_AVAILABLE)
|
||||
/* Handle GenPD suspend sequence for Tegra PCI iGPU */
|
||||
if (dev_is_pci(dev) && nv->is_tegra_pci_igpu_rg_enabled)
|
||||
{
|
||||
/* Turn on the GPU power before saving PCI configuration */
|
||||
pm_runtime_forbid(dev);
|
||||
|
||||
dev_pm_genpd_suspend(dev);
|
||||
|
||||
/*
|
||||
* If a PCI device is attached to a GenPD power domain,
|
||||
* resume_early callback in PCI framework will not be
|
||||
@@ -4505,7 +4499,7 @@ nvidia_resume(
|
||||
{
|
||||
NV_STATUS status = NV_OK;
|
||||
struct pci_dev *pci_dev;
|
||||
#if defined(NV_PM_RUNTIME_AVAILABLE) && defined(NV_PM_DOMAIN_AVAILABLE)
|
||||
#if defined(NV_PM_RUNTIME_AVAILABLE)
|
||||
struct pci_bus *bus;
|
||||
struct pci_host_bridge *bridge;
|
||||
struct device *ctrl;
|
||||
@@ -4524,7 +4518,7 @@ nvidia_resume(
|
||||
}
|
||||
nv = NV_STATE_PTR(nvl);
|
||||
|
||||
#if defined(NV_PM_RUNTIME_AVAILABLE) && defined(NV_PM_DOMAIN_AVAILABLE)
|
||||
#if defined(NV_PM_RUNTIME_AVAILABLE)
|
||||
/* Handle GenPD resume sequence for Tegra PCI iGPU */
|
||||
if (dev_is_pci(dev) && nv->is_tegra_pci_igpu_rg_enabled)
|
||||
{
|
||||
@@ -4545,8 +4539,6 @@ nvidia_resume(
|
||||
"NVRM: restore GPU pm_domain after suspend\n");
|
||||
dev->pm_domain = ctrl->pm_domain;
|
||||
|
||||
dev_pm_genpd_resume(dev);
|
||||
|
||||
pm_runtime_allow(dev);
|
||||
}
|
||||
#endif
|
||||
@@ -4920,8 +4912,6 @@ int nv_pmops_runtime_suspend(
|
||||
}
|
||||
#endif
|
||||
|
||||
nv_pci_tegra_boost_sys_uproc(dev);
|
||||
|
||||
err = nvidia_transition_dynamic_power(dev, NV_TRUE);
|
||||
if (err)
|
||||
{
|
||||
@@ -4958,8 +4948,6 @@ int nv_pmops_runtime_resume(
|
||||
#endif
|
||||
int err;
|
||||
|
||||
nv_pci_tegra_boost_sys_uproc(dev);
|
||||
|
||||
err = nvidia_transition_dynamic_power(dev, NV_FALSE);
|
||||
if (err)
|
||||
{
|
||||
@@ -5786,7 +5774,7 @@ NvBool NV_API_CALL nv_pci_tegra_register_power_domain
|
||||
NvBool attach
|
||||
)
|
||||
{
|
||||
#if defined(NV_PM_RUNTIME_AVAILABLE) && defined(NV_PM_DOMAIN_AVAILABLE)
|
||||
#if defined(NV_PM_RUNTIME_AVAILABLE)
|
||||
nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv);
|
||||
struct pci_dev *pci_dev = nvl->pci_dev;
|
||||
struct device_node *node = pci_dev->dev.of_node;
|
||||
@@ -5821,7 +5809,7 @@ NvBool NV_API_CALL nv_pci_tegra_pm_init
|
||||
nv_state_t *nv
|
||||
)
|
||||
{
|
||||
#if defined(NV_PM_RUNTIME_AVAILABLE) && defined(NV_PM_DOMAIN_AVAILABLE)
|
||||
#if defined(NV_PM_RUNTIME_AVAILABLE)
|
||||
nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv);
|
||||
struct pci_dev *pci_dev = nvl->pci_dev;
|
||||
struct pci_bus *bus = pci_dev->bus;
|
||||
@@ -5858,7 +5846,7 @@ void NV_API_CALL nv_pci_tegra_pm_deinit
|
||||
nv_state_t *nv
|
||||
)
|
||||
{
|
||||
#if defined(NV_PM_RUNTIME_AVAILABLE) && defined(NV_PM_DOMAIN_AVAILABLE)
|
||||
#if defined(NV_PM_RUNTIME_AVAILABLE)
|
||||
nv_linux_state_t *nvl = NV_GET_NVL_FROM_NV_STATE(nv);
|
||||
struct pci_dev *pci_dev = nvl->pci_dev;
|
||||
struct pci_bus *bus = pci_dev->bus;
|
||||
@@ -6107,21 +6095,6 @@ void NV_API_CALL nv_get_screen_info(
|
||||
*pPhysicalAddress = 0;
|
||||
*pFbWidth = *pFbHeight = *pFbDepth = *pFbPitch = *pFbSize = 0;
|
||||
|
||||
#if defined(CONFIG_OF)
|
||||
//
|
||||
// Try to get the framebuffer information from device tree simple-framebuffer node.
|
||||
// This is particularly useful for Tegra platforms where the bootloader
|
||||
// sets up a simple framebuffer via device tree.
|
||||
//
|
||||
if (pci_dev == NULL)
|
||||
{
|
||||
if (nv_platform_get_screen_info_dt(pPhysicalAddress, pFbWidth, pFbHeight, pFbDepth, pFbPitch, pFbSize) == NV_OK)
|
||||
{
|
||||
return;
|
||||
}
|
||||
}
|
||||
#endif // CONFIG_OF
|
||||
|
||||
#if defined(CONFIG_FB) && defined(NV_NUM_REGISTERED_FB_PRESENT)
|
||||
if (num_registered_fb > 0)
|
||||
{
|
||||
@@ -6130,13 +6103,8 @@ void NV_API_CALL nv_get_screen_info(
|
||||
if (!registered_fb[i])
|
||||
continue;
|
||||
|
||||
/*
|
||||
* Ensure that either this is a zero-FB SOC GPU with a console in
|
||||
* the system carveout, or it’s a dGPU device with console mapped
|
||||
* onto its BAR.
|
||||
*/
|
||||
if (NV_HAS_CONSOLE_IN_SYSMEM_CARVEOUT(nv) ||
|
||||
NV_IS_CONSOLE_MAPPED(nv, registered_fb[i]->fix.smem_start))
|
||||
/* Make sure base address is mapped to GPU BAR */
|
||||
if (NV_IS_CONSOLE_MAPPED(nv, registered_fb[i]->fix.smem_start))
|
||||
{
|
||||
*pPhysicalAddress = registered_fb[i]->fix.smem_start;
|
||||
*pFbWidth = registered_fb[i]->var.xres;
|
||||
@@ -6184,13 +6152,9 @@ void NV_API_CALL nv_get_screen_info(
|
||||
physAddr |= (NvU64)screen_info.ext_lfb_base << 32;
|
||||
}
|
||||
#endif
|
||||
/*
|
||||
* Ensure that either this is a zero-FB SOC GPU with a console in the
|
||||
* system carveout, or it’s a dGPU device with console mapped onto its
|
||||
* BAR.
|
||||
*/
|
||||
if (NV_HAS_CONSOLE_IN_SYSMEM_CARVEOUT(nv) ||
|
||||
NV_IS_CONSOLE_MAPPED(nv, physAddr))
|
||||
|
||||
/* Make sure base address is mapped to GPU BAR */
|
||||
if (NV_IS_CONSOLE_MAPPED(nv, physAddr))
|
||||
{
|
||||
*pPhysicalAddress = physAddr;
|
||||
*pFbWidth = screen_info.lfb_width;
|
||||
@@ -6207,7 +6171,7 @@ void NV_API_CALL nv_get_screen_info(
|
||||
* If screen info can't be fetched with previous methods, then try
|
||||
* to get the base address and size from the memory resource tree.
|
||||
*/
|
||||
if ((pci_dev != NULL) && !NV_HAS_CONSOLE_IN_SYSMEM_CARVEOUT(nv))
|
||||
if (pci_dev != NULL)
|
||||
{
|
||||
BUILD_BUG_ON(NV_GPU_BAR_INDEX_IMEM != NV_GPU_BAR_INDEX_FB + 1);
|
||||
for (i = NV_GPU_BAR_INDEX_FB; i <= NV_GPU_BAR_INDEX_IMEM; i++)
|
||||
@@ -6258,8 +6222,7 @@ void NV_API_CALL nv_set_gpu_pg_mask
|
||||
*
|
||||
* Make sure the GPU PG feature is allowable only when runtime PM is supported here.
|
||||
*/
|
||||
#if defined(NV_BPMP_MRQ_HAS_STRAP_SET)
|
||||
#if defined(NV_PM_RUNTIME_AVAILABLE) && defined(NV_PM_DOMAIN_AVAILABLE)
|
||||
#if defined(NV_BPMP_MRQ_HAS_STRAP_SET) && defined(NV_PM_RUNTIME_AVAILABLE)
|
||||
struct mrq_strap_request request;
|
||||
NvS32 ret, api_ret;
|
||||
NV_STATUS status = NV_ERR_NOT_SUPPORTED;
|
||||
@@ -6315,8 +6278,7 @@ void NV_API_CALL nv_set_gpu_pg_mask
|
||||
nv_printf(NV_DBG_INFO, "NVRM: set gpu_pg_mask %d success\n", nv->tegra_pci_igpu_pg_mask);
|
||||
#else
|
||||
nv_printf(NV_DBG_INFO, "NVRM: gpu_pg_mask configuration is not supported\n");
|
||||
#endif // defined(NV_PM_RUNTIME_AVAILABLE) && defined(NV_PM_DOMAIN_AVAILABLE)
|
||||
#endif // defined(NV_BPMP_MRQ_HAS_STRAP_SET)
|
||||
#endif // defined(NV_BPMP_MRQ_HAS_STRAP_SET) && defined(NV_PM_RUNTIME_AVAILABLE)
|
||||
}
|
||||
|
||||
module_init(nvidia_init_module);
|
||||
|
||||
@@ -234,7 +234,6 @@ NV_CONFTEST_GENERIC_COMPILE_TESTS += get_user_pages_remote
|
||||
NV_CONFTEST_GENERIC_COMPILE_TESTS += pin_user_pages
|
||||
NV_CONFTEST_GENERIC_COMPILE_TESTS += pin_user_pages_remote
|
||||
NV_CONFTEST_GENERIC_COMPILE_TESTS += pm_runtime_available
|
||||
NV_CONFTEST_GENERIC_COMPILE_TESTS += pm_domain_available
|
||||
NV_CONFTEST_GENERIC_COMPILE_TESTS += vm_fault_t
|
||||
NV_CONFTEST_GENERIC_COMPILE_TESTS += pci_class_multimedia_hd_audio
|
||||
NV_CONFTEST_GENERIC_COMPILE_TESTS += drm_available
|
||||
|
||||
@@ -1 +1 @@
|
||||
rel-38_eng_2025-12-16
|
||||
jetson_38.2.2
|
||||
|
||||
@@ -2567,36 +2567,5 @@ typedef struct NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO_PARAMS {
|
||||
NvU32 counterValueV;
|
||||
} NV0073_CTRL_CMD_SYSTEM_GET_CRASH_LOCK_COUNTER_INFO_PARAMS;
|
||||
|
||||
/*
|
||||
* NV0073_CTRL_CMD_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH
|
||||
*
|
||||
* Queries the UEFI allocated ISO BW and Floor BW for Display.
|
||||
*
|
||||
* subDeviceInstance
|
||||
* This parameter specifies the subdevice instance within the
|
||||
* NV04_DISPLAY_COMMON parent device to which the operation should be
|
||||
* directed.
|
||||
* isoBandwidthKBPS
|
||||
* ISO BW set by UEFI to initialize display
|
||||
* floorBandwidthKBPS
|
||||
* Floor BW set by UEFI to initialize display
|
||||
*
|
||||
* Possible status values returned are:
|
||||
* NV_OK
|
||||
* NV_ERR_INVALID_ARGUMENT
|
||||
* NV_ERR_NOT_SUPPORTED
|
||||
* NV_ERR_GENERIC
|
||||
*/
|
||||
|
||||
#define NV0073_CTRL_CMD_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH (0x730161U) /* finn: Evaluated from "(FINN_NV04_DISPLAY_COMMON_SYSTEM_INTERFACE_ID << 8) | NV0073_CTRL_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID" */
|
||||
|
||||
#define NV0073_CTRL_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH_PARAMS_MESSAGE_ID (0x61U)
|
||||
|
||||
typedef struct NV0073_CTRL_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH_PARAMS {
|
||||
NvU32 subDeviceInstance;
|
||||
NvU32 isoBandwidthKBPS;
|
||||
NvU32 floorBandwidthKBPS;
|
||||
} NV0073_CTRL_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH_PARAMS;
|
||||
|
||||
/* _ctrl0073system_h_ */
|
||||
|
||||
|
||||
@@ -598,17 +598,13 @@ typedef enum NvKmsKapiRegisterWaiterResultRec {
|
||||
NVKMS_KAPI_REG_WAITER_ALREADY_SIGNALLED,
|
||||
} NvKmsKapiRegisterWaiterResult;
|
||||
|
||||
typedef void NvKmsKapiSuspendResumeCallbackFunc(NvBool suspend);
|
||||
|
||||
struct NvKmsKapiGpuInfo {
|
||||
nv_gpu_info_t gpuInfo;
|
||||
MIGDeviceId migDevice;
|
||||
};
|
||||
|
||||
struct NvKmsKapiCallbacks {
|
||||
void (*suspendResume)(NvBool suspend);
|
||||
void (*remove)(NvU32 gpuId);
|
||||
void (*probe)(const struct NvKmsKapiGpuInfo *gpu_info);
|
||||
};
|
||||
|
||||
struct NvKmsKapiFunctionsTable {
|
||||
|
||||
/*!
|
||||
@@ -1477,12 +1473,12 @@ struct NvKmsKapiFunctionsTable {
|
||||
);
|
||||
|
||||
/*!
|
||||
* Set the pointer to the callback function table.
|
||||
* Set the callback function for suspending and resuming the display system.
|
||||
*/
|
||||
void
|
||||
(*setCallbacks)
|
||||
(*setSuspendResumeCallback)
|
||||
(
|
||||
const struct NvKmsKapiCallbacks *callbacks
|
||||
NvKmsKapiSuspendResumeCallbackFunc *function
|
||||
);
|
||||
|
||||
/*!
|
||||
|
||||
@@ -3890,53 +3890,28 @@ static NvBool GetCRC32
|
||||
return NV_TRUE;
|
||||
}
|
||||
|
||||
static const struct NvKmsKapiCallbacks *pCallbacks;
|
||||
static NvKmsKapiSuspendResumeCallbackFunc *pSuspendResumeFunc;
|
||||
|
||||
void nvKmsKapiSuspendResume
|
||||
(
|
||||
NvBool suspend
|
||||
)
|
||||
{
|
||||
if (pCallbacks) {
|
||||
pCallbacks->suspendResume(suspend);
|
||||
if (pSuspendResumeFunc) {
|
||||
pSuspendResumeFunc(suspend);
|
||||
}
|
||||
}
|
||||
|
||||
static void nvKmsKapiSetCallbacks
|
||||
static void nvKmsKapiSetSuspendResumeCallback
|
||||
(
|
||||
const struct NvKmsKapiCallbacks *callbacks
|
||||
NvKmsKapiSuspendResumeCallbackFunc *function
|
||||
)
|
||||
{
|
||||
if (pCallbacks && callbacks) {
|
||||
nvKmsKapiLogDebug("Kapi callback functions already registered");
|
||||
if (pSuspendResumeFunc && function) {
|
||||
nvKmsKapiLogDebug("Kapi suspend/resume callback function already registered");
|
||||
}
|
||||
|
||||
pCallbacks = callbacks;
|
||||
}
|
||||
|
||||
void nvKmsKapiRemove
|
||||
(
|
||||
NvU32 gpuId
|
||||
)
|
||||
{
|
||||
if (pCallbacks) {
|
||||
pCallbacks->remove(gpuId);
|
||||
}
|
||||
}
|
||||
|
||||
void nvKmsKapiProbe
|
||||
(
|
||||
const nv_gpu_info_t *gpu_info
|
||||
)
|
||||
{
|
||||
if (pCallbacks) {
|
||||
const struct NvKmsKapiGpuInfo kapi_gpu_info = {
|
||||
.gpuInfo = *gpu_info,
|
||||
.migDevice = NO_MIG_DEVICE,
|
||||
};
|
||||
|
||||
pCallbacks->probe(&kapi_gpu_info);
|
||||
}
|
||||
pSuspendResumeFunc = function;
|
||||
}
|
||||
|
||||
static NvBool SignalVrrSemaphore
|
||||
@@ -4081,7 +4056,7 @@ NvBool nvKmsKapiGetFunctionsTableInternal
|
||||
nvKmsKapiUnregisterSemaphoreSurfaceCallback;
|
||||
funcsTable->setSemaphoreSurfaceValue =
|
||||
nvKmsKapiSetSemaphoreSurfaceValue;
|
||||
funcsTable->setCallbacks = nvKmsKapiSetCallbacks;
|
||||
funcsTable->setSuspendResumeCallback = nvKmsKapiSetSuspendResumeCallback;
|
||||
funcsTable->framebufferConsoleDisabled = FramebufferConsoleDisabled;
|
||||
|
||||
funcsTable->tryInitDisplaySemaphore = nvKmsKapiTryInitDisplaySemaphore;
|
||||
|
||||
@@ -104,8 +104,6 @@ NvBool nvKmsKapiGetFunctionsTableInternal
|
||||
);
|
||||
|
||||
void nvKmsKapiSuspendResume(NvBool suspend);
|
||||
void nvKmsKapiRemove(NvU32 gpuId);
|
||||
void nvKmsKapiProbe(const nv_gpu_info_t *gpu_info);
|
||||
|
||||
NvBool nvKmsGetBacklight(NvU32 display_id, void *drv_priv, NvU32 *brightness);
|
||||
NvBool nvKmsSetBacklight(NvU32 display_id, void *drv_priv, NvU32 brightness);
|
||||
|
||||
@@ -7826,6 +7826,7 @@ NvBool nvAllocateDisplayBandwidth(
|
||||
if (!pDevEvo->isSOCDisplay) {
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
params.subDeviceInstance = 0;
|
||||
params.averageBandwidthKBPS = newIsoBandwidthKBPS;
|
||||
params.floorBandwidthKBPS = newDramFloorKBPS;
|
||||
@@ -7927,62 +7928,6 @@ static void AssignNVEvoIsModePossibleDispInput(
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* Query UEFI passed ISO BW and DRAM Floor
|
||||
*/
|
||||
static NvBool QueryUefiIMPParams(NVDispEvoPtr pDispEvo,
|
||||
const NvU32 modesetRequestedHeadsMask)
|
||||
{
|
||||
NVDevEvoPtr pDevEvo = pDispEvo->pDevEvo;
|
||||
NVDispHeadStateEvoPtr pHeadState;
|
||||
NV0073_CTRL_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH_PARAMS params = {};
|
||||
NvU32 ret;
|
||||
NvBool uefiHandoff = FALSE;
|
||||
|
||||
if (!pDevEvo->isSOCDisplay) {
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
if (!pDevEvo->coreInitMethodsPending || (modesetRequestedHeadsMask == 0x0)) {
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
for (NvU32 head = 0; head < pDevEvo->numHeads; head++) {
|
||||
if (!nvDpyIdListIsEmpty(pDispEvo->vbiosDpyConfig[head])) {
|
||||
pHeadState = &pDispEvo->headState[head];
|
||||
|
||||
if ((pHeadState->activeRmId != 0x0) &&
|
||||
(pDispEvo->isoBandwidthKBPS == 0) && (pDispEvo->dramFloorKBPS == 0)) {
|
||||
nvEvoLogDev(pDevEvo, EVO_LOG_INFO,
|
||||
"Found active displayID: 0x%x initialized by UEFI on head %u", pHeadState->activeRmId, head);
|
||||
uefiHandoff = TRUE;
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (uefiHandoff)
|
||||
{
|
||||
params.subDeviceInstance = 0;
|
||||
params.isoBandwidthKBPS = 0;
|
||||
params.floorBandwidthKBPS = 0;
|
||||
ret = nvRmApiControl(nvEvoGlobal.clientHandle,
|
||||
pDevEvo->displayCommonHandle,
|
||||
NV0073_CTRL_CMD_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH,
|
||||
¶ms, sizeof(params));
|
||||
if (ret != NV_OK) {
|
||||
nvEvoLogDev(pDevEvo, EVO_LOG_ERROR,
|
||||
"Failed to query IMP params for UEFI initialized firmware head");
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
pDispEvo->isoBandwidthKBPS = NV_MAX(pDispEvo->isoBandwidthKBPS, params.isoBandwidthKBPS);
|
||||
pDispEvo->dramFloorKBPS = NV_MAX(pDispEvo->dramFloorKBPS, params.floorBandwidthKBPS);
|
||||
}
|
||||
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
/*!
|
||||
* Validate the described disp configuration through IMP.
|
||||
|
||||
@@ -8057,22 +8002,20 @@ NvBool nvValidateImpOneDisp(
|
||||
|
||||
switch (reallocBandwidth) {
|
||||
case NV_EVO_REALLOCATE_BANDWIDTH_MODE_PRE:
|
||||
if (!QueryUefiIMPParams(pDispEvo, modesetRequestedHeadsMask)) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
needToRealloc = (impOutput.minRequiredBandwidthKBPS > pDispEvo->isoBandwidthKBPS) ||
|
||||
(impOutput.floorBandwidthKBPS > pDispEvo->dramFloorKBPS);
|
||||
newIsoBandwidthKBPS =
|
||||
NV_MAX(pDispEvo->isoBandwidthKBPS, impOutput.minRequiredBandwidthKBPS);
|
||||
newDramFloorKBPS =
|
||||
NV_MAX(pDispEvo->dramFloorKBPS, impOutput.floorBandwidthKBPS);
|
||||
|
||||
break;
|
||||
case NV_EVO_REALLOCATE_BANDWIDTH_MODE_POST:
|
||||
needToRealloc = (impOutput.minRequiredBandwidthKBPS != pDispEvo->isoBandwidthKBPS) ||
|
||||
(impOutput.floorBandwidthKBPS != pDispEvo->dramFloorKBPS);
|
||||
newIsoBandwidthKBPS = impOutput.minRequiredBandwidthKBPS;
|
||||
newDramFloorKBPS = impOutput.floorBandwidthKBPS;
|
||||
|
||||
break;
|
||||
case NV_EVO_REALLOCATE_BANDWIDTH_MODE_NONE:
|
||||
default:
|
||||
|
||||
@@ -3207,8 +3207,7 @@ static NvBool AssignPerHeadImpParams(NVC372_CTRL_IMP_HEAD *pImpHead,
|
||||
const NvBool enableDsc,
|
||||
const NvBool b2Heads1Or,
|
||||
const int head,
|
||||
const NVEvoScalerCaps *pScalerCaps,
|
||||
const NvU32 possibleDscSliceCountMask)
|
||||
const NVEvoScalerCaps *pScalerCaps)
|
||||
{
|
||||
const NVHwModeViewPortEvo *pViewPort = &pTimings->viewPort;
|
||||
struct NvKmsScalingUsageBounds scalingUsageBounds = { };
|
||||
@@ -3261,7 +3260,6 @@ static NvBool AssignPerHeadImpParams(NVC372_CTRL_IMP_HEAD *pImpHead,
|
||||
pImpHead->cursorSize32p = 256 / 32;
|
||||
|
||||
pImpHead->bEnableDsc = enableDsc;
|
||||
pImpHead->possibleDscSliceCountMask = possibleDscSliceCountMask;
|
||||
|
||||
pImpHead->bIs2Head1Or = b2Heads1Or;
|
||||
|
||||
@@ -3396,8 +3394,7 @@ nvEvoSetCtrlIsModePossibleParams3(NVDispEvoPtr pDispEvo,
|
||||
enableDsc,
|
||||
b2Heads1Or,
|
||||
head,
|
||||
&pEvoCaps->head[head].scalerCaps,
|
||||
pInput->head[head].possibleDscSliceCountMask)) {
|
||||
&pEvoCaps->head[head].scalerCaps)) {
|
||||
return FALSE;
|
||||
}
|
||||
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014 - 2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2014 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -1717,16 +1717,14 @@ ValidateColorspace(const NVDevEvoRec *pDevEvo,
|
||||
const NVFlipEvoHwState *pFlipState,
|
||||
NvU32 layer)
|
||||
{
|
||||
NVSurfaceEvoPtr pSurfaceEvo =
|
||||
pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT];
|
||||
if (pSurfaceEvo == NULL) {
|
||||
return TRUE;
|
||||
}
|
||||
|
||||
if ((pFlipState->layer[layer].colorSpace !=
|
||||
NVKMS_INPUT_COLOR_SPACE_NONE)) {
|
||||
|
||||
NVSurfaceEvoPtr pSurfaceEvo =
|
||||
pFlipState->layer[layer].pSurfaceEvo[NVKMS_LEFT];
|
||||
const NvKmsSurfaceMemoryFormatInfo *pFormatInfo =
|
||||
nvKmsGetSurfaceMemoryFormatInfo(pSurfaceEvo->format);
|
||||
(pSurfaceEvo != NULL) ?
|
||||
nvKmsGetSurfaceMemoryFormatInfo(pSurfaceEvo->format) : NULL;
|
||||
|
||||
if (pFormatInfo == NULL) {
|
||||
return FALSE;
|
||||
|
||||
@@ -1,5 +1,5 @@
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2005-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 2005-2015 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -1989,9 +1989,7 @@ static NvBool ConstructModeTimingsMetaData(
|
||||
* pTimingsEvo after ValidateMode has written to it.
|
||||
*/
|
||||
if (nvDpyIsHdmiEvo(pDpyEvo)) {
|
||||
if (pVideoInfoFrameCtrl != NULL) {
|
||||
NvTiming_ConstructVideoInfoframeCtrl(&timing, pVideoInfoFrameCtrl);
|
||||
}
|
||||
NvTiming_ConstructVideoInfoframeCtrl(&timing, pVideoInfoFrameCtrl);
|
||||
|
||||
if (pVendorInfoFrameCtrl != NULL) {
|
||||
// Currently hardcoded to send infoframe necessary for HDMI 1.4a 4kx2k extended modes.
|
||||
|
||||
@@ -143,8 +143,6 @@ typedef enum _TEGRASOC_WHICH_CLK
|
||||
TEGRASOC_WHICH_CLK_SPPLL0_DIV10,
|
||||
TEGRASOC_WHICH_CLK_SPPLL0_DIV25,
|
||||
TEGRASOC_WHICH_CLK_SPPLL1_VCO,
|
||||
TEGRASOC_WHICH_CLK_SPPLL0,
|
||||
TEGRASOC_WHICH_CLK_SPPLL1,
|
||||
TEGRASOC_WHICH_CLK_VPLL0_REF,
|
||||
TEGRASOC_WHICH_CLK_VPLL0,
|
||||
TEGRASOC_WHICH_CLK_VPLL1,
|
||||
@@ -230,9 +228,6 @@ typedef enum _TEGRASOC_WHICH_CLK
|
||||
TEGRASOC_WHICH_CLK_MIPI_CAL,
|
||||
TEGRASOC_WHICH_CLK_UART_FST_MIPI_CAL,
|
||||
TEGRASOC_WHICH_CLK_SOR0_DIV,
|
||||
TEGRASOC_WHICH_CLK_SOR1_DIV,
|
||||
TEGRASOC_WHICH_CLK_SOR2_DIV,
|
||||
TEGRASOC_WHICH_CLK_SOR3_DIV,
|
||||
TEGRASOC_WHICH_CLK_DISP_ROOT,
|
||||
TEGRASOC_WHICH_CLK_HUB_ROOT,
|
||||
TEGRASOC_WHICH_CLK_PLLA_DISP,
|
||||
@@ -601,12 +596,6 @@ typedef struct nv_state_t
|
||||
NvU32 dispNisoStreamId;
|
||||
} iommus;
|
||||
|
||||
struct {
|
||||
NvU32 max_dispclk_rate_using_disppllkhz;
|
||||
NvU32 max_dispclk_rate_using_sppll0clkoutakhz;
|
||||
NvU32 max_hubclk_rate_using_sppll0clkoutbkhz;
|
||||
} clocks;
|
||||
|
||||
/* Console is managed by drm drivers or NVKMS */
|
||||
NvBool client_managed_console;
|
||||
} nv_state_t;
|
||||
@@ -675,24 +664,23 @@ typedef NV_STATUS (*nvPmaEvictRangeCallback)(void *, NvU64, NvU64, nvgpuGpuMemor
|
||||
* flags
|
||||
*/
|
||||
|
||||
#define NV_FLAG_OPEN 0x0001
|
||||
#define NV_FLAG_EXCLUDE 0x0002
|
||||
#define NV_FLAG_CONTROL 0x0004
|
||||
#define NV_FLAG_PCI_P2P_UNSUPPORTED_CHIPSET 0x0008
|
||||
#define NV_FLAG_SOC_DISPLAY 0x0010
|
||||
#define NV_FLAG_USES_MSI 0x0020
|
||||
#define NV_FLAG_USES_MSIX 0x0040
|
||||
#define NV_FLAG_PASSTHRU 0x0080
|
||||
#define NV_FLAG_SUSPENDED 0x0100
|
||||
#define NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT 0x0200
|
||||
#define NV_FLAG_OPEN 0x0001
|
||||
#define NV_FLAG_EXCLUDE 0x0002
|
||||
#define NV_FLAG_CONTROL 0x0004
|
||||
#define NV_FLAG_PCI_P2P_UNSUPPORTED_CHIPSET 0x0008
|
||||
#define NV_FLAG_SOC_DISPLAY 0x0010
|
||||
#define NV_FLAG_USES_MSI 0x0020
|
||||
#define NV_FLAG_USES_MSIX 0x0040
|
||||
#define NV_FLAG_PASSTHRU 0x0080
|
||||
#define NV_FLAG_SUSPENDED 0x0100
|
||||
/* To be set when an FLR needs to be triggered after device shut down. */
|
||||
#define NV_FLAG_TRIGGER_FLR 0x0400
|
||||
#define NV_FLAG_PERSISTENT_SW_STATE 0x0800
|
||||
#define NV_FLAG_IN_RECOVERY 0x1000
|
||||
#define NV_FLAG_PCI_REMOVE_IN_PROGRESS 0x2000
|
||||
#define NV_FLAG_UNBIND_LOCK 0x4000
|
||||
#define NV_FLAG_TRIGGER_FLR 0x0400
|
||||
#define NV_FLAG_PERSISTENT_SW_STATE 0x0800
|
||||
#define NV_FLAG_IN_RECOVERY 0x1000
|
||||
#define NV_FLAG_PCI_REMOVE_IN_PROGRESS 0x2000
|
||||
#define NV_FLAG_UNBIND_LOCK 0x4000
|
||||
/* To be set when GPU is not present on the bus, to help device teardown */
|
||||
#define NV_FLAG_IN_SURPRISE_REMOVAL 0x8000
|
||||
#define NV_FLAG_IN_SURPRISE_REMOVAL 0x8000
|
||||
|
||||
typedef enum
|
||||
{
|
||||
@@ -740,20 +728,6 @@ typedef enum
|
||||
NV_MEMORY_TYPE_DEVICE_MMIO, /* All kinds of MMIO referred by NVRM e.g. BARs and MCFG of device */
|
||||
} nv_memory_type_t;
|
||||
|
||||
typedef struct nv_allocation_request_s
|
||||
{
|
||||
NvU32 count;
|
||||
NvU64 page_size;
|
||||
NvBool alloc_type_contiguous;
|
||||
NvU32 cache_type;
|
||||
NvBool alloc_type_zeroed;
|
||||
NvBool unencrypted;
|
||||
NvBool no_reclaim;
|
||||
NvS32 node_id;
|
||||
NvU64 *pte_array;
|
||||
void **private;
|
||||
} nv_allocation_request_t;
|
||||
|
||||
#define NV_PRIMARY_VGA(nv) ((nv)->primary_vga)
|
||||
|
||||
#define NV_IS_CTL_DEVICE(nv) ((nv)->flags & NV_FLAG_CONTROL)
|
||||
@@ -763,9 +737,6 @@ typedef struct nv_allocation_request_s
|
||||
#define NV_IS_DEVICE_IN_SURPRISE_REMOVAL(nv) \
|
||||
(((nv)->flags & NV_FLAG_IN_SURPRISE_REMOVAL) != 0)
|
||||
|
||||
#define NV_HAS_CONSOLE_IN_SYSMEM_CARVEOUT(nv) \
|
||||
(((nv)->flags & NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT) != 0)
|
||||
|
||||
/*
|
||||
* For console setup by EFI GOP, the base address is BAR1.
|
||||
* For console setup by VBIOS, the base address is BAR2 + 16MB.
|
||||
@@ -925,7 +896,7 @@ nv_state_t* NV_API_CALL nv_get_ctl_state (void);
|
||||
void NV_API_CALL nv_set_dma_address_size (nv_state_t *, NvU32 );
|
||||
|
||||
NV_STATUS NV_API_CALL nv_alias_pages (nv_state_t *, NvU32, NvU64, NvU32, NvU32, NvU64, NvU64 *, NvBool, void **);
|
||||
NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, nv_allocation_request_t *);
|
||||
NV_STATUS NV_API_CALL nv_alloc_pages (nv_state_t *, NvU32, NvU64, NvBool, NvU32, NvBool, NvBool, NvS32, NvU64 *, void **);
|
||||
NV_STATUS NV_API_CALL nv_free_pages (nv_state_t *, NvU32, NvBool, NvU32, void *);
|
||||
|
||||
NV_STATUS NV_API_CALL nv_register_user_pages (nv_state_t *, NvU64, NvU64 *, void *, void **, NvBool);
|
||||
@@ -1063,7 +1034,6 @@ NV_STATUS NV_API_CALL nv_i2c_transfer(nv_state_t *, NvU32, NvU8, nv_i2c_msg_t *,
|
||||
void NV_API_CALL nv_i2c_unregister_clients(nv_state_t *);
|
||||
NV_STATUS NV_API_CALL nv_i2c_bus_status(nv_state_t *, NvU32, NvS32 *, NvS32 *);
|
||||
NV_STATUS NV_API_CALL nv_imp_get_import_data (TEGRA_IMP_IMPORT_DATA *);
|
||||
NV_STATUS NV_API_CALL nv_imp_get_uefi_data (nv_state_t *nv, NvU32 *iso_bw_kbps, NvU32 *floor_bw_kbps);
|
||||
NV_STATUS NV_API_CALL nv_imp_enable_disable_rfl (nv_state_t *nv, NvBool bEnable);
|
||||
NV_STATUS NV_API_CALL nv_imp_icc_set_bw (nv_state_t *nv, NvU32 avg_bw_kbps, NvU32 floor_bw_kbps);
|
||||
NV_STATUS NV_API_CALL nv_get_num_dpaux_instances(nv_state_t *nv, NvU32 *num_instances);
|
||||
|
||||
@@ -818,11 +818,11 @@ NV_STATUS osAllocPagesInternal(
|
||||
// For carveout, the memory is already reserved so we don't have
|
||||
// to allocate memory.
|
||||
//
|
||||
if (memdescIsCarveoutMemory(pMemDesc) ||
|
||||
if (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT) ||
|
||||
memdescGetFlag(pMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED))
|
||||
{
|
||||
// We only support carveout with contiguous memory.
|
||||
if (memdescIsCarveoutMemory(pMemDesc) &&
|
||||
// We only support scanout carveout with contiguous memory.
|
||||
if (memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT) &&
|
||||
!memdescGetContiguity(pMemDesc, AT_CPU))
|
||||
{
|
||||
status = NV_ERR_NOT_SUPPORTED;
|
||||
@@ -848,7 +848,7 @@ NV_STATUS osAllocPagesInternal(
|
||||
cpuCacheAttrib,
|
||||
memdescGetGuestId(pMemDesc),
|
||||
memdescGetPteArray(pMemDesc, AT_CPU),
|
||||
memdescIsCarveoutMemory(pMemDesc),
|
||||
memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT),
|
||||
&pMemData);
|
||||
}
|
||||
else
|
||||
@@ -894,24 +894,18 @@ NV_STATUS osAllocPagesInternal(
|
||||
if (status != NV_OK)
|
||||
goto done;
|
||||
|
||||
{
|
||||
nv_allocation_request_t alloc_request = {0};
|
||||
alloc_request.count = osPageCount; // TODO: This call needs to receive the page count param at the requested page size.
|
||||
alloc_request.page_size = pageSize;
|
||||
alloc_request.alloc_type_contiguous = memdescGetContiguity(pMemDesc, AT_CPU);
|
||||
alloc_request.cache_type = cpuCacheAttrib;
|
||||
alloc_request.alloc_type_zeroed = pSys->getProperty(pSys,
|
||||
PDB_PROP_SYS_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS);
|
||||
alloc_request.unencrypted = unencrypted;
|
||||
alloc_request.no_reclaim = memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_NO_RECLAIM);
|
||||
alloc_request.node_id = nodeId;
|
||||
alloc_request.pte_array = memdescGetPteArray(pMemDesc, AT_CPU);
|
||||
alloc_request.private = &pMemData;
|
||||
|
||||
status = nv_alloc_pages(
|
||||
NV_GET_NV_STATE(pGpu),
|
||||
&alloc_request);
|
||||
}
|
||||
status = nv_alloc_pages(
|
||||
NV_GET_NV_STATE(pGpu),
|
||||
osPageCount, // TODO: This call needs to receive the page count param at the requested page size.
|
||||
pageSize,
|
||||
memdescGetContiguity(pMemDesc, AT_CPU),
|
||||
cpuCacheAttrib,
|
||||
pSys->getProperty(pSys,
|
||||
PDB_PROP_SYS_INITIALIZE_SYSTEM_MEMORY_ALLOCATIONS),
|
||||
unencrypted,
|
||||
nodeId,
|
||||
memdescGetPteArray(pMemDesc, AT_CPU),
|
||||
&pMemData);
|
||||
|
||||
if (nv && nv->force_dma32_alloc)
|
||||
nv->force_dma32_alloc = NV_FALSE;
|
||||
@@ -3053,7 +3047,7 @@ osIovaMap
|
||||
// address is same as the DMA address.
|
||||
//
|
||||
//
|
||||
if (memdescIsCarveoutMemory(pIovaMapping->pPhysMemDesc) ||
|
||||
if (memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT) ||
|
||||
memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED))
|
||||
{
|
||||
return NV_OK;
|
||||
@@ -3208,7 +3202,7 @@ osIovaUnmap
|
||||
// For guest-allocated or carveout memory, we never actually remapped the
|
||||
// memory, so we shouldn't try to unmap it here.
|
||||
//
|
||||
if (memdescIsCarveoutMemory(pIovaMapping->pPhysMemDesc) ||
|
||||
if (memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT) ||
|
||||
memdescGetFlag(pIovaMapping->pPhysMemDesc, MEMDESC_FLAGS_GUEST_ALLOCATED))
|
||||
{
|
||||
return;
|
||||
@@ -4867,37 +4861,6 @@ osTegraSocGetImpImportData
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Returns IMP-relevant data collected from UEFI
|
||||
*
|
||||
* This function is basically a wrapper to call the unix/linux layer.
|
||||
*
|
||||
* @param[in] pOsGpuInfo Per GPU Linux state
|
||||
* @param[out] pIsoBwKbps ISO BW set by UEFI
|
||||
* @param[out] pFloorBwKbps DRAM Floor BW set by UEFI
|
||||
*
|
||||
* @returns NV_OK if successful,
|
||||
* NV_ERR_NOT_SUPPORTED if the functionality is not available, or
|
||||
* other errors as may be returned by subfunctions.
|
||||
*/
|
||||
NV_STATUS
|
||||
osTegraSocGetImpUefiData
|
||||
(
|
||||
OS_GPU_INFO *pOsGpuInfo,
|
||||
NvU32 *pIsoBwKbps,
|
||||
NvU32 *pFloorBwKbps
|
||||
)
|
||||
{
|
||||
if (NV_IS_SOC_DISPLAY_DEVICE(pOsGpuInfo))
|
||||
{
|
||||
return nv_imp_get_uefi_data(pOsGpuInfo, pIsoBwKbps, pFloorBwKbps);
|
||||
}
|
||||
else
|
||||
{
|
||||
return NV_ERR_NOT_SUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Tells BPMP whether or not RFL is valid
|
||||
*
|
||||
@@ -4934,42 +4897,6 @@ osTegraSocEnableDisableRfl
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Returns max rates for display clocks passed by UEFI
|
||||
*
|
||||
* @param[in] pOsGpuInfo Per GPU Linux state
|
||||
* @param[out] pMaxDispClkRateDisppll disp clock maxrate with disppll as parent
|
||||
* @param[out] pMaxDispClkRateSppllClkouta disp clock maxrate with sppllclkouta as parent
|
||||
* @param[out] pMaxHubClkRateSppllClkoutb hub clock maxrate with sppllclkoutb as parent
|
||||
*
|
||||
* @returns NV_OK if successful,
|
||||
* NV_ERR_NOT_SUPPORTED if the functionality is not available
|
||||
*/
|
||||
NV_STATUS
|
||||
osTegraSocGetDispClockRates
|
||||
(
|
||||
OS_GPU_INFO *pOsGpuInfo,
|
||||
NvU32 *pMaxDispClkRateDisppll,
|
||||
NvU32 *pMaxDispClkRateSppllClkouta,
|
||||
NvU32 *pMaxHubClkRateSppllClkoutb
|
||||
)
|
||||
{
|
||||
nv_state_t *nv = pOsGpuInfo;
|
||||
|
||||
if (NV_IS_SOC_DISPLAY_DEVICE(nv))
|
||||
{
|
||||
*pMaxDispClkRateDisppll = nv->clocks.max_dispclk_rate_using_disppllkhz;
|
||||
*pMaxDispClkRateSppllClkouta = nv->clocks.max_dispclk_rate_using_sppll0clkoutakhz;
|
||||
*pMaxHubClkRateSppllClkoutb = nv->clocks.max_hubclk_rate_using_sppll0clkoutbkhz;
|
||||
|
||||
return NV_OK;
|
||||
}
|
||||
else
|
||||
{
|
||||
return NV_ERR_NOT_SUPPORTED;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Allocates a specified amount of ISO memory bandwidth for display
|
||||
*
|
||||
|
||||
@@ -1910,7 +1910,7 @@ static NV_STATUS RmGetAllocPrivate(
|
||||
bPeerIoMem = memdescGetFlag(pMemDesc, MEMDESC_FLAGS_PEER_IO_MEM);
|
||||
|
||||
if (!(pMemDesc->Allocated || bPeerIoMem ||
|
||||
memdescIsCarveoutMemory(pMemDesc) ||
|
||||
(memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT)) ||
|
||||
(memdescGetFlag(pMemDesc, MEMDESC_FLAGS_ALLOW_EXT_SYSMEM_USER_CPU_MAPPING))))
|
||||
{
|
||||
NV_PRINTF(LEVEL_ERROR, "Mmap is not allowed\n");
|
||||
@@ -4784,8 +4784,7 @@ NV_STATUS NV_API_CALL rm_pmu_perfmon_get_load(
|
||||
return NV_ERR_INVALID_ARGUMENT;
|
||||
}
|
||||
|
||||
if (nvp->dynamic_power.state != NV_DYNAMIC_POWER_STATE_IN_USE &&
|
||||
nvp->dynamic_power.state != NV_DYNAMIC_POWER_STATE_IDLE_INSTANT)
|
||||
if (nvp->dynamic_power.state == NV_DYNAMIC_POWER_STATE_IDLE_INDICATED)
|
||||
{
|
||||
*load = 0;
|
||||
return NV_OK;
|
||||
|
||||
@@ -636,11 +636,6 @@ osInitNvMapping(
|
||||
{
|
||||
nv->flags |= NV_FLAG_TRIGGER_FLR;
|
||||
}
|
||||
|
||||
if (pGpu->getProperty(pGpu, PDB_PROP_GPU_IS_SOC_SDM))
|
||||
{
|
||||
nv->flags |= NV_FLAG_HAS_CONSOLE_IN_SYSMEM_CARVEOUT;
|
||||
}
|
||||
}
|
||||
|
||||
static NV_STATUS
|
||||
|
||||
@@ -3233,21 +3233,6 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
#endif
|
||||
},
|
||||
{ /* [22] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
/*pFunc=*/ (void (*)(void)) dispcmnCtrlCmdSystemQueryUefiDisplayBandwidth_IMPL,
|
||||
#endif // NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u)
|
||||
/*flags=*/ 0x4u,
|
||||
/*accessRight=*/0x0u,
|
||||
/*methodId=*/ 0x730161u,
|
||||
/*paramSize=*/ sizeof(NV0073_CTRL_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH_PARAMS),
|
||||
/*pClassInfo=*/ &(__nvoc_class_def_DispCommon.classInfo),
|
||||
#if NV_PRINTF_STRINGS_ALLOWED
|
||||
/*func=*/ "dispcmnCtrlCmdSystemQueryUefiDisplayBandwidth"
|
||||
#endif
|
||||
},
|
||||
{ /* [23] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3262,7 +3247,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificGetI2cPortid"
|
||||
#endif
|
||||
},
|
||||
{ /* [24] */
|
||||
{ /* [23] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x820046u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3277,7 +3262,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificGetType"
|
||||
#endif
|
||||
},
|
||||
{ /* [25] */
|
||||
{ /* [24] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3292,7 +3277,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificFakeDevice"
|
||||
#endif
|
||||
},
|
||||
{ /* [26] */
|
||||
{ /* [25] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3307,7 +3292,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificGetEdidV2"
|
||||
#endif
|
||||
},
|
||||
{ /* [27] */
|
||||
{ /* [26] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3322,7 +3307,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificSetEdidV2"
|
||||
#endif
|
||||
},
|
||||
{ /* [28] */
|
||||
{ /* [27] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3337,7 +3322,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificGetConnectorData"
|
||||
#endif
|
||||
},
|
||||
{ /* [29] */
|
||||
{ /* [28] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3352,7 +3337,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificGetHdcpRepeaterInfo"
|
||||
#endif
|
||||
},
|
||||
{ /* [30] */
|
||||
{ /* [29] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3367,7 +3352,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificSetHdmiEnable"
|
||||
#endif
|
||||
},
|
||||
{ /* [31] */
|
||||
{ /* [30] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3382,7 +3367,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificCtrlHdmi"
|
||||
#endif
|
||||
},
|
||||
{ /* [32] */
|
||||
{ /* [31] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3397,7 +3382,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificSetHdmiAudioMutestream"
|
||||
#endif
|
||||
},
|
||||
{ /* [33] */
|
||||
{ /* [32] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3412,7 +3397,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificGetHdcpState"
|
||||
#endif
|
||||
},
|
||||
{ /* [34] */
|
||||
{ /* [33] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3427,7 +3412,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificGetHdcpDiagnostics"
|
||||
#endif
|
||||
},
|
||||
{ /* [35] */
|
||||
{ /* [34] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3442,7 +3427,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificHdcpCtrl"
|
||||
#endif
|
||||
},
|
||||
{ /* [36] */
|
||||
{ /* [35] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3457,7 +3442,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificGetAllHeadMask"
|
||||
#endif
|
||||
},
|
||||
{ /* [37] */
|
||||
{ /* [36] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3472,7 +3457,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificSetOdPacket"
|
||||
#endif
|
||||
},
|
||||
{ /* [38] */
|
||||
{ /* [37] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3487,7 +3472,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificSetOdPacketCtrl"
|
||||
#endif
|
||||
},
|
||||
{ /* [39] */
|
||||
{ /* [38] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3502,7 +3487,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificGetPclkLimit"
|
||||
#endif
|
||||
},
|
||||
{ /* [40] */
|
||||
{ /* [39] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x46u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3517,7 +3502,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificOrGetInfo"
|
||||
#endif
|
||||
},
|
||||
{ /* [41] */
|
||||
{ /* [40] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3532,7 +3517,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificHdcpKsvListValidate"
|
||||
#endif
|
||||
},
|
||||
{ /* [42] */
|
||||
{ /* [41] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3547,7 +3532,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificHdcpUpdate"
|
||||
#endif
|
||||
},
|
||||
{ /* [43] */
|
||||
{ /* [42] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3562,7 +3547,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificSetHdmiSinkCaps"
|
||||
#endif
|
||||
},
|
||||
{ /* [44] */
|
||||
{ /* [43] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3577,7 +3562,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificSetMonitorPower"
|
||||
#endif
|
||||
},
|
||||
{ /* [45] */
|
||||
{ /* [44] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3592,7 +3577,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificSetHdmiFrlLinkConfig"
|
||||
#endif
|
||||
},
|
||||
{ /* [46] */
|
||||
{ /* [45] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3607,7 +3592,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificGetRegionalCrcs"
|
||||
#endif
|
||||
},
|
||||
{ /* [47] */
|
||||
{ /* [46] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3622,7 +3607,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificApplyEdidOverrideV2"
|
||||
#endif
|
||||
},
|
||||
{ /* [48] */
|
||||
{ /* [47] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3637,7 +3622,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificGetHdmiGpuCaps"
|
||||
#endif
|
||||
},
|
||||
{ /* [49] */
|
||||
{ /* [48] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3652,7 +3637,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificDisplayChange"
|
||||
#endif
|
||||
},
|
||||
{ /* [50] */
|
||||
{ /* [49] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3667,7 +3652,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificGetHdmiScdcData"
|
||||
#endif
|
||||
},
|
||||
{ /* [51] */
|
||||
{ /* [50] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3682,7 +3667,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificIsDirectmodeDisplay"
|
||||
#endif
|
||||
},
|
||||
{ /* [52] */
|
||||
{ /* [51] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3697,7 +3682,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificSetHdmiFrlCapacityComputation"
|
||||
#endif
|
||||
},
|
||||
{ /* [53] */
|
||||
{ /* [52] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3712,7 +3697,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificSetSharedGenericPacket"
|
||||
#endif
|
||||
},
|
||||
{ /* [54] */
|
||||
{ /* [53] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3727,7 +3712,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificAcquireSharedGenericPacket"
|
||||
#endif
|
||||
},
|
||||
{ /* [55] */
|
||||
{ /* [54] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3742,7 +3727,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificReleaseSharedGenericPacket"
|
||||
#endif
|
||||
},
|
||||
{ /* [56] */
|
||||
{ /* [55] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3757,7 +3742,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificDispI2cReadWrite"
|
||||
#endif
|
||||
},
|
||||
{ /* [57] */
|
||||
{ /* [56] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3772,7 +3757,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificGetValidHeadWindowAssignment"
|
||||
#endif
|
||||
},
|
||||
{ /* [58] */
|
||||
{ /* [57] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3787,7 +3772,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSpecificDefaultAdaptivesyncDisplay"
|
||||
#endif
|
||||
},
|
||||
{ /* [59] */
|
||||
{ /* [58] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc0u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3802,7 +3787,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdInternalGetHotplugUnplugState"
|
||||
#endif
|
||||
},
|
||||
{ /* [60] */
|
||||
{ /* [59] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3817,7 +3802,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdFrlConfigMacroPad"
|
||||
#endif
|
||||
},
|
||||
{ /* [61] */
|
||||
{ /* [60] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4au)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3832,7 +3817,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDfpGetInfo"
|
||||
#endif
|
||||
},
|
||||
{ /* [62] */
|
||||
{ /* [61] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3847,7 +3832,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDfpGetDisplayportDongleInfo"
|
||||
#endif
|
||||
},
|
||||
{ /* [63] */
|
||||
{ /* [62] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3862,7 +3847,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDfpSetEldAudioCaps"
|
||||
#endif
|
||||
},
|
||||
{ /* [64] */
|
||||
{ /* [63] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3877,7 +3862,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDfpUpdateDynamicDfpCache"
|
||||
#endif
|
||||
},
|
||||
{ /* [65] */
|
||||
{ /* [64] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3892,7 +3877,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDfpSetAudioEnable"
|
||||
#endif
|
||||
},
|
||||
{ /* [66] */
|
||||
{ /* [65] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3907,7 +3892,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDfpAssignSor"
|
||||
#endif
|
||||
},
|
||||
{ /* [67] */
|
||||
{ /* [66] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3922,7 +3907,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDfpGetPadlinkMask"
|
||||
#endif
|
||||
},
|
||||
{ /* [68] */
|
||||
{ /* [67] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3937,7 +3922,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDfpConfigTwoHeadOneOr"
|
||||
#endif
|
||||
},
|
||||
{ /* [69] */
|
||||
{ /* [68] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3952,7 +3937,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDfpDscCrcControl"
|
||||
#endif
|
||||
},
|
||||
{ /* [70] */
|
||||
{ /* [69] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x40u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3967,7 +3952,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDfpInitMuxData"
|
||||
#endif
|
||||
},
|
||||
{ /* [71] */
|
||||
{ /* [70] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3982,7 +3967,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDfpGetDsiModeTiming"
|
||||
#endif
|
||||
},
|
||||
{ /* [72] */
|
||||
{ /* [71] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x46u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -3997,7 +3982,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDfpGetFixedModeTiming"
|
||||
#endif
|
||||
},
|
||||
{ /* [73] */
|
||||
{ /* [72] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4au)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4012,7 +3997,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDfpEdpDriverUnload"
|
||||
#endif
|
||||
},
|
||||
{ /* [74] */
|
||||
{ /* [73] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4027,7 +4012,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSystemSetRegionRamRectangles"
|
||||
#endif
|
||||
},
|
||||
{ /* [75] */
|
||||
{ /* [74] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4042,7 +4027,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdSystemConfigureSafetyInterrupts"
|
||||
#endif
|
||||
},
|
||||
{ /* [76] */
|
||||
{ /* [75] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x48u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4057,7 +4042,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDfpSetForceBlackPixels"
|
||||
#endif
|
||||
},
|
||||
{ /* [77] */
|
||||
{ /* [76] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x844u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4072,7 +4057,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpAuxchCtrl"
|
||||
#endif
|
||||
},
|
||||
{ /* [78] */
|
||||
{ /* [77] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x844u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4087,7 +4072,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpCtrl"
|
||||
#endif
|
||||
},
|
||||
{ /* [79] */
|
||||
{ /* [78] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4102,7 +4087,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpGetLaneData"
|
||||
#endif
|
||||
},
|
||||
{ /* [80] */
|
||||
{ /* [79] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4117,7 +4102,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpSetLaneData"
|
||||
#endif
|
||||
},
|
||||
{ /* [81] */
|
||||
{ /* [80] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4132,7 +4117,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpSetTestpattern"
|
||||
#endif
|
||||
},
|
||||
{ /* [82] */
|
||||
{ /* [81] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4147,7 +4132,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpGetTestpattern"
|
||||
#endif
|
||||
},
|
||||
{ /* [83] */
|
||||
{ /* [82] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4162,7 +4147,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpSetPreemphasisDrivecurrentPostcursor2Data"
|
||||
#endif
|
||||
},
|
||||
{ /* [84] */
|
||||
{ /* [83] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4177,7 +4162,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpGetPreemphasisDrivecurrentPostcursor2Data"
|
||||
#endif
|
||||
},
|
||||
{ /* [85] */
|
||||
{ /* [84] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4192,7 +4177,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpMainLinkCtrl"
|
||||
#endif
|
||||
},
|
||||
{ /* [86] */
|
||||
{ /* [85] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4207,7 +4192,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpSetAudioMuteStream"
|
||||
#endif
|
||||
},
|
||||
{ /* [87] */
|
||||
{ /* [86] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4222,7 +4207,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpTopologyAllocateDisplayId"
|
||||
#endif
|
||||
},
|
||||
{ /* [88] */
|
||||
{ /* [87] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4237,7 +4222,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpTopologyFreeDisplayId"
|
||||
#endif
|
||||
},
|
||||
{ /* [89] */
|
||||
{ /* [88] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4252,7 +4237,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpGetLinkConfig"
|
||||
#endif
|
||||
},
|
||||
{ /* [90] */
|
||||
{ /* [89] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4267,7 +4252,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpGetEDPData"
|
||||
#endif
|
||||
},
|
||||
{ /* [91] */
|
||||
{ /* [90] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4282,7 +4267,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpConfigStream"
|
||||
#endif
|
||||
},
|
||||
{ /* [92] */
|
||||
{ /* [91] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4297,7 +4282,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpSetRateGov"
|
||||
#endif
|
||||
},
|
||||
{ /* [93] */
|
||||
{ /* [92] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4312,7 +4297,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpSetManualDisplayPort"
|
||||
#endif
|
||||
},
|
||||
{ /* [94] */
|
||||
{ /* [93] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4327,7 +4312,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpSetEcf"
|
||||
#endif
|
||||
},
|
||||
{ /* [95] */
|
||||
{ /* [94] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4342,7 +4327,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpSendACT"
|
||||
#endif
|
||||
},
|
||||
{ /* [96] */
|
||||
{ /* [95] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x820046u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4357,7 +4342,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpGetCaps"
|
||||
#endif
|
||||
},
|
||||
{ /* [97] */
|
||||
{ /* [96] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4372,7 +4357,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpGenerateFakeInterrupt"
|
||||
#endif
|
||||
},
|
||||
{ /* [98] */
|
||||
{ /* [97] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4387,7 +4372,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpConfigRadScratchReg"
|
||||
#endif
|
||||
},
|
||||
{ /* [99] */
|
||||
{ /* [98] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4402,7 +4387,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpConfigSingleHeadMultiStream"
|
||||
#endif
|
||||
},
|
||||
{ /* [100] */
|
||||
{ /* [99] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4417,7 +4402,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpSetTriggerSelect"
|
||||
#endif
|
||||
},
|
||||
{ /* [101] */
|
||||
{ /* [100] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4432,7 +4417,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpSetTriggerAll"
|
||||
#endif
|
||||
},
|
||||
{ /* [102] */
|
||||
{ /* [101] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4447,7 +4432,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpGetAuxLogData"
|
||||
#endif
|
||||
},
|
||||
{ /* [103] */
|
||||
{ /* [102] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4462,7 +4447,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpConfigIndexedLinkRates"
|
||||
#endif
|
||||
},
|
||||
{ /* [104] */
|
||||
{ /* [103] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4477,7 +4462,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpSetStereoMSAProperties"
|
||||
#endif
|
||||
},
|
||||
{ /* [105] */
|
||||
{ /* [104] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4492,7 +4477,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpConfigureFec"
|
||||
#endif
|
||||
},
|
||||
{ /* [106] */
|
||||
{ /* [105] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4507,7 +4492,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpConfigMacroPad"
|
||||
#endif
|
||||
},
|
||||
{ /* [107] */
|
||||
{ /* [106] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4522,7 +4507,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpGetGenericInfoframe"
|
||||
#endif
|
||||
},
|
||||
{ /* [108] */
|
||||
{ /* [107] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4537,7 +4522,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpGetMsaAttributes"
|
||||
#endif
|
||||
},
|
||||
{ /* [109] */
|
||||
{ /* [108] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4552,7 +4537,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpSetMSAPropertiesv2"
|
||||
#endif
|
||||
},
|
||||
{ /* [110] */
|
||||
{ /* [109] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4567,7 +4552,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpSetLevelInfoTableData"
|
||||
#endif
|
||||
},
|
||||
{ /* [111] */
|
||||
{ /* [110] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4582,7 +4567,7 @@ static const struct NVOC_EXPORTED_METHOD_DEF __nvoc_exported_method_def_DispComm
|
||||
/*func=*/ "dispcmnCtrlCmdDpGetLevelInfoTableData"
|
||||
#endif
|
||||
},
|
||||
{ /* [112] */
|
||||
{ /* [111] */
|
||||
#if NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
/*pFunc=*/ (void (*)(void)) NULL,
|
||||
#else
|
||||
@@ -4882,7 +4867,7 @@ NV_STATUS __nvoc_up_thunk_Notifier_dispcmnGetOrAllocNotifShare(struct DispCommon
|
||||
|
||||
const struct NVOC_EXPORT_INFO __nvoc_export_info__DispCommon =
|
||||
{
|
||||
/*numEntries=*/ 113,
|
||||
/*numEntries=*/ 112,
|
||||
/*pExportEntries=*/ __nvoc_exported_method_def_DispCommon
|
||||
};
|
||||
|
||||
@@ -5034,11 +5019,6 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) {
|
||||
pThis->__dispcmnCtrlCmdSystemAllocateDisplayBandwidth__ = &dispcmnCtrlCmdSystemAllocateDisplayBandwidth_IMPL;
|
||||
#endif
|
||||
|
||||
// dispcmnCtrlCmdSystemQueryUefiDisplayBandwidth -- exported (id=0x730161)
|
||||
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x4u)
|
||||
pThis->__dispcmnCtrlCmdSystemQueryUefiDisplayBandwidth__ = &dispcmnCtrlCmdSystemQueryUefiDisplayBandwidth_IMPL;
|
||||
#endif
|
||||
|
||||
// dispcmnCtrlCmdSystemInternalAllocateDisplayBandwidth -- exported (id=0x730157)
|
||||
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0xc4u)
|
||||
pThis->__dispcmnCtrlCmdSystemInternalAllocateDisplayBandwidth__ = &dispcmnCtrlCmdSystemInternalAllocateDisplayBandwidth_IMPL;
|
||||
@@ -5483,13 +5463,13 @@ static void __nvoc_init_funcTable_DispCommon_1(DispCommon *pThis) {
|
||||
#if !NVOC_EXPORTED_METHOD_DISABLED_BY_FLAG(0x44u)
|
||||
pThis->__dispcmnCtrlCmdSpecificGetRegionalCrcs__ = &dispcmnCtrlCmdSpecificGetRegionalCrcs_IMPL;
|
||||
#endif
|
||||
} // End __nvoc_init_funcTable_DispCommon_1 with approximately 113 basic block(s).
|
||||
} // End __nvoc_init_funcTable_DispCommon_1 with approximately 112 basic block(s).
|
||||
|
||||
|
||||
// Initialize vtable(s) for 139 virtual method(s).
|
||||
// Initialize vtable(s) for 138 virtual method(s).
|
||||
void __nvoc_init_funcTable_DispCommon(DispCommon *pThis) {
|
||||
|
||||
// Initialize vtable(s) with 113 per-object function pointer(s).
|
||||
// Initialize vtable(s) with 112 per-object function pointer(s).
|
||||
__nvoc_init_funcTable_DispCommon_1(pThis);
|
||||
}
|
||||
|
||||
|
||||
@@ -16,7 +16,7 @@ extern "C" {
|
||||
#endif
|
||||
|
||||
/*
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2025 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-FileCopyrightText: Copyright (c) 1993-2024 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
|
||||
* SPDX-License-Identifier: MIT
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
@@ -1575,7 +1575,7 @@ struct DispCommon {
|
||||
struct DisplayApi *__nvoc_pbase_DisplayApi; // dispapi super
|
||||
struct DispCommon *__nvoc_pbase_DispCommon; // dispcmn
|
||||
|
||||
// Vtable with 113 per-object function pointers
|
||||
// Vtable with 112 per-object function pointers
|
||||
NV_STATUS (*__dispcmnCtrlCmdSpecificGetHdcpState__)(struct DispCommon * /*this*/, NV0073_CTRL_SPECIFIC_GET_HDCP_STATE_PARAMS *); // exported (id=0x730280)
|
||||
NV_STATUS (*__dispcmnCtrlCmdSpecificHdcpCtrl__)(struct DispCommon * /*this*/, NV0073_CTRL_SPECIFIC_HDCP_CTRL_PARAMS *); // exported (id=0x730282)
|
||||
NV_STATUS (*__dispcmnCtrlCmdSpecificGetHdcpRepeaterInfo__)(struct DispCommon * /*this*/, NV0073_CTRL_SPECIFIC_GET_HDCP_REPEATER_INFO_PARAMS *); // exported (id=0x730260)
|
||||
@@ -1599,7 +1599,6 @@ struct DispCommon {
|
||||
NV_STATUS (*__dispcmnCtrlCmdSystemQueryDisplayIdsWithMux__)(struct DispCommon * /*this*/, NV0073_CTRL_CMD_SYSTEM_QUERY_DISPLAY_IDS_WITH_MUX_PARAMS *); // exported (id=0x73013d)
|
||||
NV_STATUS (*__dispcmnCtrlCmdSystemCheckSidebandI2cSupport__)(struct DispCommon * /*this*/, NV0073_CTRL_CMD_SYSTEM_CHECK_SIDEBAND_I2C_SUPPORT_PARAMS *); // exported (id=0x73014b)
|
||||
NV_STATUS (*__dispcmnCtrlCmdSystemAllocateDisplayBandwidth__)(struct DispCommon * /*this*/, NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS *); // exported (id=0x730143)
|
||||
NV_STATUS (*__dispcmnCtrlCmdSystemQueryUefiDisplayBandwidth__)(struct DispCommon * /*this*/, NV0073_CTRL_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH_PARAMS *); // exported (id=0x730161)
|
||||
NV_STATUS (*__dispcmnCtrlCmdSystemInternalAllocateDisplayBandwidth__)(struct DispCommon * /*this*/, NV0073_CTRL_SYSTEM_INTERNAL_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS *); // exported (id=0x730157)
|
||||
NV_STATUS (*__dispcmnCtrlCmdSystemGetHotplugConfig__)(struct DispCommon * /*this*/, NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS *); // exported (id=0x730109)
|
||||
NV_STATUS (*__dispcmnCtrlCmdSystemGetHotplugEventConfig__)(struct DispCommon * /*this*/, NV0073_CTRL_SYSTEM_HOTPLUG_EVENT_CONFIG_PARAMS *); // exported (id=0x730144)
|
||||
@@ -1809,8 +1808,6 @@ NV_STATUS __nvoc_objCreate_DispCommon(DispCommon**, Dynamic*, NvU32, struct CALL
|
||||
#define dispcmnCtrlCmdSystemCheckSidebandI2cSupport(pDispCommon, pParams) dispcmnCtrlCmdSystemCheckSidebandI2cSupport_DISPATCH(pDispCommon, pParams)
|
||||
#define dispcmnCtrlCmdSystemAllocateDisplayBandwidth_FNPTR(pDispCommon) pDispCommon->__dispcmnCtrlCmdSystemAllocateDisplayBandwidth__
|
||||
#define dispcmnCtrlCmdSystemAllocateDisplayBandwidth(pDispCommon, pParams) dispcmnCtrlCmdSystemAllocateDisplayBandwidth_DISPATCH(pDispCommon, pParams)
|
||||
#define dispcmnCtrlCmdSystemQueryUefiDisplayBandwidth_FNPTR(pDispCommon) pDispCommon->__dispcmnCtrlCmdSystemQueryUefiDisplayBandwidth__
|
||||
#define dispcmnCtrlCmdSystemQueryUefiDisplayBandwidth(pDispCommon, pParams) dispcmnCtrlCmdSystemQueryUefiDisplayBandwidth_DISPATCH(pDispCommon, pParams)
|
||||
#define dispcmnCtrlCmdSystemInternalAllocateDisplayBandwidth_FNPTR(pDispCommon) pDispCommon->__dispcmnCtrlCmdSystemInternalAllocateDisplayBandwidth__
|
||||
#define dispcmnCtrlCmdSystemInternalAllocateDisplayBandwidth(pDispCommon, pParams) dispcmnCtrlCmdSystemInternalAllocateDisplayBandwidth_DISPATCH(pDispCommon, pParams)
|
||||
#define dispcmnCtrlCmdSystemGetHotplugConfig_FNPTR(pDispCommon) pDispCommon->__dispcmnCtrlCmdSystemGetHotplugConfig__
|
||||
@@ -2135,10 +2132,6 @@ static inline NV_STATUS dispcmnCtrlCmdSystemAllocateDisplayBandwidth_DISPATCH(st
|
||||
return pDispCommon->__dispcmnCtrlCmdSystemAllocateDisplayBandwidth__(pDispCommon, pParams);
|
||||
}
|
||||
|
||||
static inline NV_STATUS dispcmnCtrlCmdSystemQueryUefiDisplayBandwidth_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH_PARAMS *pParams) {
|
||||
return pDispCommon->__dispcmnCtrlCmdSystemQueryUefiDisplayBandwidth__(pDispCommon, pParams);
|
||||
}
|
||||
|
||||
static inline NV_STATUS dispcmnCtrlCmdSystemInternalAllocateDisplayBandwidth_DISPATCH(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_INTERNAL_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS *pParams) {
|
||||
return pDispCommon->__dispcmnCtrlCmdSystemInternalAllocateDisplayBandwidth__(pDispCommon, pParams);
|
||||
}
|
||||
@@ -2645,8 +2638,6 @@ NV_STATUS dispcmnCtrlCmdSystemCheckSidebandI2cSupport_IMPL(struct DispCommon *pD
|
||||
|
||||
NV_STATUS dispcmnCtrlCmdSystemAllocateDisplayBandwidth_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS *pParams);
|
||||
|
||||
NV_STATUS dispcmnCtrlCmdSystemQueryUefiDisplayBandwidth_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH_PARAMS *pParams);
|
||||
|
||||
NV_STATUS dispcmnCtrlCmdSystemInternalAllocateDisplayBandwidth_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_INTERNAL_ALLOCATE_DISPLAY_BANDWIDTH_PARAMS *pParams);
|
||||
|
||||
NV_STATUS dispcmnCtrlCmdSystemGetHotplugConfig_IMPL(struct DispCommon *pDispCommon, NV0073_CTRL_SYSTEM_GET_SET_HOTPLUG_CONFIG_PARAMS *pHotplugParams);
|
||||
|
||||
@@ -191,22 +191,6 @@ static inline NvBool gpuarchSupportsIgpuRg(struct GpuArch *pGpuArch) {
|
||||
|
||||
#define gpuarchSupportsIgpuRg_HAL(pGpuArch) gpuarchSupportsIgpuRg(pGpuArch)
|
||||
|
||||
static inline NvU32 gpuarchGetGpcFuseStatusOffset_4a4dee(struct GpuArch *pGpuArch) {
|
||||
return 0;
|
||||
}
|
||||
|
||||
|
||||
#ifdef __nvoc_gpu_arch_h_disabled
|
||||
static inline NvU32 gpuarchGetGpcFuseStatusOffset(struct GpuArch *pGpuArch) {
|
||||
NV_ASSERT_FAILED_PRECOMP("GpuArch was disabled!");
|
||||
return 0;
|
||||
}
|
||||
#else //__nvoc_gpu_arch_h_disabled
|
||||
#define gpuarchGetGpcFuseStatusOffset(pGpuArch) gpuarchGetGpcFuseStatusOffset_4a4dee(pGpuArch)
|
||||
#endif //__nvoc_gpu_arch_h_disabled
|
||||
|
||||
#define gpuarchGetGpcFuseStatusOffset_HAL(pGpuArch) gpuarchGetGpcFuseStatusOffset(pGpuArch)
|
||||
|
||||
NV_STATUS gpuarchConstruct_IMPL(struct GpuArch *arg_pGpuArch, NvU32 arg_chipArch, NvU32 arg_chipImpl, NvU32 arg_hidrev, TEGRA_CHIP_TYPE arg_tegraType);
|
||||
|
||||
#define __nvoc_gpuarchConstruct(arg_pGpuArch, arg_chipArch, arg_chipImpl, arg_hidrev, arg_tegraType) gpuarchConstruct_IMPL(arg_pGpuArch, arg_chipArch, arg_chipImpl, arg_hidrev, arg_tegraType)
|
||||
|
||||
@@ -332,12 +332,7 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) {
|
||||
pThis->setProperty(pThis, PDB_PROP_GPU_RUSD_DISABLE_CLK_PUBLIC_DOMAIN_INFO, NV_FALSE);
|
||||
}
|
||||
pThis->setProperty(pThis, PDB_PROP_GPU_RECOVERY_REBOOT_REQUIRED, NV_FALSE);
|
||||
|
||||
// NVOC Property Hal field -- PDB_PROP_GPU_ALLOC_ISO_SYS_MEM_FROM_CARVEOUT
|
||||
// default
|
||||
{
|
||||
pThis->setProperty(pThis, PDB_PROP_GPU_ALLOC_ISO_SYS_MEM_FROM_CARVEOUT, NV_FALSE);
|
||||
}
|
||||
pThis->setProperty(pThis, PDB_PROP_GPU_ALLOC_ISO_SYS_MEM_FROM_CARVEOUT, NV_FALSE);
|
||||
|
||||
pThis->deviceInstance = 32;
|
||||
|
||||
@@ -429,9 +424,6 @@ void __nvoc_init_dataField_OBJGPU(OBJGPU *pThis) {
|
||||
pThis->bInstanceMemoryAlwaysCached = NV_TRUE;
|
||||
}
|
||||
|
||||
// Hal field -- bAPageSizeAllocRetryEnabled
|
||||
pThis->bAPageSizeAllocRetryEnabled = NV_FALSE;
|
||||
|
||||
// Hal field -- bComputePolicyTimesliceSupported
|
||||
// default
|
||||
{
|
||||
|
||||
@@ -1293,7 +1293,6 @@ struct OBJGPU {
|
||||
NvBool bClientRmAllocatedCtxBuffer;
|
||||
NvBool bEccPageRetirementWithSliAllowed;
|
||||
NvBool bInstanceMemoryAlwaysCached;
|
||||
NvBool bAPageSizeAllocRetryEnabled;
|
||||
NvBool bUseRpcSimEscapes;
|
||||
NvBool bRmProfilingPrivileged;
|
||||
NvBool bGeforceSmb;
|
||||
|
||||
@@ -567,20 +567,6 @@ static inline NV_STATUS kdispArbAndAllocDisplayBandwidth(struct OBJGPU *pGpu, st
|
||||
|
||||
#define kdispArbAndAllocDisplayBandwidth_HAL(pGpu, pKernelDisplay, iccBwClient, minRequiredIsoBandwidthKBPS, minRequiredFloorBandwidthKBPS) kdispArbAndAllocDisplayBandwidth(pGpu, pKernelDisplay, iccBwClient, minRequiredIsoBandwidthKBPS, minRequiredFloorBandwidthKBPS)
|
||||
|
||||
NV_STATUS kdispGetUefiDisplayBandwidth_v04_02(struct OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 *uefiIsoBandwidthKBPS, NvU32 *uefiFloorBandwidthKBPS);
|
||||
|
||||
|
||||
#ifdef __nvoc_kern_disp_h_disabled
|
||||
static inline NV_STATUS kdispGetUefiDisplayBandwidth(struct OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, NvU32 *uefiIsoBandwidthKBPS, NvU32 *uefiFloorBandwidthKBPS) {
|
||||
NV_ASSERT_FAILED_PRECOMP("KernelDisplay was disabled!");
|
||||
return NV_ERR_NOT_SUPPORTED;
|
||||
}
|
||||
#else //__nvoc_kern_disp_h_disabled
|
||||
#define kdispGetUefiDisplayBandwidth(pGpu, pKernelDisplay, uefiIsoBandwidthKBPS, uefiFloorBandwidthKBPS) kdispGetUefiDisplayBandwidth_v04_02(pGpu, pKernelDisplay, uefiIsoBandwidthKBPS, uefiFloorBandwidthKBPS)
|
||||
#endif //__nvoc_kern_disp_h_disabled
|
||||
|
||||
#define kdispGetUefiDisplayBandwidth_HAL(pGpu, pKernelDisplay, uefiIsoBandwidthKBPS, uefiFloorBandwidthKBPS) kdispGetUefiDisplayBandwidth(pGpu, pKernelDisplay, uefiIsoBandwidthKBPS, uefiFloorBandwidthKBPS)
|
||||
|
||||
NV_STATUS kdispSetPushBufferParamsToPhysical_IMPL(struct OBJGPU *pGpu, struct KernelDisplay *pKernelDisplay, struct DispChannel *pDispChannel, NvHandle hObjectBuffer, struct ContextDma *pBufferContextDma, NvU32 hClass, NvU32 channelInstance, DISPCHNCLASS internalDispChnClass, ChannelPBSize channelPBSize, NvU32 subDeviceId);
|
||||
|
||||
|
||||
|
||||
@@ -381,11 +381,7 @@ typedef struct ADDRESS_TRANSLATION_ *ADDRESS_TRANSLATION;
|
||||
// 32-bit addressable.
|
||||
#define MEMDESC_FLAGS_ALLOC_32BIT_ADDRESSABLE NVBIT64(41)
|
||||
|
||||
//
|
||||
// This flag causes linux to not try as hard to reclaim used pages. Useful when
|
||||
// we are retrying with successively smaller page sizes as in sysmemConstruct.
|
||||
//
|
||||
#define MEMDESC_FLAGS_ALLOC_NO_RECLAIM NVBIT64(42)
|
||||
// unused NVBIT64(42)
|
||||
|
||||
//
|
||||
// If this flag is set then it indicates that the memory associated with
|
||||
@@ -425,7 +421,6 @@ typedef struct ADDRESS_TRANSLATION_ *ADDRESS_TRANSLATION;
|
||||
//
|
||||
#define MEMDESC_FLAGS_ALLOC_AS_LOCALIZED NVBIT64(50)
|
||||
|
||||
// Indicate whether memdesc tracks the memory allocated from the scanout-carevout heap.
|
||||
#define MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT NVBIT64(51)
|
||||
|
||||
// Force-compress pte kind when mapping with virtual pte kind
|
||||
@@ -441,9 +436,6 @@ typedef struct ADDRESS_TRANSLATION_ *ADDRESS_TRANSLATION;
|
||||
// Indicate if memdesc is allocated for non IO-coherent memory.
|
||||
#define MEMDESC_FLAGS_NON_IO_COHERENT NVBIT64(54)
|
||||
|
||||
// Indicate if memdesc is tracking the uefi carveout memory.
|
||||
#define MEMDESC_FLAGS_ALLOC_FROM_UEFI_CARVEOUT NVBIT64(55)
|
||||
|
||||
//
|
||||
// RM internal allocations owner tags
|
||||
// Total 200 tags are introduced, out of which some are already
|
||||
@@ -1219,13 +1211,6 @@ NV_STATUS memdescFillMemdescForPhysAttr(MEMORY_DESCRIPTOR *pMemDesc, ADDRESS_TRA
|
||||
NvBool memdescIsEgm(MEMORY_DESCRIPTOR *pMemDesc);
|
||||
NvU64 memdescGetAdjustedPageSize(MEMORY_DESCRIPTOR *pMemDesc);
|
||||
|
||||
static inline NvBool
|
||||
memdescIsCarveoutMemory(MEMORY_DESCRIPTOR *pMemDesc)
|
||||
{
|
||||
return !!(pMemDesc->_flags & (MEMDESC_FLAGS_ALLOC_FROM_SCANOUT_CARVEOUT |
|
||||
MEMDESC_FLAGS_ALLOC_FROM_UEFI_CARVEOUT));
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Get PTE kind
|
||||
*
|
||||
|
||||
@@ -2324,8 +2324,6 @@ static inline NV_STATUS memmgrCalculateHeapOffsetWithGSP(OBJGPU *pGpu, struct Me
|
||||
|
||||
#define memmgrCalculateHeapOffsetWithGSP_HAL(pGpu, pMemoryManager, offset) memmgrCalculateHeapOffsetWithGSP(pGpu, pMemoryManager, offset)
|
||||
|
||||
NV_STATUS memmgrGetCarveoutRegionInfo_KERNEL(POBJGPU pGpu, struct MemoryManager *pMemoryManager, NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS *pParams);
|
||||
|
||||
static inline NV_STATUS memmgrGetCarveoutRegionInfo_56cd7a(POBJGPU pGpu, struct MemoryManager *pMemoryManager, NV2080_CTRL_FB_GET_CARVEOUT_REGION_INFO_PARAMS *pParams) {
|
||||
return NV_OK;
|
||||
}
|
||||
@@ -2337,7 +2335,7 @@ static inline NV_STATUS memmgrGetCarveoutRegionInfo(POBJGPU pGpu, struct MemoryM
|
||||
return NV_ERR_NOT_SUPPORTED;
|
||||
}
|
||||
#else //__nvoc_mem_mgr_h_disabled
|
||||
#define memmgrGetCarveoutRegionInfo(pGpu, pMemoryManager, pParams) memmgrGetCarveoutRegionInfo_KERNEL(pGpu, pMemoryManager, pParams)
|
||||
#define memmgrGetCarveoutRegionInfo(pGpu, pMemoryManager, pParams) memmgrGetCarveoutRegionInfo_56cd7a(pGpu, pMemoryManager, pParams)
|
||||
#endif //__nvoc_mem_mgr_h_disabled
|
||||
|
||||
#define memmgrGetCarveoutRegionInfo_HAL(pGpu, pMemoryManager, pParams) memmgrGetCarveoutRegionInfo(pGpu, pMemoryManager, pParams)
|
||||
|
||||
@@ -676,7 +676,6 @@ NV_STATUS osTegraSocBpmpSendMrq(OBJGPU *pGpu,
|
||||
NvS32 *pApiRet);
|
||||
NV_STATUS osMapGsc(NvU64 gsc_base, NvU64 *va);
|
||||
NV_STATUS osTegraSocGetImpImportData(OBJGPU *pGpu, TEGRA_IMP_IMPORT_DATA *pTegraImpImportData);
|
||||
NV_STATUS osTegraSocGetImpUefiData(OS_GPU_INFO *pOsGpuInfo, NvU32 *pIsoBwKbps, NvU32 *pFloorBwKbps);
|
||||
NV_STATUS osTegraSocEnableDisableRfl(OS_GPU_INFO *pOsGpuInfo, NvBool bEnable);
|
||||
NV_STATUS osTegraAllocateDisplayBandwidth(OS_GPU_INFO *pOsGpuInfo,
|
||||
NvU32 averageBandwidthKBPS,
|
||||
@@ -847,10 +846,6 @@ NV_STATUS osTegraDceRegisterIpcClient(NvU32 interfaceType, void *usrCtx,
|
||||
NV_STATUS osTegraDceClientIpcSendRecv(NvU32 clientId, void *msg,
|
||||
NvU32 msgLength);
|
||||
NV_STATUS osTegraDceUnregisterIpcClient(NvU32 clientId);
|
||||
NV_STATUS osTegraSocGetDispClockRates(OS_GPU_INFO *pOsGpuInfo,
|
||||
NvU32 *pMaxDispClkRateDisppll,
|
||||
NvU32 *pMaxDispClkRateSppllClkouta,
|
||||
NvU32 *pMaxHubClkRateSppllClkoutb);
|
||||
|
||||
//
|
||||
// Define OS-layer specific type instead of #include "clk_domains.h" for
|
||||
|
||||
@@ -113,9 +113,6 @@ typedef rpc_display_modeset_v01_00 rpc_display_modeset_v;
|
||||
typedef struct rpc_dce_rm_init_v01_00
|
||||
{
|
||||
NvBool bInit;
|
||||
NvU32 maxDispClkRateDisppll;
|
||||
NvU32 maxDispClkRateSppllClkouta;
|
||||
NvU32 maxHubClkRateSppllClkoutb;
|
||||
NvU32 hInternalClient;
|
||||
} rpc_dce_rm_init_v01_00;
|
||||
|
||||
|
||||
@@ -76,7 +76,6 @@ struct THREAD_STATE_NODE
|
||||
*/
|
||||
NvU32 threadSeqId;
|
||||
NvBool bValid;
|
||||
NvBool bUsingHeap;
|
||||
THREAD_TIMEOUT_STATE timeout;
|
||||
NvU32 cpuNum;
|
||||
NvU32 flags;
|
||||
@@ -209,7 +208,6 @@ void threadStateOnlyProcessWorkISRAndDeferredIntHandler(THREAD_STATE_NODE
|
||||
void threadStateOnlyFreeISRAndDeferredIntHandler(THREAD_STATE_NODE *, OBJGPU*, NvU32);
|
||||
void threadStateFreeISRAndDeferredIntHandler(THREAD_STATE_NODE *, OBJGPU*, NvU32);
|
||||
void threadStateInit(THREAD_STATE_NODE *pThreadNode, NvU32 flags);
|
||||
THREAD_STATE_NODE* threadStateAlloc(NvU32 flags);
|
||||
void threadStateFree(THREAD_STATE_NODE *pThreadNode, NvU32 flags);
|
||||
|
||||
NV_STATUS threadStateGetCurrent(THREAD_STATE_NODE **ppThreadNode, OBJGPU *pGpu);
|
||||
|
||||
@@ -157,19 +157,6 @@ extern "C" {
|
||||
|
||||
#define MAKE_NV_PRINTF_STR(str) str
|
||||
|
||||
#if NVOS_IS_DCECORE
|
||||
#define NV_PRINTF_EX(module, level, format, ...) \
|
||||
do \
|
||||
{ \
|
||||
if (NV_PRINTF_LEVEL_ENABLED(level)) \
|
||||
{ \
|
||||
LIBOS_LOG_INTERNAL(LIBOS_LOG_ENTRY, level, \
|
||||
format, ##__VA_ARGS__); \
|
||||
} \
|
||||
NV_PRINTF_STRING(module, level, format, ##__VA_ARGS__); \
|
||||
} while (0)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @def NV_PRINTF(level, format, args...)
|
||||
* @brief Standard formatted printing/logging interface.
|
||||
|
||||
@@ -1528,7 +1528,7 @@
|
||||
// Set watchdog timeout value for the libos user task watchdog
|
||||
#define NV_REG_STR_RM_GSP_LIBOS_WATCHDOG_TIMEOUT "RmGspLibosWatchdogTimeOut"
|
||||
#define NV_REG_STR_RM_GSP_LIBOS_WATCHDOG_TIMEOUT_MIN 0x00000000
|
||||
#define NV_REG_STR_RM_GSP_LIBOS_WATCHDOG_TIMEOUT_DEFAULT 0x0000000A
|
||||
#define NV_REG_STR_RM_GSP_LIBOS_WATCHDOG_TIMEOUT_DEFAULT 0x00000005
|
||||
|
||||
#define NV_REG_STR_RM_DO_LOG_RC_EVENTS "RmLogonRC"
|
||||
// Type Dword
|
||||
|
||||
@@ -505,21 +505,27 @@ static void _threadStateLogInitCaller(THREAD_STATE_NODE *pThreadNode, NvU64 func
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Common initialization logic for both stack and heap thread state nodes
|
||||
* @brief Initialize a threadState for regular threads (non-interrupt context)
|
||||
*
|
||||
* @param[in/out] pThreadNode The node to initialize
|
||||
* @param[in] flags Thread state flags
|
||||
* @param[in] bUsingHeap NV_TRUE if heap-allocated, NV_FALSE if stack-allocated
|
||||
* @param[in/out] pThreadNode
|
||||
* @param[in] flags
|
||||
*
|
||||
* @return NV_OK on success, error code on failure
|
||||
*/
|
||||
static NV_STATUS _threadStateInitCommon(THREAD_STATE_NODE *pThreadNode, NvU32 flags, NvBool bUsingHeap)
|
||||
void threadStateInit(THREAD_STATE_NODE *pThreadNode, NvU32 flags)
|
||||
{
|
||||
NV_STATUS rmStatus;
|
||||
NvU64 funcAddr;
|
||||
|
||||
// Isrs should be using threadStateIsrInit().
|
||||
NV_ASSERT((flags & (THREAD_STATE_FLAGS_IS_ISR_LOCKLESS |
|
||||
THREAD_STATE_FLAGS_IS_ISR |
|
||||
THREAD_STATE_FLAGS_DEFERRED_INT_HANDLER_RUNNING)) == 0);
|
||||
|
||||
// Check to see if ThreadState is enabled
|
||||
if (!(threadStateDatabase.setupFlags & THREAD_STATE_SETUP_FLAGS_ENABLED))
|
||||
return;
|
||||
|
||||
portMemSet(pThreadNode, 0, sizeof(*pThreadNode));
|
||||
pThreadNode->bUsingHeap = bUsingHeap;
|
||||
pThreadNode->threadSeqId = portAtomicIncrementU32(&threadStateDatabase.threadSeqCntr);
|
||||
pThreadNode->cpuNum = osGetCurrentProcessorNumber();
|
||||
pThreadNode->flags = flags;
|
||||
@@ -537,10 +543,9 @@ static NV_STATUS _threadStateInitCommon(THREAD_STATE_NODE *pThreadNode, NvU32 fl
|
||||
|
||||
rmStatus = osGetCurrentThread(&pThreadNode->threadId);
|
||||
if (rmStatus != NV_OK)
|
||||
return rmStatus;
|
||||
return;
|
||||
|
||||
NV_ASSERT_OR_RETURN(pThreadNode->cpuNum < threadStateDatabase.maxCPUs,
|
||||
NV_ERR_INVALID_STATE);
|
||||
NV_ASSERT_OR_RETURN_VOID(pThreadNode->cpuNum < threadStateDatabase.maxCPUs);
|
||||
|
||||
funcAddr = (NvU64) (NV_RETURN_ADDRESS());
|
||||
|
||||
@@ -550,23 +555,27 @@ static NV_STATUS _threadStateInitCommon(THREAD_STATE_NODE *pThreadNode, NvU32 fl
|
||||
// Reset the threadId as insertion failed. bValid is already NV_FALSE
|
||||
pThreadNode->threadId = 0;
|
||||
portSyncSpinlockRelease(threadStateDatabase.spinlock);
|
||||
return NV_ERR_GENERIC;
|
||||
return;
|
||||
}
|
||||
else
|
||||
{
|
||||
pThreadNode->bValid = NV_TRUE;
|
||||
rmStatus = NV_OK;
|
||||
}
|
||||
|
||||
pThreadNode->bValid = NV_TRUE;
|
||||
_threadStateLogInitCaller(pThreadNode, funcAddr);
|
||||
|
||||
portSyncSpinlockRelease(threadStateDatabase.spinlock);
|
||||
|
||||
_threadStatePrintInfo(pThreadNode);
|
||||
|
||||
NV_ASSERT(rmStatus == NV_OK);
|
||||
threadPriorityStateAlloc();
|
||||
|
||||
if (TLS_MIRROR_THREADSTATE)
|
||||
{
|
||||
THREAD_STATE_NODE **pTls = (THREAD_STATE_NODE **)tlsEntryAcquire(TLS_ENTRY_ID_THREADSTATE);
|
||||
NV_ASSERT_OR_RETURN(pTls != NULL, NV_ERR_INVALID_STATE);
|
||||
|
||||
NV_ASSERT_OR_RETURN_VOID(pTls != NULL);
|
||||
if (*pTls != NULL)
|
||||
{
|
||||
NV_PRINTF(LEVEL_WARNING,
|
||||
@@ -575,66 +584,6 @@ static NV_STATUS _threadStateInitCommon(THREAD_STATE_NODE *pThreadNode, NvU32 fl
|
||||
}
|
||||
*pTls = pThreadNode;
|
||||
}
|
||||
return NV_OK;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Initialize a threadState for regular threads (non-interrupt context)
|
||||
* Use the new UAF-safe API for new code, threadStateAlloc().
|
||||
* @param[in/out] pThreadNode
|
||||
* @param[in] flags
|
||||
*
|
||||
*/
|
||||
void threadStateInit(THREAD_STATE_NODE *pThreadNode, NvU32 flags)
|
||||
{
|
||||
// Isrs should be using threadStateIsrInit().
|
||||
NV_ASSERT_OR_RETURN_VOID((flags & (THREAD_STATE_FLAGS_IS_ISR_LOCKLESS |
|
||||
THREAD_STATE_FLAGS_IS_ISR |
|
||||
THREAD_STATE_FLAGS_DEFERRED_INT_HANDLER_RUNNING)) == 0);
|
||||
|
||||
// Check to see if ThreadState is enabled
|
||||
if (!(threadStateDatabase.setupFlags & THREAD_STATE_SETUP_FLAGS_ENABLED))
|
||||
return;
|
||||
|
||||
// Use common initialization logic (stack-allocated)
|
||||
// Note: Legacy void API ignores errors for backward compatibility
|
||||
_threadStateInitCommon(pThreadNode, flags, NV_FALSE);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Allocate a heap-based threadState
|
||||
* @param[in] flags Thread state flags
|
||||
*
|
||||
* @return Heap-allocated THREAD_STATE_NODE* on success, NULL on failure
|
||||
*/
|
||||
THREAD_STATE_NODE* threadStateAlloc(NvU32 flags)
|
||||
{
|
||||
THREAD_STATE_NODE *pHeapNode;
|
||||
NV_STATUS rmStatus;
|
||||
|
||||
// Isrs should be using threadStateIsrInit().
|
||||
NV_ASSERT_OR_RETURN((flags & (THREAD_STATE_FLAGS_IS_ISR_LOCKLESS |
|
||||
THREAD_STATE_FLAGS_IS_ISR |
|
||||
THREAD_STATE_FLAGS_DEFERRED_INT_HANDLER_RUNNING)) == 0, NULL);
|
||||
|
||||
// Check to see if ThreadState is enabled
|
||||
if (!(threadStateDatabase.setupFlags & THREAD_STATE_SETUP_FLAGS_ENABLED))
|
||||
return NULL;
|
||||
|
||||
// Allocate heap node directly
|
||||
pHeapNode = portMemAllocNonPaged(sizeof(THREAD_STATE_NODE));
|
||||
if (pHeapNode == NULL)
|
||||
return NULL;
|
||||
|
||||
rmStatus = _threadStateInitCommon(pHeapNode, flags, NV_TRUE);
|
||||
if (rmStatus != NV_OK)
|
||||
goto cleanup_heap;
|
||||
|
||||
return pHeapNode;
|
||||
|
||||
cleanup_heap:
|
||||
portMemFree(pHeapNode);
|
||||
return NULL;
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -925,12 +874,6 @@ void threadStateFree(THREAD_STATE_NODE *pThreadNode, NvU32 flags)
|
||||
r);
|
||||
}
|
||||
}
|
||||
|
||||
// Free heap memory if this node was heap-allocated
|
||||
if (pThreadNode->bUsingHeap)
|
||||
{
|
||||
portMemFree(pThreadNode);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@@ -644,9 +644,6 @@ rpcDceRmInit_dce
|
||||
OBJGPU *pGpu = (OBJGPU*)pRmApi->pPrivateContext;
|
||||
OBJRPC *pRpc = GPU_GET_RPC(pGpu);
|
||||
DceClient *pDceClientrm = GPU_GET_DCECLIENTRM(pGpu);
|
||||
NvU32 maxDispClkRateDisppll = 0;
|
||||
NvU32 maxDispClkRateSppllClkouta = 0;
|
||||
NvU32 maxHubClkRateSppllClkoutb = 0;
|
||||
|
||||
rpc_generic_union *msg_data;
|
||||
NV_STATUS status = NV_ERR_NOT_SUPPORTED;
|
||||
@@ -667,20 +664,7 @@ rpcDceRmInit_dce
|
||||
goto done;
|
||||
}
|
||||
|
||||
if (bInit)
|
||||
{
|
||||
status = osTegraSocGetDispClockRates(pGpu->pOsGpuInfo, &maxDispClkRateDisppll, &maxDispClkRateSppllClkouta, &maxHubClkRateSppllClkoutb);
|
||||
if (status != NV_OK)
|
||||
{
|
||||
NV_PRINTF(LEVEL_INFO, "NVRM_RPC_DCE: Retrieving disp clocks max rate Failed [0x%x]\n", status);
|
||||
}
|
||||
}
|
||||
|
||||
rpc_params->bInit = bInit;
|
||||
rpc_params->maxDispClkRateDisppll = maxDispClkRateDisppll;
|
||||
rpc_params->maxDispClkRateSppllClkouta = maxDispClkRateSppllClkouta;
|
||||
rpc_params->maxHubClkRateSppllClkoutb = maxHubClkRateSppllClkoutb;
|
||||
|
||||
rpc_params->bInit = bInit;
|
||||
status = _dceRpcIssueAndWait(pRmApi);
|
||||
if (status != NV_OK)
|
||||
{
|
||||
|
||||
@@ -146,38 +146,3 @@ typedef struct
|
||||
return status;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Retrieves display bandwidth values set by UEFI
|
||||
*
|
||||
* @param[in] pGpu OBJGPU pointer
|
||||
* @param[in] pKernelDisplay KernelDisplay pointer
|
||||
* @param[out] uefiIsoBandwidthKBPS ISO BW set by UEFI (KB/sec)
|
||||
* @param[out] uefiFloorBandwidthKBPS dramclk freq * pipe width set by UEFI (KB/sec)
|
||||
*
|
||||
* @returns NV_OK if successful,
|
||||
* NV_ERR_NOT_SUPPORTED if the functionality is not available, or
|
||||
* NV_ERR_GENERIC if some other kind of error occurred.
|
||||
*/
|
||||
NV_STATUS
|
||||
kdispGetUefiDisplayBandwidth_v04_02
|
||||
(
|
||||
OBJGPU *pGpu,
|
||||
KernelDisplay *pKernelDisplay,
|
||||
NvU32 *uefiIsoBandwidthKBPS,
|
||||
NvU32 *uefiFloorBandwidthKBPS
|
||||
)
|
||||
{
|
||||
NV_STATUS status = NV_OK;
|
||||
|
||||
status = osTegraSocGetImpUefiData(pGpu->pOsGpuInfo, uefiIsoBandwidthKBPS, uefiFloorBandwidthKBPS);
|
||||
if (status == NV_OK)
|
||||
{
|
||||
NV_PRINTF(LEVEL_INFO, "UEFI has set ISO BW = %u KBPS, floor BW = %u KBPS", *uefiIsoBandwidthKBPS, *uefiFloorBandwidthKBPS);
|
||||
}
|
||||
else
|
||||
{
|
||||
NV_PRINTF(LEVEL_ERROR, "Unable to retrieve UEFI set ISO BW and floor BW");
|
||||
}
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
@@ -173,49 +173,6 @@ dispcmnCtrlCmdSystemAllocateDisplayBandwidth_IMPL
|
||||
return status;
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Query Display Bandwidth values set by UEFI.
|
||||
*/
|
||||
NV_STATUS
|
||||
dispcmnCtrlCmdSystemQueryUefiDisplayBandwidth_IMPL
|
||||
(
|
||||
DispCommon *pDispCommon,
|
||||
NV0073_CTRL_SYSTEM_QUERY_UEFI_DISPLAY_BANDWIDTH_PARAMS *pParams
|
||||
)
|
||||
{
|
||||
OBJGPU *pGpu;
|
||||
KernelDisplay *pKernelDisplay;
|
||||
NV_STATUS status;
|
||||
|
||||
// client gave us a subdevice #: get right pGpu for it
|
||||
status = dispapiSetUnicastAndSynchronize_HAL(
|
||||
staticCast(pDispCommon, DisplayApi),
|
||||
DISPAPI_GET_GPUGRP(pDispCommon),
|
||||
&pGpu,
|
||||
NULL,
|
||||
pParams->subDeviceInstance);
|
||||
if (status != NV_OK)
|
||||
{
|
||||
return status;
|
||||
}
|
||||
|
||||
status = dispapiValidateRmctrlPriv(pGpu);
|
||||
if (status != NV_OK)
|
||||
{
|
||||
return status;
|
||||
}
|
||||
|
||||
pKernelDisplay = GPU_GET_KERNEL_DISPLAY(pGpu);
|
||||
|
||||
status =
|
||||
kdispGetUefiDisplayBandwidth_HAL(pGpu,
|
||||
pKernelDisplay,
|
||||
&pParams->isoBandwidthKBPS,
|
||||
&pParams->floorBandwidthKBPS);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
NV_STATUS
|
||||
dispcmnCtrlCmdSystemGetVblankEnable_IMPL
|
||||
(
|
||||
|
||||
@@ -21,7 +21,6 @@
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include "class/cl003e.h"
|
||||
#include "class/cl0040.h" /* NV01_MEMORY_LOCAL_USER */
|
||||
#include "class/cl84a0.h" /* NV01_MEMORY_LIST_XXX */
|
||||
#include "class/cl00b1.h" /* NV01_MEMORY_HW_RESOURCES */
|
||||
@@ -522,31 +521,6 @@ done:
|
||||
return NV_OK;
|
||||
}
|
||||
|
||||
static NvBool _checkVidmemClassValidity(RsResourceRef *pResourceRef,
|
||||
Memory *pMemory)
|
||||
{
|
||||
if ((pResourceRef->externalClassId == NV01_MEMORY_LOCAL_USER ||
|
||||
pResourceRef->externalClassId == NV01_MEMORY_LIST_FBMEM ||
|
||||
pResourceRef->externalClassId == NV01_MEMORY_LIST_OBJECT) &&
|
||||
(pMemory->categoryClassId == NV01_MEMORY_LOCAL_USER))
|
||||
{
|
||||
return NV_TRUE;
|
||||
}
|
||||
return NV_FALSE;
|
||||
}
|
||||
static NvBool _checkSysMemClassValidity(RsResourceRef *pResourceRef,
|
||||
Memory *pMemory)
|
||||
{
|
||||
if ((pResourceRef->externalClassId == NV01_MEMORY_SYSTEM ||
|
||||
pResourceRef->externalClassId == NV01_MEMORY_LIST_SYSTEM ||
|
||||
pResourceRef->externalClassId == NV01_MEMORY_LIST_OBJECT) &&
|
||||
(pMemory->categoryClassId == NV01_MEMORY_SYSTEM))
|
||||
{
|
||||
return NV_TRUE;
|
||||
}
|
||||
return NV_FALSE;
|
||||
}
|
||||
|
||||
//
|
||||
// _gpuCollectMemInfo
|
||||
//
|
||||
@@ -563,8 +537,7 @@ _gpuCollectMemInfo
|
||||
Heap *pTargetedHeap,
|
||||
NV2080_CTRL_GPU_PID_INFO_VIDEO_MEMORY_USAGE_DATA *pData,
|
||||
NvBool bIsGuestProcess,
|
||||
NvBool bGlobalInfo,
|
||||
NvBool isZeroFb
|
||||
NvBool bGlobalInfo
|
||||
)
|
||||
{
|
||||
RS_ITERATOR iter;
|
||||
@@ -595,7 +568,10 @@ _gpuCollectMemInfo
|
||||
// type NVOS32_TYPE_UNUSED. So while calculating the per process FB
|
||||
// usage, only consider the allocation if memory type is not
|
||||
// NVOS32_TYPE_UNUSED.
|
||||
if (((isZeroFb && _checkSysMemClassValidity(pResourceRef, pMemory)) || _checkVidmemClassValidity(pResourceRef, pMemory)) &&
|
||||
if ((pResourceRef->externalClassId == NV01_MEMORY_LOCAL_USER ||
|
||||
pResourceRef->externalClassId == NV01_MEMORY_LIST_FBMEM ||
|
||||
pResourceRef->externalClassId == NV01_MEMORY_LIST_OBJECT ) &&
|
||||
(pMemory->categoryClassId == NV01_MEMORY_LOCAL_USER) &&
|
||||
(bGlobalInfo || (pMemory->pHeap == pTargetedHeap)) &&
|
||||
(RES_GET_HANDLE(pMemory->pDevice) == hDevice) &&
|
||||
(pMemory->pMemDesc != NULL) &&
|
||||
@@ -707,7 +683,7 @@ gpuFindClientInfoWithPidIterator_IMPL
|
||||
// clients, RM needs to provide the unique list being used by the client
|
||||
_gpuCollectMemInfo(hClient, hDevice, pHeap,
|
||||
&pData->vidMemUsage, ((subPid != 0) ? NV_TRUE : NV_FALSE),
|
||||
bGlobalInfo, pGpu->getProperty(pGpu, PDB_PROP_GPU_ZERO_FB));
|
||||
bGlobalInfo);
|
||||
break;
|
||||
}
|
||||
default:
|
||||
|
||||
@@ -182,16 +182,10 @@ memdescCreate
|
||||
NvU32 gpuCacheAttrib = NV_MEMORY_UNCACHED;
|
||||
NV_STATUS status = NV_OK;
|
||||
NvU64 pageArraySize;
|
||||
MemoryManager *pMemoryManager = NULL;
|
||||
|
||||
|
||||
allocSize = Size;
|
||||
|
||||
if (allocSize == 0)
|
||||
{
|
||||
return NV_ERR_INVALID_ARGUMENT;
|
||||
}
|
||||
|
||||
//
|
||||
// this memdesc may have gotten forced to sysmem if no carveout,
|
||||
// but for VPR it needs to be in vidmem, so check and re-direct here,
|
||||
@@ -207,29 +201,25 @@ memdescCreate
|
||||
|
||||
if (pGpu != NULL)
|
||||
{
|
||||
pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu);
|
||||
}
|
||||
MemoryManager *pMemoryManager = GPU_GET_MEMORY_MANAGER(pGpu);
|
||||
|
||||
if (((AddressSpace == ADDR_SYSMEM) || (AddressSpace == ADDR_UNKNOWN)) &&
|
||||
!(Flags & MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL))
|
||||
{
|
||||
NvU64 pageSize = osGetPageSize();
|
||||
|
||||
if (pMemoryManager && pMemoryManager->sysmemPageSize)
|
||||
if (((AddressSpace == ADDR_SYSMEM) || (AddressSpace == ADDR_UNKNOWN)) &&
|
||||
!(Flags & MEMDESC_FLAGS_OWNED_BY_CTX_BUF_POOL))
|
||||
{
|
||||
pageSize = pMemoryManager->sysmemPageSize;
|
||||
NvU64 pageSize = osGetPageSize();
|
||||
|
||||
if (pMemoryManager && pMemoryManager->sysmemPageSize)
|
||||
{
|
||||
pageSize = pMemoryManager->sysmemPageSize;
|
||||
}
|
||||
|
||||
allocSize = RM_ALIGN_UP(allocSize, pageSize);
|
||||
if (allocSize < Size)
|
||||
{
|
||||
return NV_ERR_INVALID_ARGUMENT;
|
||||
}
|
||||
}
|
||||
|
||||
allocSize = RM_ALIGN_UP(allocSize, pageSize);
|
||||
if (allocSize < Size)
|
||||
{
|
||||
return NV_ERR_INVALID_ARGUMENT;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
if (pGpu != NULL)
|
||||
{
|
||||
if (RMCFG_FEATURE_PLATFORM_MODS || IsT194(pGpu) || IsT234(pGpu))
|
||||
{
|
||||
if ( (AddressSpace == ADDR_FBMEM) &&
|
||||
@@ -270,7 +260,16 @@ memdescCreate
|
||||
// (4k >> 12 = 1). This modification helps us to avoid overflow of variable
|
||||
// allocSize, in case caller of this function passes highest value of NvU64.
|
||||
//
|
||||
PageCount = ((allocSize - 1) >> RM_PAGE_SHIFT) + 1;
|
||||
// If allocSize is passed as 0, PageCount should be returned as 0.
|
||||
//
|
||||
if (allocSize == 0)
|
||||
{
|
||||
PageCount = 0;
|
||||
}
|
||||
else
|
||||
{
|
||||
PageCount = ((allocSize - 1) >> RM_PAGE_SHIFT) + 1;
|
||||
}
|
||||
|
||||
if (PhysicallyContiguous)
|
||||
{
|
||||
@@ -1051,17 +1050,10 @@ memdescAlloc
|
||||
}
|
||||
|
||||
// Actually allocate the memory
|
||||
status = _memdescAllocInternal(pMemDesc);
|
||||
NV_CHECK_OK(status, LEVEL_ERROR, _memdescAllocInternal(pMemDesc));
|
||||
|
||||
if (status != NV_OK)
|
||||
{
|
||||
if (status == NV_ERR_NO_MEMORY && pGpu->bAPageSizeAllocRetryEnabled && pMemDesc->_pageSize != RM_PAGE_SIZE)
|
||||
{
|
||||
NV_PRINTF(LEVEL_INFO, "Failed to allocate memory due to insufficient memory with page size 0x%llx, retrying with page size 0x%x\n", pMemDesc->_pageSize, RM_PAGE_SIZE);
|
||||
}
|
||||
else
|
||||
{
|
||||
NV_PRINTF(LEVEL_ERROR, "Failed to allocate memory with page size 0x%llx\n status: %x", pMemDesc->_pageSize, status);
|
||||
}
|
||||
pMemDesc->pHeap = NULL;
|
||||
}
|
||||
|
||||
|
||||
@@ -55,12 +55,7 @@ NV_STATUS stdmemValidateParams
|
||||
return NV_ERR_INVALID_ARGUMENT;
|
||||
}
|
||||
|
||||
if (pAllocData->size == 0)
|
||||
{
|
||||
return NV_ERR_INVALID_ARGUMENT;
|
||||
}
|
||||
|
||||
//
|
||||
//
|
||||
// These flags don't do anything in this path. No mapping on alloc and
|
||||
// kernel map is controlled by TYPE
|
||||
//
|
||||
|
||||
@@ -154,9 +154,7 @@ sysmemConstruct_IMPL
|
||||
MEMORY_DESCRIPTOR *pMemDesc;
|
||||
NvU32 flags;
|
||||
RM_ATTR_PAGE_SIZE pageSizeAttr;
|
||||
NvBool bLastAttempt = NV_TRUE;
|
||||
|
||||
pGpu->bAPageSizeAllocRetryEnabled = NV_FALSE;
|
||||
NvBool bRetry = NV_FALSE;
|
||||
|
||||
NV_ASSERT_OR_RETURN(pRmClient != NULL, NV_ERR_INVALID_CLIENT);
|
||||
|
||||
@@ -205,8 +203,7 @@ sysmemConstruct_IMPL
|
||||
if (FLD_TEST_DRF(OS32, _ATTR, _PAGE_SIZE, _DEFAULT, pAllocData->attr) &&
|
||||
(GPU_GET_MEMORY_MANAGER(pGpu)->bSysmemPageSizeDefaultAllowLargePages))
|
||||
{
|
||||
pGpu->bAPageSizeAllocRetryEnabled = NV_TRUE;
|
||||
bLastAttempt = NV_FALSE;
|
||||
bRetry = NV_TRUE;
|
||||
}
|
||||
|
||||
do
|
||||
@@ -250,8 +247,6 @@ sysmemConstruct_IMPL
|
||||
if (FLD_TEST_DRF(OS32, _ATTR2, _NISO_DISPLAY, _YES, pAllocData->attr2))
|
||||
memdescSetFlag(pMemDesc, MEMDESC_FLAGS_MEMORY_TYPE_DISPLAY_NISO, NV_TRUE);
|
||||
|
||||
memdescSetFlag(pMemDesc, MEMDESC_FLAGS_ALLOC_NO_RECLAIM, !bLastAttempt);
|
||||
|
||||
memdescSetFlag(pMemDesc, MEMDESC_FLAGS_SYSMEM_OWNED_BY_CLIENT, NV_TRUE);
|
||||
|
||||
if (FLD_TEST_DRF(OS32, _ATTR2, _FIXED_NUMA_NODE_ID, _YES, pAllocData->attr2))
|
||||
@@ -278,21 +273,13 @@ sysmemConstruct_IMPL
|
||||
memdescTagAlloc(rmStatus, NV_FB_ALLOC_RM_INTERNAL_OWNER_UNNAMED_TAG_132, pMemDesc);
|
||||
if (rmStatus != NV_OK)
|
||||
{
|
||||
if (pGpu->bAPageSizeAllocRetryEnabled)
|
||||
if (bRetry)
|
||||
{
|
||||
NvU64 pageSize;
|
||||
pageSize = _sysmemGetNextSmallerPageSize(pGpu, &pAllocData->attr, &pAllocData->attr2);
|
||||
if (pageSize == 0)
|
||||
{
|
||||
NV_CHECK_OR_GOTO(LEVEL_ERROR, !bLastAttempt, failed_destroy_memdesc);
|
||||
bLastAttempt = NV_TRUE;
|
||||
NV_PRINTF(LEVEL_INFO,
|
||||
"Sysmem alloc failed at 4K page size, retrying with reclamation enabled.\n");
|
||||
}
|
||||
else
|
||||
{
|
||||
NV_PRINTF(LEVEL_INFO,
|
||||
"Sysmem alloc failed, retrying with page size 0x%llx.\n", pageSize);
|
||||
NV_CHECK_OK_OR_GOTO(rmStatus, LEVEL_ERROR, rmStatus, failed_destroy_memdesc);
|
||||
}
|
||||
NV_PRINTF(LEVEL_INFO, "Sysmem alloc failed, retrying with page size 0x%llx.\n", pageSize);
|
||||
|
||||
@@ -310,10 +297,9 @@ sysmemConstruct_IMPL
|
||||
else
|
||||
{
|
||||
// Got a valid allocation, set retry to false.
|
||||
pGpu->bAPageSizeAllocRetryEnabled = NV_FALSE;
|
||||
bRetry = NV_FALSE;
|
||||
}
|
||||
} while (pGpu->bAPageSizeAllocRetryEnabled);
|
||||
pGpu->bAPageSizeAllocRetryEnabled = NV_FALSE;
|
||||
} while (bRetry);
|
||||
|
||||
// ClientDB can set the pagesize for memdesc.
|
||||
// With GPU SMMU mapping, this needs to be set on the SMMU memdesc.
|
||||
|
||||
@@ -411,21 +411,6 @@ osTegraSocPowerManagement
|
||||
return NV_OK;
|
||||
}
|
||||
|
||||
#if !(RMCFG_FEATURE_PLATFORM_UNIX || RMCFG_FEATURE_PLATFORM_DCE) || \
|
||||
(RMCFG_FEATURE_PLATFORM_UNIX && !RMCFG_FEATURE_TEGRA_SOC_NVDISPLAY)
|
||||
NV_STATUS
|
||||
osTegraSocGetDispClockRates
|
||||
(
|
||||
OS_GPU_INFO *pOsGpuInfo,
|
||||
NvU32 *pMaxDispClkRateDisppll,
|
||||
NvU32 *pMaxDispClkRateSppllClkouta,
|
||||
NvU32 *pMaxHubClkRateSppllClkoutb
|
||||
)
|
||||
{
|
||||
return NV_ERR_NOT_SUPPORTED;
|
||||
}
|
||||
#endif
|
||||
|
||||
NV_STATUS osLockPageableDataSection(RM_PAGEABLE_SECTION *pSection)
|
||||
{
|
||||
return NV_OK;
|
||||
|
||||
Reference in New Issue
Block a user