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osi: core: Update eqos pad calibration

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Updated eqos pad calibration for qnx

Bug 2831220
Bug 3500401

Change-Id: I2301e66ae8bc905b8a61deb37694b0875a20173d
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2846450
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahesh Patil
2023-01-19 19:32:11 +00:00
committed by mobile promotions
parent 43efa1f979
commit 047a42bef8
3 changed files with 17 additions and 115 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/osi_common.h
View File

@@ -176,11 +176,9 @@
/* Default maximum Giant Packet Size Limit is 16K */
#define OSI_MAX_MTU_SIZE 16383U
#ifdef UPDATED_PAD_CAL
/* MAC Tx/Rx Idle retry and delay count */
#define OSI_TXRX_IDLE_RETRY 5000U
#define OSI_DELAY_COUNT 10U
#endif
#define EQOS_DMA_CHX_STATUS(x) ((0x0080U * (x)) + 0x1160U)
#define MGBE_DMA_CHX_STATUS(x) ((0x0080U * (x)) + 0x3160U)

126
osi/core/eqos_core.c
View File

@@ -29,7 +29,6 @@
#include "core_common.h"
#include "macsec.h"
#ifdef UPDATED_PAD_CAL
/*
* Forward declarations of local functions.
*/
@@ -37,7 +36,6 @@ static nve32_t eqos_post_pad_calibrate(
struct osi_core_priv_data *const osi_core);
static nve32_t eqos_pre_pad_calibrate(
struct osi_core_priv_data *const osi_core);
#endif /* UPDATED_PAD_CAL */
#ifndef OSI_STRIPPED_LIB
/**
@@ -124,7 +122,6 @@ static nve32_t eqos_config_flow_control(
}
#endif /* !OSI_STRIPPED_LIB */
#ifdef UPDATED_PAD_CAL
/**
* @brief eqos_pad_calibrate - performs PAD calibration
*
@@ -166,7 +163,7 @@ static nve32_t eqos_pad_calibrate(struct osi_core_priv_data *const osi_core)
nve32_t cond = COND_NOT_MET, ret = 0;
nveu32_t value;
__sync_val_compare_and_swap(&osi_core->padctrl.is_pad_cal_in_progress,
(void)__sync_val_compare_and_swap(&osi_core->padctrl.is_pad_cal_in_progress,
OSI_DISABLE, OSI_ENABLE);
ret = eqos_pre_pad_calibrate(osi_core);
if (ret < 0) {
@@ -224,105 +221,14 @@ calibration_failed:
value = osi_readla(osi_core, (nveu8_t *)ioaddr + EQOS_PAD_CRTL);
value &= ~EQOS_PAD_CRTL_E_INPUT_OR_E_PWRD;
osi_writela(osi_core, value, (nveu8_t *)ioaddr + EQOS_PAD_CRTL);
ret = eqos_post_pad_calibrate(osi_core) < 0 ? -1 : ret;
ret = (eqos_post_pad_calibrate(osi_core) < 0) ? -1 : ret;
error:
__sync_val_compare_and_swap(&osi_core->padctrl.is_pad_cal_in_progress,
(void)__sync_val_compare_and_swap(&osi_core->padctrl.is_pad_cal_in_progress,
OSI_ENABLE, OSI_DISABLE);
return ret;
}
#else
/**
* @brief eqos_pad_calibrate - PAD calibration
*
* @note
* Algorithm:
* - Set field PAD_E_INPUT_OR_E_PWRD in reg ETHER_QOS_SDMEMCOMPPADCTRL_0
* - Delay for 1 usec.
* - Set AUTO_CAL_ENABLE and AUTO_CAL_START in reg
* ETHER_QOS_AUTO_CAL_CONFIG_0
* - Wait on AUTO_CAL_ACTIVE until it is 0
* - Re-program the value PAD_E_INPUT_OR_E_PWRD in
* ETHER_QOS_SDMEMCOMPPADCTRL_0 to save power
*
* @param[in] osi_core: OSI core private data structure.
*
* @note
* - MAC should out of reset and clocks enabled.
* - RGMII and MDIO interface needs to be IDLE before performing PAD
* calibration.
*
* @note
* API Group:
* - Initialization: Yes
* - Run time: Yes
* - De-initialization: No
*
* @retval 0 on success
* @retval -1 on failure.
*/
static nve32_t eqos_pad_calibrate(struct osi_core_priv_data *const osi_core)
{
void *ioaddr = osi_core->base;
nveu32_t retry = RETRY_COUNT;
nveu32_t count;
nve32_t cond = COND_NOT_MET, ret = 0;
nveu32_t value;
/* 1. Set field PAD_E_INPUT_OR_E_PWRD in
* reg ETHER_QOS_SDMEMCOMPPADCTRL_0
*/
value = osi_readla(osi_core, (nveu8_t *)ioaddr + EQOS_PAD_CRTL);
value |= EQOS_PAD_CRTL_E_INPUT_OR_E_PWRD;
osi_writela(osi_core, value, (nveu8_t *)ioaddr + EQOS_PAD_CRTL);
/* 2. delay for 1 usec */
osi_core->osd_ops.usleep_range(1, 3);
/* 3. Set AUTO_CAL_ENABLE and AUTO_CAL_START in
* reg ETHER_QOS_AUTO_CAL_CONFIG_0.
* Set pad_auto_cal pd/pu offset values
*/
value = osi_readla(osi_core,
(nveu8_t *)ioaddr + EQOS_PAD_AUTO_CAL_CFG);
value &= ~EQOS_PAD_CRTL_PU_OFFSET_MASK;
value &= ~EQOS_PAD_CRTL_PD_OFFSET_MASK;
value |= osi_core->padctrl.pad_auto_cal_pu_offset;
value |= (osi_core->padctrl.pad_auto_cal_pd_offset << 8U);
value |= EQOS_PAD_AUTO_CAL_CFG_START |
EQOS_PAD_AUTO_CAL_CFG_ENABLE;
osi_writela(osi_core, value, (nveu8_t *)ioaddr + EQOS_PAD_AUTO_CAL_CFG);
/* 4. Wait on 1 to 3 us before start checking for calibration done.
* This delay is consumed in delay inside while loop.
*/
/* 5. Wait on AUTO_CAL_ACTIVE until it is 0. 10ms is the timeout */
count = 0;
while (cond == COND_NOT_MET) {
if (count > retry) {
ret = -1;
goto calibration_failed;
}
count++;
osi_core->osd_ops.usleep_range(10, 12);
value = osi_readla(osi_core, (nveu8_t *)ioaddr +
EQOS_PAD_AUTO_CAL_STAT);
/* calibration done when CAL_STAT_ACTIVE is zero */
if ((value & EQOS_PAD_AUTO_CAL_STAT_ACTIVE) == 0U) {
cond = COND_MET;
}
}
calibration_failed:
/* 6. Re-program the value PAD_E_INPUT_OR_E_PWRD in
* ETHER_QOS_SDMEMCOMPPADCTRL_0 to save power
*/
value = osi_readla(osi_core, (nveu8_t *)ioaddr + EQOS_PAD_CRTL);
value &= ~EQOS_PAD_CRTL_E_INPUT_OR_E_PWRD;
osi_writela(osi_core, value, (nveu8_t *)ioaddr + EQOS_PAD_CRTL);
return ret;
}
#endif /* UPDATED_PAD_CAL */
/** \cond DO_NOT_DOCUMENT */
/**
* @brief eqos_configure_mtl_queue - Configure MTL Queue
@@ -1266,7 +1172,6 @@ static nve32_t eqos_core_init(struct osi_core_priv_data *const osi_core)
nveu32_t value = 0;
nveu32_t value1 = 0;
#ifndef UPDATED_PAD_CAL
/* PAD calibration */
ret = eqos_pad_calibrate(osi_core);
if (ret < 0) {
@@ -1274,7 +1179,6 @@ static nve32_t eqos_core_init(struct osi_core_priv_data *const osi_core)
"eqos pad calibration failed\n", 0ULL);
goto fail;
}
#endif /* !UPDATED_PAD_CAL */
/* reset mmc counters */
osi_writela(osi_core, EQOS_MMC_CNTRL_CNTRST,
@@ -3849,7 +3753,6 @@ static nve32_t eqos_get_hw_features(struct osi_core_priv_data *const osi_core,
return 0;
}
#ifdef UPDATED_PAD_CAL
/**
* @brief eqos_padctl_rx_pins Enable/Disable RGMII Rx pins
*
@@ -3865,11 +3768,13 @@ static nve32_t eqos_get_hw_features(struct osi_core_priv_data *const osi_core,
static nve32_t eqos_padctl_rx_pins(struct osi_core_priv_data *const osi_core,
nveu32_t enable)
{
nve32_t ret = 0;
nveu32_t value;
void *pad_addr = osi_core->padctrl.padctrl_base;
if (pad_addr == OSI_NULL) {
return -1;
ret = -1;
goto error;
}
if (enable == OSI_ENABLE) {
value = osi_readla(osi_core, (nveu8_t *)pad_addr +
@@ -3924,7 +3829,9 @@ static nve32_t eqos_padctl_rx_pins(struct osi_core_priv_data *const osi_core,
osi_writela(osi_core, value, (nveu8_t *)pad_addr +
osi_core->padctrl.offset_rd3);
}
return 0;
error:
return ret;
}
/**
@@ -3942,6 +3849,7 @@ static nve32_t eqos_padctl_rx_pins(struct osi_core_priv_data *const osi_core,
*/
static inline nve32_t poll_for_mac_tx_rx_idle(struct osi_core_priv_data *osi_core)
{
nve32_t ret = 0;
nveu32_t retry = 0;
nveu32_t mac_debug;
@@ -3962,10 +3870,10 @@ static inline nve32_t poll_for_mac_tx_rx_idle(struct osi_core_priv_data *osi_cor
OSI_CORE_ERR(osi_core->osd,
OSI_LOG_ARG_HW_FAIL, "RGMII idle timed out\n",
mac_debug);
return -1;
ret = -1;
}
return 0;
return ret;
}
/**
@@ -4017,8 +3925,8 @@ static nve32_t eqos_pre_pad_calibrate(struct osi_core_priv_data *const osi_core)
if (ret < 0) {
goto error;
}
goto done;
return ret;
error:
/* roll back on fail */
hw_start_mac(osi_core);
@@ -4035,6 +3943,7 @@ error:
value |= EQOS_IMR_RGSMIIIE;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base + EQOS_MAC_IMR);
done:
return ret;
}
@@ -4076,12 +3985,12 @@ static nve32_t eqos_post_pad_calibrate(
mac_isr = osi_readla(osi_core, (nveu8_t *)osi_core->base +
EQOS_MAC_ISR);
/* RGMII/SMII interrupt disabled in eqos_pre_pad_calibrate */
if ((mac_isr & EQOS_MAC_ISR_RGSMIIS) == EQOS_MAC_ISR_RGSMIIS &&
(mac_imr & EQOS_MAC_ISR_RGSMIIS) == OSI_DISABLE) {
if (((mac_isr & EQOS_MAC_ISR_RGSMIIS) == EQOS_MAC_ISR_RGSMIIS) &&
((mac_imr & EQOS_MAC_ISR_RGSMIIS) == OSI_DISABLE)) {
/* clear RGSMIIIE pending interrupt status due to pad enable */
mac_pcs = osi_readla(osi_core, (nveu8_t *)osi_core->base +
EQOS_MAC_PCS);
if (mac_pcs) {
if (mac_pcs != 0U) {
/* do nothing */
}
}
@@ -4091,7 +4000,6 @@ static nve32_t eqos_post_pad_calibrate(
osi_writela(osi_core, mac_imr, (nveu8_t *)osi_core->base + EQOS_MAC_IMR);
return ret;
}
#endif /* UPDATED_PAD_CAL */
#ifndef OSI_STRIPPED_LIB
/**

4
osi/core/eqos_core.h
View File

@@ -260,11 +260,9 @@
#endif /* !OSI_STRIPPED_LIB */
#define EQOS_MAC_PCS 0x00F8
#ifdef UPDATED_PAD_CAL
#define EQOS_MAC_DEBUG 0x0114
#define EQOS_MAC_DEBUG_RPESTS OSI_BIT(0)
#define EQOS_MAC_DEBUG_TPESTS OSI_BIT(16)
#endif
#define EQOS_MAC_MDIO_ADDRESS 0x0200
#define EQOS_MAC_MDIO_DATA 0x0204
@@ -568,10 +566,8 @@
/* MACSEC Recommended value*/
#define EQOS_MTL_EST_CTOV_MACSEC_RECOMMEND 758U
#endif /* MACSEC_SUPPORT */
#ifdef UPDATED_PAD_CAL
/* EQOS RGMII Rx padctrl registers E_INPUT bit */
#define EQOS_PADCTL_EQOS_E_INPUT OSI_BIT(6)
#endif
/** @} */
void update_ehfc_rfa_rfd(nveu32_t rx_fifo, nveu32_t *value);