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osi: core: combine config_mac_pkt_filter_reg

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Bug 3701869

Change-Id: I603bd57511f115fb5af42dca2a5804cf4926ebbb
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2740658
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Narayan Reddy
2022-07-06 14:04:42 +00:00
committed by Bhadram Varka
parent d3b56f5eee
commit 09d4489e78
8 changed files with 90 additions and 251 deletions
Download Patch File Download Diff File Expand all files Collapse all files

72
osi/core/core_common.c
View File

@@ -486,6 +486,78 @@ exit:
return ret;
}
static inline void config_l2_da_perfect_inverse_match(
struct osi_core_priv_data *osi_core,
nveu32_t perfect_inverse_match)
{
nveu32_t value = 0U;
value = osi_readla(osi_core, ((nveu8_t *)osi_core->base + MAC_PKT_FILTER_REG));
value &= ~MAC_PFR_DAIF;
if (perfect_inverse_match == OSI_INV_MATCH) {
/* Set DA Inverse Filtering */
value |= MAC_PFR_DAIF;
}
osi_writela(osi_core, value, ((nveu8_t *)osi_core->base + MAC_PKT_FILTER_REG));
}
nve32_t hw_config_mac_pkt_filter_reg(struct osi_core_priv_data *const osi_core,
const struct osi_filter *filter)
{
nveu32_t value = 0U;
nve32_t ret = 0;
value = osi_readla(osi_core, ((nveu8_t *)osi_core->base + MAC_PKT_FILTER_REG));
/*Retain all other values */
value &= (MAC_PFR_DAIF | MAC_PFR_DBF | MAC_PFR_SAIF |
MAC_PFR_SAF | MAC_PFR_PCF | MAC_PFR_VTFE |
MAC_PFR_IPFE | MAC_PFR_DNTU | MAC_PFR_RA);
if ((filter->oper_mode & OSI_OPER_EN_PERFECT) != OSI_DISABLE) {
value |= MAC_PFR_HPF;
}
#ifndef OSI_STRIPPED_LIB
if ((filter->oper_mode & OSI_OPER_DIS_PERFECT) != OSI_DISABLE) {
value &= ~MAC_PFR_HPF;
}
if ((filter->oper_mode & OSI_OPER_EN_PROMISC) != OSI_DISABLE) {
value |= MAC_PFR_PR;
}
if ((filter->oper_mode & OSI_OPER_DIS_PROMISC) != OSI_DISABLE) {
value &= ~MAC_PFR_PR;
}
if ((filter->oper_mode & OSI_OPER_EN_ALLMULTI) != OSI_DISABLE) {
value |= MAC_PFR_PM;
}
if ((filter->oper_mode & OSI_OPER_DIS_ALLMULTI) != OSI_DISABLE) {
value &= ~MAC_PFR_PM;
}
#endif /* !OSI_STRIPPED_LIB */
osi_writela(osi_core, value,
((nveu8_t *)osi_core->base + MAC_PKT_FILTER_REG));
#ifndef OSI_STRIPPED_LIB
if ((filter->oper_mode & OSI_OPER_EN_L2_DA_INV) != OSI_DISABLE) {
config_l2_da_perfect_inverse_match(osi_core, OSI_INV_MATCH);
}
if ((filter->oper_mode & OSI_OPER_DIS_L2_DA_INV) != OSI_DISABLE) {
#endif /* !OSI_STRIPPED_LIB */
config_l2_da_perfect_inverse_match(osi_core, OSI_PFT_MATCH);
#ifndef OSI_STRIPPED_LIB
}
#endif /* !OSI_STRIPPED_LIB */
return ret;
}
#ifndef OSI_STRIPPED_LIB
/**
* @brief hw_est_read - indirect read the GCL to Software own list

18
osi/core/core_common.h
View File

@@ -52,13 +52,27 @@
#define MAC_PPS_CTL_PPSCTRL0 (OSI_BIT(3) | OSI_BIT(2) |\
OSI_BIT(1) | OSI_BIT(0))
#define MAC_SSIR_SSINC_SHIFT 16U
#define MAC_PFR_PR OSI_BIT(0)
#define MAC_PFR_DAIF OSI_BIT(3)
#define MAC_PFR_PM OSI_BIT(4)
#define MAC_PFR_DBF OSI_BIT(5)
#define MAC_PFR_PCF (OSI_BIT(6) | OSI_BIT(7))
#define MAC_PFR_SAIF OSI_BIT(8)
#define MAC_PFR_SAF OSI_BIT(9)
#define MAC_PFR_HPF OSI_BIT(10)
#define MAC_PFR_VTFE OSI_BIT(16)
#define MAC_PFR_IPFE OSI_BIT(20)
#define MAC_PFR_IPFE_SHIFT 20U
#define MAC_PFR_DNTU OSI_BIT(21)
#define MAC_PFR_RA OSI_BIT(31)
#define WRAP_SYNC_TSC_PTP_CAPTURE 0x800CU
#define WRAP_TSC_CAPTURE_LOW 0x8010U
#define WRAP_TSC_CAPTURE_HIGH 0x8014U
#define WRAP_PTP_CAPTURE_LOW 0x8018U
#define WRAP_PTP_CAPTURE_HIGH 0x801CU
#define MAC_PKT_FILTER_REG 0x0008
#ifndef OSI_STRIPPED_LIB
/**
@@ -100,4 +114,6 @@ void hw_config_tscr(struct osi_core_priv_data *const osi_core, const nveu32_t pt
void hw_config_ssir(struct osi_core_priv_data *const osi_core);
nve32_t hw_ptp_tsc_capture(struct osi_core_priv_data *const osi_core,
struct osi_core_ptp_tsc_data *data);
nve32_t hw_config_mac_pkt_filter_reg(struct osi_core_priv_data *const osi_core,
const struct osi_filter *filter);
#endif /* INCLUDED_CORE_COMMON_H */

4
osi/core/core_local.h
View File

@@ -111,10 +111,6 @@ struct core_ops {
void (*handle_common_intr)(struct osi_core_priv_data *const osi_core);
/** Called to do pad caliberation */
nve32_t (*pad_calibrate)(struct osi_core_priv_data *const osi_core);
/** Called to config mac packet filter */
nve32_t (*config_mac_pkt_filter_reg)(
struct osi_core_priv_data *const osi_core,
const struct osi_filter *filter);
/** Called to update MAC address 1-127 */
nve32_t (*update_mac_addr_low_high_reg)(
struct osi_core_priv_data *const osi_core,

121
osi/core/eqos_core.c
View File

@@ -2614,126 +2614,6 @@ static void eqos_config_mac_tx(struct osi_core_priv_data *const osi_core,
}
#endif /* MACSEC_SUPPORT */
/**
* @brief eqos_config_l2_da_perfect_inverse_match - configure register for
* inverse or perfect match.
*
* @note
* Algorithm:
* - use perfect_inverse_match filed to set perfect/inverse matching for L2 DA.
* - Refer to EQOS column of <<RM_18, (sequence diagram)>> for API details.
* - TraceID:ETHERNET_NVETHERNETRM_018
*
* @param[in] base: Base address from OSI core private data structure.
* @param[in] perfect_inverse_match: OSI_INV_MATCH - inverse mode else - perfect mode
*
* @pre MAC should be initialized and started. see osi_start_mac()
*
* @note
* API Group:
* - Initialization: Yes
* - Run time: Yes
* - De-initialization: No
*
* @retval 0 always
*/
static inline nve32_t eqos_config_l2_da_perfect_inverse_match(
struct osi_core_priv_data *const osi_core,
nveu32_t perfect_inverse_match)
{
nveu32_t value = 0U;
value = osi_readla(osi_core,
(nveu8_t *)osi_core->base + EQOS_MAC_PFR);
value &= ~EQOS_MAC_PFR_DAIF;
if (perfect_inverse_match == OSI_INV_MATCH) {
value |= EQOS_MAC_PFR_DAIF;
}
eqos_core_safety_writel(osi_core, value,
(nveu8_t *)osi_core->base + EQOS_MAC_PFR,
EQOS_MAC_PFR_IDX);
return 0;
}
/**
* @brief eqos_config_mac_pkt_filter_reg - configure mac filter register.
*
* @note
* - This sequence is used to configure MAC in different pkt
* processing modes like promiscuous, multicast, unicast,
* hash unicast/multicast based on input filter arguments.
* - Refer to EQOS column of <<RM_18, (sequence diagram)>> for API details.
* - TraceID:ETHERNET_NVETHERNETRM_018
*
* @param[in] osi_core: OSI core private data structure. Used param base.
* @param[in] filter: OSI filter structure. used param oper_mode.
*
* @pre MAC should be initialized and started. see osi_start_mac()
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*
* @retval 0 always
*/
static nve32_t eqos_config_mac_pkt_filter_reg(
struct osi_core_priv_data *const osi_core,
const struct osi_filter *filter)
{
nveu32_t value = 0U;
nve32_t ret = 0;
value = osi_readla(osi_core, (nveu8_t *)osi_core->base + EQOS_MAC_PFR);
/*Retain all other values */
value &= (EQOS_MAC_PFR_DAIF | EQOS_MAC_PFR_DBF | EQOS_MAC_PFR_SAIF |
EQOS_MAC_PFR_SAF | EQOS_MAC_PFR_PCF | EQOS_MAC_PFR_VTFE |
EQOS_MAC_PFR_IPFE | EQOS_MAC_PFR_DNTU | EQOS_MAC_PFR_RA);
if ((filter->oper_mode & OSI_OPER_EN_PROMISC) != OSI_DISABLE) {
value |= EQOS_MAC_PFR_PR;
}
if ((filter->oper_mode & OSI_OPER_DIS_PROMISC) != OSI_DISABLE) {
value &= ~EQOS_MAC_PFR_PR;
}
if ((filter->oper_mode & OSI_OPER_EN_ALLMULTI) != OSI_DISABLE) {
value |= EQOS_MAC_PFR_PM;
}
if ((filter->oper_mode & OSI_OPER_DIS_ALLMULTI) != OSI_DISABLE) {
value &= ~EQOS_MAC_PFR_PM;
}
if ((filter->oper_mode & OSI_OPER_EN_PERFECT) != OSI_DISABLE) {
value |= EQOS_MAC_PFR_HPF;
}
if ((filter->oper_mode & OSI_OPER_DIS_PERFECT) != OSI_DISABLE) {
value &= ~EQOS_MAC_PFR_HPF;
}
eqos_core_safety_writel(osi_core, value, (nveu8_t *)osi_core->base +
EQOS_MAC_PFR, EQOS_MAC_PFR_IDX);
if ((filter->oper_mode & OSI_OPER_EN_L2_DA_INV) != OSI_DISABLE) {
ret = eqos_config_l2_da_perfect_inverse_match(osi_core,
OSI_INV_MATCH);
}
if ((filter->oper_mode & OSI_OPER_DIS_L2_DA_INV) != OSI_DISABLE) {
ret = eqos_config_l2_da_perfect_inverse_match(osi_core,
OSI_PFT_MATCH);
}
return ret;
}
/**
* @brief eqos_update_mac_addr_helper - Function to update DCS and MBC; helper function for
* eqos_update_mac_addr_low_high_reg()
@@ -5992,7 +5872,6 @@ void eqos_init_core_ops(struct core_ops *ops)
ops->core_init = eqos_core_init;
ops->handle_common_intr = eqos_handle_common_intr;
ops->pad_calibrate = eqos_pad_calibrate;
ops->config_mac_pkt_filter_reg = eqos_config_mac_pkt_filter_reg;
ops->update_mac_addr_low_high_reg = eqos_update_mac_addr_low_high_reg;
ops->config_l3_l4_filter_enable = eqos_config_l3_l4_filter_enable;
ops->config_l3_filters = eqos_config_l3_filters;

10
osi/core/eqos_core.h
View File

@@ -460,19 +460,9 @@
#define EQOS_MTL_RXQ_OP_MODE_RFA_MASK 0x00003F00U
#define EQOS_MTL_RXQ_OP_MODE_RFD_SHIFT 14U
#define EQOS_MTL_RXQ_OP_MODE_RFD_MASK 0x000FC000U
#define EQOS_MAC_PFR_PR OSI_BIT(0)
#define EQOS_MAC_PFR_DAIF OSI_BIT(3)
#define EQOS_MAC_PFR_PM OSI_BIT(4)
#define EQOS_MAC_PFR_DBF OSI_BIT(5)
#define EQOS_MAC_PFR_PCF (OSI_BIT(6) | OSI_BIT(7))
#define EQOS_MAC_PFR_SAIF OSI_BIT(8)
#define EQOS_MAC_PFR_SAF OSI_BIT(9)
#define EQOS_MAC_PFR_HPF OSI_BIT(10)
#define EQOS_MAC_PFR_VTFE OSI_BIT(16)
#define EQOS_MAC_PFR_IPFE OSI_BIT(20)
#define EQOS_MAC_PFR_IPFE_SHIFT 20U
#define EQOS_MAC_PFR_DNTU OSI_BIT(21)
#define EQOS_MAC_PFR_RA OSI_BIT(31)
#define EQOS_MAC_L3L4_CTR_L4SPM0 OSI_BIT(18)
#define EQOS_MAC_L3L4_CTR_L4SPIM0 OSI_BIT(19)
#define EQOS_MAC_L3L4_CTR_L4DPM0 OSI_BIT(20)

104
osi/core/mgbe_core.c
View File

@@ -258,109 +258,6 @@ static nve32_t mgbe_mac_indir_addr_read(struct osi_core_priv_data *osi_core,
return 0;
}
/**
* @brief mgbe_config_l2_da_perfect_inverse_match - configure register for
* inverse or perfect match.
*
* Algorithm: This sequence is used to select perfect/inverse matching
* for L2 DA
*
* @param[in] osi_core: OSI core private data structure.
* @param[in] perfect_inverse_match: 1 - inverse mode 0- perfect mode
*
* @note MAC should be init and started. see osi_start_mac()
*/
static inline void mgbe_config_l2_da_perfect_inverse_match(
struct osi_core_priv_data *osi_core,
nveu32_t perfect_inverse_match)
{
nveu32_t value = 0U;
value = osi_readla(osi_core,
(nveu8_t *)osi_core->base + MGBE_MAC_PFR);
value &= ~MGBE_MAC_PFR_DAIF;
if (perfect_inverse_match == OSI_INV_MATCH) {
/* Set DA Inverse Filtering */
value |= MGBE_MAC_PFR_DAIF;
}
osi_writela(osi_core, value,
(nveu8_t *)osi_core->base + MGBE_MAC_PFR);
}
/**
* @brief mgbe_config_mac_pkt_filter_reg - configure mac filter register.
*
* Algorithm: This sequence is used to configure MAC in differnet pkt
* processing modes like promiscuous, multicast, unicast,
* hash unicast/multicast.
*
* @param[in] osi_core: OSI core private data structure.
* @param[in] filter: OSI filter structure.
*
* @note 1) MAC should be initialized and started. see osi_start_mac()
*
* @retval 0 always
*/
static nve32_t mgbe_config_mac_pkt_filter_reg(struct osi_core_priv_data *const osi_core,
const struct osi_filter *filter)
{
nveu32_t value = 0U;
nve32_t ret = 0;
value = osi_readla(osi_core,
(nveu8_t *)osi_core->base + MGBE_MAC_PFR);
/* Retain all other values */
value &= (MGBE_MAC_PFR_DAIF | MGBE_MAC_PFR_DBF | MGBE_MAC_PFR_SAIF |
MGBE_MAC_PFR_SAF | MGBE_MAC_PFR_PCF | MGBE_MAC_PFR_VTFE |
MGBE_MAC_PFR_IPFE | MGBE_MAC_PFR_DNTU | MGBE_MAC_PFR_RA);
if ((filter->oper_mode & OSI_OPER_EN_PROMISC) != OSI_DISABLE) {
/* Set Promiscuous Mode Bit */
value |= MGBE_MAC_PFR_PR;
}
if ((filter->oper_mode & OSI_OPER_DIS_PROMISC) != OSI_DISABLE) {
/* Reset Promiscuous Mode Bit */
value &= ~MGBE_MAC_PFR_PR;
}
if ((filter->oper_mode & OSI_OPER_EN_ALLMULTI) != OSI_DISABLE) {
/* Set Pass All Multicast Bit */
value |= MGBE_MAC_PFR_PM;
}
if ((filter->oper_mode & OSI_OPER_DIS_ALLMULTI) != OSI_DISABLE) {
/* Reset Pass All Multicast Bit */
value &= ~MGBE_MAC_PFR_PM;
}
if ((filter->oper_mode & OSI_OPER_EN_PERFECT) != OSI_DISABLE) {
/* Set Hash or Perfect Filter Bit */
value |= MGBE_MAC_PFR_HPF;
}
if ((filter->oper_mode & OSI_OPER_DIS_PERFECT) != OSI_DISABLE) {
/* Reset Hash or Perfect Filter Bit */
value &= ~MGBE_MAC_PFR_HPF;
}
osi_writela(osi_core, value,
(nveu8_t *)osi_core->base + MGBE_MAC_PFR);
if ((filter->oper_mode & OSI_OPER_EN_L2_DA_INV) != OSI_DISABLE) {
mgbe_config_l2_da_perfect_inverse_match(osi_core,
OSI_INV_MATCH);
}
if ((filter->oper_mode & OSI_OPER_DIS_L2_DA_INV) != OSI_DISABLE) {
mgbe_config_l2_da_perfect_inverse_match(osi_core,
OSI_PFT_MATCH);
}
return ret;
}
/**
* @brief mgbe_filter_args_validate - Validates the filter arguments
*
@@ -5567,7 +5464,6 @@ void mgbe_init_core_ops(struct core_ops *ops)
ops->core_init = mgbe_core_init;
ops->handle_common_intr = mgbe_handle_common_intr;
ops->pad_calibrate = mgbe_pad_calibrate;
ops->config_mac_pkt_filter_reg = mgbe_config_mac_pkt_filter_reg;
ops->update_mac_addr_low_high_reg = mgbe_update_mac_addr_low_high_reg;
ops->config_l3_l4_filter_enable = mgbe_config_l3_l4_filter_enable;
ops->config_l3_filters = mgbe_config_l3_filters;

10
osi/core/mgbe_core.h
View File

@@ -598,19 +598,9 @@
#define MGBE_DMA_ISR_DCH0_DCH15_MASK 0x3FFU
#define MGBE_DMA_CHX_STATUS_TI OSI_BIT(0)
#define MGBE_DMA_CHX_STATUS_RI OSI_BIT(6)
#define MGBE_MAC_PFR_PR OSI_BIT(0)
#define MGBE_MAC_PFR_DAIF OSI_BIT(3)
#define MGBE_MAC_PFR_PM OSI_BIT(4)
#define MGBE_MAC_PFR_DBF OSI_BIT(5)
#define MGBE_MAC_PFR_PCF (OSI_BIT(6) | OSI_BIT(7))
#define MGBE_MAC_PFR_SAIF OSI_BIT(8)
#define MGBE_MAC_PFR_SAF OSI_BIT(9)
#define MGBE_MAC_PFR_HPF OSI_BIT(10)
#define MGBE_MAC_PFR_VTFE OSI_BIT(16)
#define MGBE_MAC_PFR_IPFE OSI_BIT(20)
#define MGBE_MAC_PFR_IPFE_SHIFT 20
#define MGBE_MAC_PFR_DNTU OSI_BIT(21)
#define MGBE_MAC_PFR_RA OSI_BIT(31)
#define MGBE_MAC_ADDRH_AE OSI_BIT(31)
#define MGBE_MAC_ADDRH_SA OSI_BIT(30)
#define MGBE_MAC_ADDRH_SA_SHIFT 30

2
osi/core/osi_hal.c
View File

@@ -387,7 +387,7 @@ nve32_t osi_l2_filter(struct osi_core_priv_data *const osi_core,
return -1;
}
ret = l_core->ops_p->config_mac_pkt_filter_reg(osi_core, filter);
ret = hw_config_mac_pkt_filter_reg(osi_core, filter);
if (ret < 0) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
"failed to configure MAC packet filter register\n",