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osi: core: Disable TXESIE for safety

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Issue:
Observed common intrrupt on
safety builds as TXESIE is not
served.

Fix:
Disable TXESIE intrrupt for
safety builds

Bug 3846917

Change-Id: I8f01d382eb2979439f7a82fce346c66f1133061f
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2814604
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mohan Thadikamalla
2022-11-23 14:56:32 +05:30
committed by mobile promotions
parent 2ac6b6f645
commit 20f52bb866
2 changed files with 5 additions and 2 deletions
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5
osi/core/mgbe_core.c
View File

@@ -2384,7 +2384,10 @@ static nve32_t mgbe_configure_mac(struct osi_core_priv_data *osi_core)
/* RGSMIIIM - RGMII/SMII interrupt and TSIE Enable */ /* RGSMIIIM - RGMII/SMII interrupt and TSIE Enable */
/* TXESIE - Transmit Error Status Interrupt Enable */ /* TXESIE - Transmit Error Status Interrupt Enable */
/* TODO: LPI need to be enabled during EEE implementation */ /* TODO: LPI need to be enabled during EEE implementation */
value |= (MGBE_IMR_RGSMIIIE | MGBE_IMR_TSIE | MGBE_IMR_TXESIE); #ifndef OSI_STRIPPED_LIB
value |= (MGBE_IMR_TXESIE);
#endif
value |= (MGBE_IMR_RGSMIIIE | MGBE_IMR_TSIE);
osi_writela(osi_core, value, (nveu8_t *)osi_core->base + MGBE_MAC_IER); osi_writela(osi_core, value, (nveu8_t *)osi_core->base + MGBE_MAC_IER);
/* Enable common interrupt at wrapper level */ /* Enable common interrupt at wrapper level */

2
osi/core/mgbe_core.h
View File

@@ -165,6 +165,7 @@
#define MGBE_MTL_RXP_BYPASS_CNT 2U #define MGBE_MTL_RXP_BYPASS_CNT 2U
#define MGBE_MAC_FPE_CTS_SVER OSI_BIT(1) #define MGBE_MAC_FPE_CTS_SVER OSI_BIT(1)
#define MGBE_IMR_TXESIE OSI_BIT(13)
#endif /* !OSI_STRIPPED_LIB */ #endif /* !OSI_STRIPPED_LIB */
#define MGBE_MTL_EST_CONTROL 0x1050 #define MGBE_MTL_EST_CONTROL 0x1050
@@ -556,7 +557,6 @@
#define MGBE_MAC_RQC1R_MCBCQ_SHIFT 8U #define MGBE_MAC_RQC1R_MCBCQ_SHIFT 8U
#define MGBE_IMR_RGSMIIIE OSI_BIT(0) #define MGBE_IMR_RGSMIIIE OSI_BIT(0)
#define MGBE_IMR_TSIE OSI_BIT(12) #define MGBE_IMR_TSIE OSI_BIT(12)
#define MGBE_IMR_TXESIE OSI_BIT(13)
#define MGBE_ISR_TSIS OSI_BIT(12) #define MGBE_ISR_TSIS OSI_BIT(12)
#define MGBE_DMA_ISR_MACIS OSI_BIT(17) #define MGBE_DMA_ISR_MACIS OSI_BIT(17)
#define MGBE_DMA_ISR_DCH0_DCH15_MASK 0x3FFU #define MGBE_DMA_ISR_DCH0_DCH15_MASK 0x3FFU