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core: dma: fix doxygen comment as per review comment

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Issue: Doxygen comments needs to be fixed for all
       units where pointer passed to a function
       and structure members updated through that
       pointer.
Fix:   corrected doxygen comments

Bug 200681427

Change-Id: I026ae30dc587234e8491d4764a5a3511042d3b9f
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2455185
(cherry picked from commit f09df9984ab5ff52cfaade8f994e2e63cb0256e0)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2457308
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
rakesh goyal
2020-12-04 20:17:47 +05:30
committed by Bhadram Varka
parent 77aa8112be
commit 24f9d3bb7e
8 changed files with 47 additions and 45 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
include/osi_core.h
View File

@@ -613,7 +613,7 @@ nve32_t osi_poll_for_mac_reset_complete(
* Algorithm:
* - Invokes EQOS MAC, MTL and common DMA register init code.
*
* @param[in] osi_core: OSI core private data structure.
* @param[in, out] osi_core: OSI core private data structure.
* @param[in] tx_fifo_size: OSI core private data structure.
* @param[in] rx_fifo_size: OSI core private data structure.
*
@@ -1330,7 +1330,7 @@ void *eqos_get_core_safety_config(void);
* destination Port Number for L4(TCP/UDP) layer
* filtering.
*
* @param[in] osi_core: OSI core private data structure.
* @param[in, out] osi_core: OSI core private data structure.
* @param[in] l_filter: L3L4 filter data structure.
* @param[in] type: L3 filter (ipv4(0) or ipv6(1))
* or L4 filter (tcp(0) or udp(1))
@@ -1958,7 +1958,7 @@ nve32_t osi_restore_registers(struct osi_core_priv_data *const osi_core);
* - MDC clock rate will be populated in OSI core private data
* structure based on AXI_CBB clock rate.
*
* @param[in] osi_core: OSI core private data structure.
* @param[in, out] osi_core: OSI core private data structure.
* @param[in] csr_clk_rate: CSR (AXI CBB) clock rate.
*
* @note OSD layer needs get the AXI CBB clock rate with OSD clock API

22
include/osi_dma.h
View File

@@ -871,7 +871,7 @@ nveu32_t osi_get_refill_rx_desc_cnt(struct osi_rx_ring *rx_ring);
* - Initialize a Rx DMA descriptor.
*
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in] rx_ring: HW ring corresponding to Rx DMA channel.
* @param[in, out] rx_ring: HW ring corresponding to Rx DMA channel.
* @param[in] chan: Rx DMA channel number
*
* @pre
@@ -905,7 +905,7 @@ nve32_t osi_rx_dma_desc_init(struct osi_dma_priv_data *osi_dma,
/**
* @brief Updates rx buffer length.
*
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in, out] osi_dma: OSI DMA private data structure.
*
* @pre
* - MAC needs to be out of reset and proper clocks need to be configured.
@@ -943,7 +943,7 @@ nve32_t osi_set_rx_buf_len(struct osi_dma_priv_data *osi_dma);
* set OWN bit, Tx ring length and set starting address of Tx DMA channel
* Tx ring base address in Tx DMA registers.
*
* @param[in] osi_dma: OSI DMA private data.
* @param[in, out] osi_dma: OSI DMA private data.
* @param[in] chan: DMA Tx channel number.
*
* @pre
@@ -993,7 +993,7 @@ void osi_hw_transmit(struct osi_dma_priv_data *osi_dma, nveu32_t chan);
* - Invokes OSD layer to release DMA address and Tx buffer which are
* updated as part of transmit routine.
*
* @param[in] osi_dma: OSI dma private data structure.
* @param[in, out] osi_dma: OSI dma private data structure.
* @param[in] chan: Channel number on which Tx complete need to be done.
* @param[in] budget: Threshold for reading the packets at a time.
*
@@ -1039,10 +1039,10 @@ nve32_t osi_process_tx_completions(struct osi_dma_priv_data *osi_dma,
* - Re-allocate the receive buffers, populate Rx descriptor and
* handover to DMA.
*
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in, out] osi_dma: OSI DMA private data structure.
* @param[in] chan: Rx DMA channel number
* @param[in] budget: Threshold for reading the packets at a time.
* @param[in] more_data_avail: Pointer to more data available flag. OSI fills
* @param[out] more_data_avail: Pointer to more data available flag. OSI fills
* this flag if more rx packets available to read(1) or not(0).
*
* @pre
@@ -1081,7 +1081,7 @@ nve32_t osi_process_rx_completions(struct osi_dma_priv_data *osi_dma,
* - Takes care of initializing the tx, rx ring and descriptors
* based on the number of channels selected.
*
* @param[in] osi_dma: OSI DMA private data.
* @param[in, out] osi_dma: OSI DMA private data.
*
* @pre
* - Allocate memory for osi_dma
@@ -1166,7 +1166,7 @@ nve32_t osi_hw_dma_deinit(struct osi_dma_priv_data *osi_dma);
/**
* @brief osi_init_dma_ops - Initialize DMA operations
*
* @param[in] osi_dma: OSI DMA private data.
* @param[in, out] osi_dma: OSI DMA private data.
*
* @note
* Traceability Details:
@@ -1307,7 +1307,7 @@ nve32_t osi_validate_dma_regs(struct osi_dma_priv_data *osi_dma);
* - This function will be invoked by OSD layer to clear the
* tx stats mentioned in osi_dma->pkt_err_stats structure
*
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in, out] osi_dma: OSI DMA private data structure.
*
* @pre
* - MAC needs to be out of reset and proper clocks need to be configured.
@@ -1341,7 +1341,7 @@ nve32_t osi_clear_tx_pkt_err_stats(struct osi_dma_priv_data *osi_dma);
* Algorithm:
* - Set or reset the slot function based on set input
*
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in, out] osi_dma: OSI DMA private data structure.
* @param[in] set: Flag to set with OSI_ENABLE and reset with OSI_DISABLE
*
* @pre MAC should be init and started. see osi_start_mac()
@@ -1375,7 +1375,7 @@ nve32_t osi_config_slot_function(struct osi_dma_priv_data *osi_dma,
* - This function will be invoked by OSD layer to clear the
* rx_crc_error mentioned in osi_dma->pkt_err_stats structure.
*
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in, out] osi_dma: OSI DMA private data structure.
*
*
* @pre

10
osi/core/eqos_core.c
View File

@@ -1190,7 +1190,7 @@ static void eqos_configure_rxq_priority(
* - Disable MMC interrupts and Configure the MMC counters
* - Enable required MAC interrupts
*
* @param[in] osi_core: OSI core private data structure.
* @param[in, out] osi_core: OSI core private data structure.
*
* @pre MAC has to be out of reset.
*
@@ -1572,7 +1572,7 @@ static void eqos_handle_mac_intrs(struct osi_core_priv_data *const osi_core,
* Algorithm:
* - increment error stats based on corresponding bit filed.
*
* @param[in] osi_core: OSI core private data structure.
* @param[in, out] osi_core: OSI core private data structure.
* @param[in] dma_sr: Dma status register read value
* @param[in] qinx: Queue index
*
@@ -2364,7 +2364,7 @@ static inline void eqos_helper_l3l4_bitmask(nveu32_t *bitmask,
* is used to configure L3((IPv4/IPv6) filters resister
* for address matching.
*
* @param[in] osi_core: OSI core private data structure.
* @param[in, out] osi_core: OSI core private data structure.
* @param[in] filter_no: filter index
* @param[in] enb_dis: 1 - enable otherwise - disable L3 filter
* @param[in] ipv4_ipv6_match: 1 - IPv6, otherwise - IPv4
@@ -2548,7 +2548,7 @@ static nve32_t eqos_config_l3_filters(
* - This sequence is used to configure L4(TCP/UDP) filters for
* SA and DA Port Number matching
*
* @param[in] osi_core: OSI core private data structure.
* @param[in, out] osi_core: OSI core private data structure.
* @param[in] filter_no: filter index
* @param[in] enb_dis: 1 - enable, otherwise - disable L4 filter
* @param[in] tcp_udp_match: 1 - udp, 0 - tcp
@@ -4150,7 +4150,7 @@ static inline nve32_t eqos_restore_registers(
* - MDC clock rate will be populated OSI core private data structure
* based on AXI_CBB clock rate.
*
* @param[in] osi_core: OSI core private data structure.
* @param[in, out] osi_core: OSI core private data structure.
* @param[in] csr_clk_rate: CSR (AXI CBB) clock rate.
*
* @pre OSD layer needs get the AXI CBB clock rate with OSD clock API

6
osi/core/eqos_mmc.c
View File

@@ -34,7 +34,7 @@
* - Read the registers, check for boundary, if more, reset
* counters else return same to caller.
*
* @param[in] osi_core: OSI core private data structure.
* @param[in, out] osi_core: OSI core private data structure.
* @param[in] last_value: previous value of stats variable.
* @param[in] offset: HW register offset
*
@@ -77,7 +77,7 @@ static inline nveu64_t update_mmc_val(struct osi_core_priv_data *osi_core,
* @brief eqos_reset_mmc - To reset MMC registers and ether_mmc_counter
* structure variable
*
* @param[in] osi_core: OSI core private data structure.
* @param[in, out] osi_core: OSI core private data structure.
*
* @pre
* - MAC should be init and started. see osi_start_mac()
@@ -109,7 +109,7 @@ void eqos_reset_mmc(struct osi_core_priv_data *osi_core)
* - Pass register offset and old value to helper function and
* update structure.
*
* @param[in] osi_core: OSI core private data structure.
* @param[in, out] osi_core: OSI core private data structure.
*
* @pre
* - MAC should be init and started. see osi_start_mac()

2
osi/dma/eqos_dma.c
View File

@@ -774,7 +774,7 @@ static nve32_t eqos_init_dma_channel(struct osi_dma_priv_data *osi_dma)
* @brief eqos_set_rx_buf_len - Set Rx buffer length
* Sets the Rx buffer length based on the new MTU size set.
*
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in, out] osi_dma: OSI DMA private data structure.
*
* @pre
* - MAC needs to be out of reset and proper clocks need to be configured

2
osi/dma/osi_dma.c
View File

@@ -315,7 +315,7 @@ static inline nve32_t rx_dma_desc_validate_args(
*
* @param[in] osi_dma: OSI DMA private data struture.
* @param[in] rx_ring: HW ring corresponding to Rx DMA channel.
* @param[in] rx_desc: Rx Rx descriptor.
* @param[in, out] rx_desc: Rx Rx descriptor.
*
* @note
* API Group:

2
osi/dma/osi_dma_local.h
View File

@@ -37,7 +37,7 @@
* - Transmit and Receive descriptors will be initialized with
* required values so that MAC DMA can understand and act accordingly.
*
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in, out] osi_dma: OSI DMA private data structure.
*
* @note
* API Group:

42
osi/dma/osi_dma_txrx.c
View File

@@ -44,8 +44,8 @@
* - Run time: Yes
* - De-initialization: No
*
* @param[in] rx_desc: Rx descriptor
* @param[in] rx_pkt_cx: Per-Rx packet context structure
* @param[in, out] rx_desc: Rx descriptor
* @param[in, out] rx_pkt_cx: Per-Rx packet context structure
*/
static inline void get_rx_csum(struct osi_rx_desc *rx_desc,
struct osi_rx_pkt_cx *rx_pkt_cx)
@@ -115,7 +115,7 @@ static inline void get_rx_csum(struct osi_rx_desc *rx_desc,
* - De-initialization: No
*
* @param[in] rx_desc: Rx descriptor
* @param[in] rx_pkt_cx: Per-Rx packet context structure
* @param[in, out] rx_pkt_cx: Per-Rx packet context structure
*/
static inline void get_rx_vlan_from_desc(struct osi_rx_desc *rx_desc,
struct osi_rx_pkt_cx *rx_pkt_cx)
@@ -181,7 +181,7 @@ static inline nve32_t get_rx_tstamp_status(struct osi_rx_desc *context_desc)
* @param[in] osi_dma: OSI private data structure.
* @param[in] rx_desc: Rx descriptor
* @param[in] context_desc: Rx context descriptor
* @param[in] rx_pkt_cx: Rx packet context
* @param[in, out] rx_pkt_cx: Rx packet context
*
* @note
* API Group:
@@ -259,7 +259,8 @@ static nve32_t get_rx_hwstamp(struct osi_dma_priv_data *osi_dma,
* - De-initialization: No
*
* @param[in] rx_desc: Rx Descriptor.
* @param[in] pkt_err_stats: Packet error stats which stores the errors reported
* @param[in, out] pkt_err_stats: Packet error stats which stores the errors
* reported
*/
static inline void get_rx_err_stats(struct osi_rx_desc *rx_desc,
struct osi_pkt_err_stats *pkt_err_stats)
@@ -292,8 +293,8 @@ static inline void get_rx_err_stats(struct osi_rx_desc *rx_desc,
* @param[in] chan: Rx DMA channel number
* @param[in] more_data_avail: Pointer to more data available flag. OSI fills
* this flag if more rx packets available to read(1) or not(0).
* @param[in] rx_ring: OSI DMA channel Rx ring
* @param[in] rx_pkt_cx: OSI DMA receive packet context
* @param[out] rx_ring: OSI DMA channel Rx ring
* @param[out] rx_pkt_cx: OSI DMA receive packet context
*
* @note
* API Group:
@@ -509,7 +510,7 @@ nve32_t osi_process_rx_completions(struct osi_dma_priv_data *osi_dma,
* - Run time: Yes
* - De-initialization: No
*
* @param[in] osi_dma: Pointer to OSI DMA private data structure.
* @param[in, out] osi_dma: Pointer to OSI DMA private data structure.
* @param[in] chan: DMA channel number for which stats should be incremented.
*/
static inline void inc_tx_pkt_stats(struct osi_dma_priv_data *osi_dma,
@@ -537,7 +538,8 @@ static inline void inc_tx_pkt_stats(struct osi_dma_priv_data *osi_dma,
* - De-initialization: No
*
* @param[in] tx_desc: Tx Descriptor.
* @param[in] pkt_err_stats: Packet error stats which stores the errors reported
* @param[in, out] pkt_err_stats: Packet error stats which stores the errors
* reported
*/
static inline void get_tx_err_stats(struct osi_tx_desc *tx_desc,
struct osi_pkt_err_stats *pkt_err_stats)
@@ -679,7 +681,7 @@ nve32_t osi_clear_rx_pkt_err_stats(struct osi_dma_priv_data *osi_dma)
*
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in] chan: Tx DMA channel number
* @param[in] tx_ring: OSI DMA channel Rx ring
* @param[out] tx_ring: OSI DMA channel Rx ring
*
* @note
* API Group:
@@ -835,8 +837,8 @@ nve32_t osi_process_tx_completions(struct osi_dma_priv_data *osi_dma,
* - If set, set the context descriptor bit along
* with other context information in the transmit descriptor.
*
* @param[in] tx_pkt_cx: Pointer to transmit packet context structure
* @param[in] tx_desc: Pointer to transmit descriptor to be filled.
* @param[in, out] tx_pkt_cx: Pointer to transmit packet context structure
* @param[in, out] tx_desc: Pointer to transmit descriptor to be filled.
*
* @note
* API Group:
@@ -898,9 +900,9 @@ static inline nve32_t need_cntx_desc(struct osi_tx_pkt_cx *tx_pkt_cx,
* - Run time: Yes
* - De-initialization: No
*
* @param[in] tx_ring: DMA channel TX ring.
* @param[in] tx_pkt_cx: Pointer to transmit packet context structure
* @param[in] tx_desc: Pointer to transmit descriptor to be filled.
* @param[in, out] tx_ring: DMA channel TX ring.
* @param[in, out] tx_pkt_cx: Pointer to transmit packet context structure
* @param[in, out] tx_desc: Pointer to transmit descriptor to be filled.
* @param[in] tx_swcx: Pointer to corresponding tx descriptor software context.
*/
static inline void fill_first_desc(struct osi_tx_ring *tx_ring,
@@ -1009,8 +1011,8 @@ static inline void dmb_oshst(void)
*
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in] chan: Tx DMA channel number
* @param[in] ops: OSI DMA Channel operations
* @param[in] tx_ring: OSI DMA channel Tx ring
* @param[out] ops: OSI DMA Channel operations
* @param[out] tx_ring: OSI DMA channel Tx ring
*
* @note
* API Group:
@@ -1211,7 +1213,7 @@ void osi_hw_transmit(struct osi_dma_priv_data *osi_dma, nveu32_t chan)
* set OWN bit, Rx ring length and set starting address of Rx DMA channel.
* Tx ring base address in Tx DMA registers.
*
* @param[in] osi_dma: OSI private data structure.
* @param[in, out] osi_dma: OSI private data structure.
* @param[in] chan: Rx channel number.
*
* @note
@@ -1321,7 +1323,7 @@ static nve32_t rx_dma_desc_initialization(struct osi_dma_priv_data *osi_dma,
* set OWN bit, Rx ring length and set starting address of Rx DMA channel.
* Tx ring base address in Tx DMA registers.
*
* @param[in] osi_dma: OSI private data structure.
* @param[in, out] osi_dma: OSI private data structure.
*
* @note
* API Group:
@@ -1358,7 +1360,7 @@ static nve32_t rx_dma_desc_init(struct osi_dma_priv_data *osi_dma)
* - Initialize Transmit descriptors and set Tx ring length,
* Tx ring base address in Tx DMA registers.
*
* @param[in] osi_dma: OSI DMA private data structure.
* @param[in, out] osi_dma: OSI DMA private data structure.
*
* @note
* API Group: