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nvethernetrm: change MAC ipg as per macsec req

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Change MAC ipg value as macsec IAS requirement when
macsec is used

Bug 3335658

Change-Id: Ie681bb0a66b256c32ac6093114fe29c65bf20a07
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2558031
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Mahesh Patil
2021-07-12 16:46:43 -07:00
committed by mobile promotions
parent 581b8ad758
commit 3af55e0c58
6 changed files with 245 additions and 97 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
osi/core/core_local.h
View File

@@ -266,6 +266,10 @@ struct core_ops {
/** Called to configure HW PTP offload feature */
int (*config_ptp_offload)(struct osi_core_priv_data *const osi_core,
struct osi_pto_config *const pto_config);
#ifdef MACSEC_SUPPORT
void (*config_macsec_ipg)(struct osi_core_priv_data *const osi_core,
const nveu32_t enable);
#endif /* MACSEC_SUPPORT */
};

160
osi/core/eqos_core.c
View File

@@ -1590,46 +1590,6 @@ static void eqos_configure_rxq_priority(
}
}
#ifdef MACSEC_SUPPORT
/**
* @brief eqos_config_macsec_ipg - Configure MAC IPG according to macsec IAS
*
* @note
* Algorithm:
* - Increase MAC IPG value to accommodate macsec 32 byte SECTAG.
*
* @param[in] osi_core: OSI core private data.
*
* @pre
* 1) MAC has to be out of reset.
* 2) Shall not use this ipg value in half duplex mode
*
* @note
* API Group:
* - Initialization: Yes
* - Run time: No
* - De-initialization: No
*/
static void eqos_config_macsec_ipg(struct osi_core_priv_data *const osi_core)
{
nveu32_t value;
/* Configure IPG {EIPG,IPG} value according to macsec IAS in
* MAC_Configuration and MAC_Extended_Configuration
* IPG (12 B[default] + 32 B[sectag]) = 352 bits
*/
value = osi_readla(osi_core, (nveu8_t *)osi_core->base + EQOS_MAC_MCR);
value |= (EQOS_MCR_IPG << EQOS_MCR_IPG_SHIFT) & EQOS_MCR_IPG_MASK;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base + EQOS_MAC_MCR);
value = osi_readla(osi_core, (nveu8_t *)osi_core->base + EQOS_MAC_EXTR);
value |= EQOS_MAC_EXTR_EIPGEN;
value |= (EQOS_MAC_EXTR_EIPG << EQOS_MAC_EXTR_EIPG_SHIFT) &
EQOS_MAC_EXTR_EIPG_MASK;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base + EQOS_MAC_EXTR);
}
#endif /* MACSEC_SUPPORT */
/**
* @brief eqos_configure_mac - Configure MAC
*
@@ -1794,11 +1754,6 @@ static void eqos_configure_mac(struct osi_core_priv_data *const osi_core)
if (osi_core->dcs_en != OSI_ENABLE) {
eqos_configure_rxq_priority(osi_core);
}
#ifdef MACSEC_SUPPORT
if (osi_core->mac_ver == OSI_EQOS_MAC_5_30) {
eqos_config_macsec_ipg(osi_core);
}
#endif /* MACSEC_SUPPORT */
}
/**
@@ -2686,6 +2641,49 @@ static void eqos_stop_mac(struct osi_core_priv_data *const osi_core)
EQOS_MAC_MCR_IDX);
}
#ifdef MACSEC_SUPPORT
/**
* @brief eqos_config_mac_tx - Enable/Disable MAC Tx
*
* @note
* Algorithm:
* - Enable or Disables MAC Transmitter
*
* @param[in] osi_core: OSI core private data structure.
* @param[in] enable: Enable or Disable.MAC Tx
*
* @pre MAC init should be complete. See osi_hw_core_init()
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*/
static void eqos_config_mac_tx(struct osi_core_priv_data *const osi_core,
const nveu32_t enable)
{
nveu32_t value;
void *addr = osi_core->base;
if (enable == OSI_ENABLE) {
value = osi_readla(osi_core, (nveu8_t *)addr + EQOS_MAC_MCR);
/* Enable MAC Transmit */
value |= EQOS_MCR_TE;
eqos_core_safety_writel(osi_core, value,
(nveu8_t *)addr + EQOS_MAC_MCR,
EQOS_MAC_MCR_IDX);
} else {
value = osi_readla(osi_core, (nveu8_t *)addr + EQOS_MAC_MCR);
/* Disable MAC Transmit */
value &= ~EQOS_MCR_TE;
eqos_core_safety_writel(osi_core, value,
(nveu8_t *)addr + EQOS_MAC_MCR,
EQOS_MAC_MCR_IDX);
}
}
#endif /* MACSEC_SUPPORT */
/**
* @brief eqos_config_l2_da_perfect_inverse_match - configure register for
* inverse or perfect match.
@@ -6272,6 +6270,75 @@ static nve32_t eqos_config_rss(struct osi_core_priv_data *const osi_core)
return -1;
}
#ifdef MACSEC_SUPPORT
/**
* @brief eqos_config_macsec_ipg - Configure MAC IPG according to macsec IAS
*
* @note
* Algorithm:
* - Stop MAC Tx
* - Update MAC IPG value to accommodate macsec 32 byte SECTAG.
* - Start MAC Tx
*
* @param[in] osi_core: OSI core private data.
* @param[in] enable: enable/disable macsec ipg value in mac
*
* @pre
* 1) MAC has to be out of reset.
* 2) Shall not use this ipg value in half duplex mode
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*/
void eqos_config_macsec_ipg(struct osi_core_priv_data *const osi_core,
const nveu32_t enable)
{
nveu32_t value;
if (osi_core->mac_ver == OSI_EQOS_MAC_5_30) {
/* stop MAC Tx */
eqos_config_mac_tx(osi_core, OSI_DISABLE);
if (enable == OSI_ENABLE) {
/* Configure IPG {EIPG,IPG} value according to macsec IAS in
* MAC_Configuration and MAC_Extended_Configuration
* IPG (12 B[default] + 32 B[sectag]) = 352 bits
*/
value = osi_readla(osi_core, (nveu8_t *)osi_core->base +
EQOS_MAC_MCR);
value |= (EQOS_MCR_IPG << EQOS_MCR_IPG_SHIFT) &
EQOS_MCR_IPG_MASK;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
EQOS_MAC_MCR);
value = osi_readla(osi_core, (nveu8_t *)osi_core->base +
EQOS_MAC_EXTR);
value |= EQOS_MAC_EXTR_EIPGEN;
value |= (EQOS_MAC_EXTR_EIPG << EQOS_MAC_EXTR_EIPG_SHIFT) &
EQOS_MAC_EXTR_EIPG_MASK;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
EQOS_MAC_EXTR);
} else {
/* reset to default IPG 12B */
value = osi_readla(osi_core, (nveu8_t *)osi_core->base +
EQOS_MAC_MCR);
value &= ~EQOS_MCR_IPG_MASK;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
EQOS_MAC_MCR);
value = osi_readla(osi_core, (nveu8_t *)osi_core->base +
EQOS_MAC_EXTR);
value &= ~EQOS_MAC_EXTR_EIPGEN;
value &= ~EQOS_MAC_EXTR_EIPG_MASK;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
EQOS_MAC_EXTR);
}
/* start MAC Tx */
eqos_config_mac_tx(osi_core, OSI_ENABLE);
}
}
#endif /* MACSEC_SUPPORT */
/**
* @brief eqos_get_core_safety_config - EQOS MAC safety configuration
*
@@ -6344,4 +6411,7 @@ void eqos_init_core_ops(struct core_ops *ops)
ops->update_frp_entry = eqos_update_frp_entry;
ops->update_frp_nve = eqos_update_frp_nve;
ops->config_rss = eqos_config_rss;
#ifdef MACSEC_SUPPORT
ops->config_macsec_ipg = eqos_config_macsec_ipg;
#endif /* MACSEC_SUPPORT */
}

2
osi/core/eqos_core.h
View File

@@ -206,7 +206,7 @@
#define EQOS_PAD_AUTO_CAL_CFG_START OSI_BIT(31)
#define EQOS_PAD_AUTO_CAL_STAT_ACTIVE OSI_BIT(31)
#define EQOS_PAD_CRTL_E_INPUT_OR_E_PWRD OSI_BIT(31)
#define EQOS_MCR_IPG_MASK 0x700000U
#define EQOS_MCR_IPG_MASK 0x7000000U
#define EQOS_MCR_IPG_SHIFT 24U
#define EQOS_MCR_IPG 0x7U
#define EQOS_MCR_IPC OSI_BIT(27)

31
osi/core/macsec.c
View File

@@ -2448,11 +2448,21 @@ static nve32_t clear_lut(struct osi_core_priv_data *const osi_core)
static nve32_t macsec_deinit(struct osi_core_priv_data *const osi_core)
{
nveu32_t i;
struct core_local *l_core = (struct core_local *)osi_core;
for (i = OSI_CTLR_SEL_TX; i <= OSI_CTLR_SEL_RX; i++) {
osi_memset(&osi_core->macsec_lut_status[i], OSI_NONE,
sizeof(struct osi_macsec_lut_status));
}
/* Update MAC ipg value as per macsec requirement */
if (l_core->ops_p->config_macsec_ipg != OSI_NULL) {
l_core->ops_p->config_macsec_ipg(osi_core, OSI_DISABLE);
} else {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
"Failed config macsec IPG\n", 0ULL);
}
return 0;
}
@@ -2461,6 +2471,7 @@ static nve32_t macsec_init(struct osi_core_priv_data *const osi_core)
nveu32_t val = 0;
struct osi_macsec_lut_config lut_config = {0};
struct osi_macsec_table_config *table_config = &lut_config.table_config;
struct core_local *l_core = (struct core_local *)osi_core;
/* Store MAC address in reverse, per HW design */
nveu8_t mac_da_mkpdu[OSI_ETH_ALEN] = {0x3, 0x0, 0x0,
0xC2, 0x80, 0x01};
@@ -2471,7 +2482,15 @@ static nve32_t macsec_init(struct osi_core_priv_data *const osi_core)
nve32_t ret = 0;
nveu16_t i, j;
/* 1. Set MTU */
/* Update MAC ipg value as per macsec requirement */
if (l_core->ops_p->config_macsec_ipg != OSI_NULL) {
l_core->ops_p->config_macsec_ipg(osi_core, OSI_ENABLE);
} else {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
"Failed config macsec IPG\n", 0ULL);
}
/* Set MTU */
val = osi_readla(osi_core, addr + MACSEC_TX_MTU_LEN);
pr_err("Read MACSEC_TX_MTU_LEN: 0x%x\n", val);
val &= ~(MTU_LENGTH_MASK);
@@ -2505,7 +2524,7 @@ static nve32_t macsec_init(struct osi_core_priv_data *const osi_core)
osi_writela(osi_core, val, addr + MACSEC_RX_SOT_DELAY);
}
/* 2. Set essential MACsec control configuration */
/* Set essential MACsec control configuration */
val = osi_readla(osi_core, addr + MACSEC_CONTROL0);
pr_err("Read MACSEC_CONTROL0: 0x%x\n", val);
val |= (MACSEC_TX_LKUP_MISS_NS_INTR | MACSEC_RX_LKUP_MISS_NS_INTR |
@@ -2539,7 +2558,7 @@ static nve32_t macsec_init(struct osi_core_priv_data *const osi_core)
pr_err("Write MACSEC_STATS_CONTROL_0: 0x%x\n", val);
osi_writela(osi_core, val, addr + MACSEC_STATS_CONTROL_0);
/* 3. Enable default interrupts needed */
/* Enable default interrupts needed */
val = osi_readla(osi_core, addr + MACSEC_TX_IMR);
pr_err("Read MACSEC_TX_IMR: 0x%x\n", val);
val |= (MACSEC_TX_DBG_BUF_CAPTURE_DONE_INT_EN |
@@ -2576,11 +2595,11 @@ static nve32_t macsec_init(struct osi_core_priv_data *const osi_core)
pr_err("Write MACSEC_COMMON_IMR: 0x%x\n", val);
osi_writela(osi_core, val, addr + MACSEC_COMMON_IMR);
/* 4. Set AES mode
/* Set AES mode
* Default power on reset is AES-GCM128, leave it.
*/
/* 5. Invalidate LUT entries */
/* Invalidate LUT entries */
ret = clear_lut(osi_core);
if (ret < 0) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
@@ -2588,7 +2607,7 @@ static nve32_t macsec_init(struct osi_core_priv_data *const osi_core)
return ret;
}
/* 6. Set default BYP for MKPDU/BC packets */
/* Set default BYP for MKPDU/BC packets */
table_config->rw = OSI_LUT_WRITE;
lut_config.lut_sel = OSI_LUT_SEL_BYPASS;
lut_config.flags |= (OSI_LUT_FLAGS_DA_VALID |

144
osi/core/mgbe_core.c
View File

@@ -2505,47 +2505,6 @@ static int mgbe_config_flow_control(struct osi_core_priv_data *const osi_core,
return 0;
}
#ifdef MACSEC_SUPPORT
/**
* @brief mgbe_config_macsec_ipg - Configure MAC IPG according to macsec IAS
*
* @note
* Algorithm:
* - Increase MAC IPG value to accommodate macsec 32 byte SECTAG.
*
* @param[in] osi_core: OSI core private data.
*
* @pre
* 1) MAC has to be out of reset.
* 2) Shall not use this ipg value in half duplex mode
*
* @note
* API Group:
* - Initialization: Yes
* - Run time: No
* - De-initialization: No
*/
static void mgbe_config_macsec_ipg(struct osi_core_priv_data *const osi_core)
{
nveu32_t value = 0U;
/* Configure IPG {EIPG,IPG} value according to macsec IAS in
* MAC_Tx_Configuration and MAC_Extended_Configuration
* IPG (12 B[default] + 32 B[sectag]) = 352 bits
*/
value = osi_readla(osi_core, (nveu8_t *)osi_core->base + MGBE_MAC_TMCR);
value &= ~MGBE_MAC_TMCR_IPG_MASK;
value |= MGBE_MAC_TMCR_IFP;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base + MGBE_MAC_TMCR);
value = osi_readla(osi_core, (nveu8_t *)osi_core->base +
MGBE_MAC_EXT_CNF);
value |= MGBE_MAC_EXT_CNF_EIPG;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
MGBE_MAC_EXT_CNF);
}
#endif /* MACSEC_SUPPORT */
/**
* @brief mgbe_configure_mac - Configure MAC
*
@@ -2689,10 +2648,6 @@ static int mgbe_configure_mac(struct osi_core_priv_data *osi_core)
}
/* TODO: USP (user Priority) to RxQ Mapping */
#ifdef MACSEC_SUPPORT
mgbe_config_macsec_ipg(osi_core);
#endif /* MACSEC_SUPPORT */
/* RSS cofiguration */
return mgbe_config_rss(osi_core);
}
@@ -3985,6 +3940,37 @@ static void mgbe_stop_mac(struct osi_core_priv_data *const osi_core)
osi_writela(osi_core, value, (nveu8_t *)addr + MGBE_MAC_RMCR);
}
#ifdef MACSEC_SUPPORT
/**
* @brief mgbe_config_mac_tx - Enable/Disable MAC Tx
*
* Algorithm: Enable/Disable MAC Transmitter engine
*
* @param[in] osi_core: OSI core private data structure.
* @param[in] enable: Enable or Disable.MAC Tx
*
* @note 1) MAC init should be complete. See osi_hw_core_init()
*/
static void mgbe_config_mac_tx(struct osi_core_priv_data *const osi_core,
const nveu32_t enable)
{
nveu32_t value;
void *addr = osi_core->base;
if (enable == OSI_ENABLE) {
value = osi_readla(osi_core, (nveu8_t *)addr + MGBE_MAC_TMCR);
/* Enable MAC Transmit */
value |= MGBE_MAC_TMCR_TE;
osi_writela(osi_core, value, (nveu8_t *)addr + MGBE_MAC_TMCR);
} else {
value = osi_readla(osi_core, (nveu8_t *)addr + MGBE_MAC_TMCR);
/* Disable MAC Transmit */
value &= ~MGBE_MAC_TMCR_TE;
osi_writela(osi_core, value, (nveu8_t *)addr + MGBE_MAC_TMCR);
}
}
#endif /* MACSEC_SUPPORT */
/**
* @brief mgbe_core_deinit - MGBE MAC core deinitialization
*
@@ -5598,6 +5584,71 @@ static void mgbe_set_mdc_clk_rate(struct osi_core_priv_data *const osi_core,
{
}
#ifdef MACSEC_SUPPORT
/**
* @brief mgbe_config_macsec_ipg - Configure MAC IPG according to macsec IAS
*
* @note
* Algorithm:
* - Stop MAC Tx
* - Update MAC IPG value to accommodate macsec 32 byte SECTAG.
* - Start MAC Tx
*
* @param[in] osi_core: OSI core private data.
* @param[in] enable: Enable or Disable MAC Tx engine
*
* @pre
* 1) MAC has to be out of reset.
* 2) Shall not use this ipg value in half duplex mode
*
* @note
* API Group:
* - Initialization: No
* - Run time: Yes
* - De-initialization: No
*/
void mgbe_config_macsec_ipg(struct osi_core_priv_data *const osi_core,
const nveu32_t enable)
{
nveu32_t value = 0U;
/* stop MAC Tx */
mgbe_config_mac_tx(osi_core, OSI_DISABLE);
if (enable == OSI_ENABLE) {
/* Configure IPG {EIPG,IPG} value according to macsec IAS in
* MAC_Tx_Configuration and MAC_Extended_Configuration
* IPG (12 B[default] + 32 B[sectag]) = 352 bits
*/
value = osi_readla(osi_core, (nveu8_t *)osi_core->base +
MGBE_MAC_TMCR);
value &= ~MGBE_MAC_TMCR_IPG_MASK;
value |= MGBE_MAC_TMCR_IFP;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
MGBE_MAC_TMCR);
value = osi_readla(osi_core, (nveu8_t *)osi_core->base +
MGBE_MAC_EXT_CNF);
value |= MGBE_MAC_EXT_CNF_EIPG;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
MGBE_MAC_EXT_CNF);
} else {
/* Update MAC IPG to default value 12B */
value = osi_readla(osi_core, (nveu8_t *)osi_core->base +
MGBE_MAC_TMCR);
value &= ~MGBE_MAC_TMCR_IPG_MASK;
value &= ~MGBE_MAC_TMCR_IFP;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
MGBE_MAC_TMCR);
value = osi_readla(osi_core, (nveu8_t *)osi_core->base +
MGBE_MAC_EXT_CNF);
value &= ~MGBE_MAC_EXT_CNF_EIPG_MASK;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
MGBE_MAC_EXT_CNF);
}
/* start MAC Tx */
mgbe_config_mac_tx(osi_core, OSI_ENABLE);
}
#endif /* MACSEC_SUPPORT */
/**
* @brief mgbe_init_core_ops - Initialize MGBE MAC core operations
*/
@@ -5659,4 +5710,7 @@ void mgbe_init_core_ops(struct core_ops *ops)
ops->update_frp_nve = mgbe_update_frp_nve;
ops->write_reg = mgbe_write_reg;
ops->read_reg = mgbe_read_reg;
#ifdef MACSEC_SUPPORT
ops->config_macsec_ipg = mgbe_config_macsec_ipg;
#endif /* MACSEC_SUPPORT */
};

1
osi/core/mgbe_core.h
View File

@@ -668,6 +668,7 @@
#define MGBE_MAC_SBD_INTR OSI_BIT(2)
#define MGBE_MAC_EXT_CNF_DDS OSI_BIT(7)
#define MGBE_MAC_EXT_CNF_EIPG 0x1U
#define MGBE_MAC_EXT_CNF_EIPG_MASK 0x7FU
/* TX timestamp */
#define MGBE_MAC_TSS_TXTSC OSI_BIT(15)
/** @} */