Merge remote-tracking branch 'origin/dev/t264-ethernet' into dev-t264

Bug 4687787

Change-Id: Ie3411c626b31d1ed4b536954c7e5a875aab29e86
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>

include/config.tmk

@@ -47,4 +47,5 @@ endif
 #NV_COMPONENT_CFLAGS += -DMACSEC_KEY_PROGRAM
 HSI_SUPPORT := 1
 MACSEC_SUPPORT := 1
+#MACSEC_KEY_PROGRAM := 1
 ccflags-y += $(NV_COMPONENT_CFLAGS)

include/mmc.h

@@ -60,6 +60,8 @@ struct osi_macsec_mmc_counters {
 	/** This counter provides the number of octets after IVC passing
 	 * valid values are between 0 and UINT64_MAX */
 	nveul64_t rx_octets_validated;
+	/** This counter provides the number of octets after decryption */
+	nveul64_t rx_octets_decrypted;
 	/** This counter provides the number not valid packets
 	 * valid values are between 0 and UINT64_MAX */
 	nveul64_t rx_pkts_not_valid[OSI_MACSEC_SC_INDEX_MAX];
@@ -84,9 +86,13 @@ struct osi_macsec_mmc_counters {
 	/** This counter provides the number of out packets protected
 	 * valid values are between 0 and UINT64_MAX */
 	nveul64_t tx_pkts_protected[OSI_MACSEC_SC_INDEX_MAX];
+	/** This counter provides the number of out packets encrypted */
+	nveul64_t tx_pkts_encrypted[OSI_MACSEC_SC_INDEX_MAX];
 	/** This counter provides the number of out octets protected/
 	 * valid values are between 0 and UINT64_MAX */
 	nveul64_t tx_octets_protected;
+	/** This counter provides the number of out octets encrypted */
+	nveul64_t tx_octets_encrypted;
 };
 #endif /* MACSEC_SUPPORT */
 #endif /* INCLUDED_MMC_H */

include/nvethernetrm_export.h

@@ -137,7 +137,9 @@ struct osi_core_frp_cmd {
 	 * Bit[0] - DMA channel 0
 	 * ..
 	 * Bit [N] - DMA channel N] */
-	nveu32_t dma_sel;
+	nveu64_t dma_sel;
+	/** OSD DCHT */
+	nveu8_t dcht;
 };
 
 /**

include/nvethernetrm_l3l4.h

@@ -47,6 +47,9 @@ struct osi_l3_l4_filter {
 		nveu32_t is_udp;
 		/** ipv6 (OSI_L3L4_ENABLE) or ipv4 (OSI_L3L4_DISABLE) */
 		nveu32_t is_ipv6;
+		/** match combined L3, L4 filters (OSI_TRUE) or ignore L3,L4
+		 * combined filter match (OSI_FALSE) */
+		nveu32_t is_l3l4_match_en;
 #endif /* !OSI_STRIPPED_LIB */
 		struct {
 			/** ipv4 address

include/osi_common.h

@@ -51,6 +51,8 @@
 #define OSI_LOCKED		0x1U
 /** @brief Number of Nano seconds per second */
 #define OSI_NSEC_PER_SEC	1000000000ULL
+#define OSI_MGBE_MAX_RX_RIIT_NSEC	17500U
+#define OSI_MGBE_MIN_RX_RIIT_NSEC	535U
 #ifndef OSI_STRIPPED_LIB
 #define OSI_MAX_RX_COALESCE_USEC	1020U
 #define OSI_EQOS_MIN_RX_COALESCE_USEC	5U
@@ -208,11 +210,14 @@
 #define OSI_EQOS_MAX_NUM_QUEUES		8U
 /** @brief Maximum number of L3L4 filters supported */
 #define OSI_MGBE_MAX_L3_L4_FILTER	8U
+/** @brief Maximum number of L3L4 filters supported for T264 */
+#define OSI_MGBE_MAX_L3_L4_FILTER_T264	48U
 /**
  * @brief Maximum number of channels in MGBE
  */
-//TBD: T264, NET04 supports only 10 VDMA
+//TBD: T264, NET05 supports only 20 VDMA, change to 48 later
-#define OSI_MGBE_MAX_NUM_CHANS		10U
+#define OSI_MGBE_MAX_NUM_CHANS		20U
+#define OSI_MGBE_T23X_MAX_NUM_CHANS	10U
 /**
  * @brief Maximum number of PDMA channels in MGBE
  */
@@ -220,6 +225,8 @@
 /** @brief Maximum number of queues in MGBE */
 #define OSI_MGBE_MAX_NUM_QUEUES		10U
 #define OSI_EQOS_XP_MAX_CHANS		4U
+/* max riit DT configs for supported speeds */
+#define OSI_MGBE_MAX_NUM_RIIT		4U
 
 /**
  * @brief Maximum number of Secure Channels supported
@@ -241,6 +248,15 @@
 /** @brief flag indicating MGBE MAC on T26X */
 #define OSI_MAC_HW_MGBE_T26X	2U
 
+/** MAC version type for EQOS version previous to 5.30 */
+#define MAC_CORE_VER_TYPE_EQOS		0U
+/** MAC version type for EQOS version 5.30 */
+#define MAC_CORE_VER_TYPE_EQOS_5_30	1U
+/** MAC version type for MGBE IP */
+#define MAC_CORE_VER_TYPE_MGBE		2U
+/** MAC version type for T26x EQOS version 5.40 */
+#define MAC_CORE_VER_TYPE_EQOS_5_40	3U
+
 #define OSI_NULL                ((void *)0)
 /** Enable Flag */
 #define OSI_ENABLE		1U
@@ -252,6 +268,7 @@
 #define OSI_H_ENABLE		(~OSI_H_DISABLE)
 
 #define OSI_BIT(nr)             ((nveu32_t)1 << (((nveu32_t)nr) & 0x1FU))
+#define OSI_BIT_64(nr)          ((nveu64_t)1 << (nr))
 
 #ifndef OSI_STRIPPED_LIB
 #define OSI_MGBE_MAC_3_00	0x30U
@@ -264,10 +281,11 @@
 #define OSI_EQOS_MAC_5_00       0x50U
 /** @brief EQOS MAC version Orin */
 #define OSI_EQOS_MAC_5_30       0x53U
+#define OSI_EQOS_MAC_5_40       0x54U
 /** @brief MGBE MAC version Orin */
 #define OSI_MGBE_MAC_3_10	0x31U
-//TBD: T264 NET04 version, update it later
 #define OSI_MGBE_MAC_3_20	0x32U
+#define OSI_MGBE_MAC_4_20	0x42U
 
 /**
  * @brief Maximum number of VM IRQs

include/osi_core.h

@@ -217,6 +217,7 @@ typedef my_lint_64		nvel64_t;
 #define EQOS_MAX_MAC_5_3_ADDRESS_FILTER	32U
 #define EQOS_MAX_L3_L4_FILTER		8U
 #define OSI_MGBE_MAX_MAC_ADDRESS_FILTER	32U
+#define OSI_MGBE_MAX_MAC_ADDRESS_FILTER_T26X	48U
 #define OSI_DA_MATCH			0U
 #ifndef OSI_STRIPPED_LIB
 #define OSI_INV_MATCH			1U
@@ -287,6 +288,15 @@ typedef my_lint_64		nvel64_t;
 #define OSI_XFI_MODE_5G		1U
 #define OSI_USXGMII_MODE_10G	2U
 #define OSI_USXGMII_MODE_5G	3U
+#define OSI_XAUI_MODE_25G	4U
+/**
+ * @brief Ethernet UPHY GBE Modes
+ */
+#define OSI_GBE_MODE_5G		0U
+#define OSI_GBE_MODE_10G	1U
+#define OSI_UPHY_GBE_MODE_25G	2U
+#define OSI_GBE_MODE_1G		3U
+#define OSI_GBE_MODE_2_5G	4U
 
 /**
  * @addtogroup IOCTL OPS MACROS
@@ -502,7 +512,8 @@ typedef my_lint_64		nvel64_t;
 
 #define VLAN_NUM_VID		4096U
 #define OSI_DELAY_1000US	1000U
-
+#define OSI_DELAY_1US		1U
+#define RCHLIST_SIZE		48U
 /**
  * @addtogroup PTP PTP related information
  *
@@ -740,7 +751,18 @@ struct osi_filter {
 	/** src_dest: SA(1) or DA(0) */
 	nveu32_t src_dest;
 	/**  indicates one hot encoded DMA receive channels to program */
-	nveu32_t dma_chansel;
+	nveu64_t dma_chansel;
+	/** Indicates packet duplication enable(1) disable (0) */
+	nveu32_t pkt_dup;
+};
+
+/**
+ * @brief OSI core structure for RCHlist
+ */
+struct rchlist_index {
+	nveu8_t mac_address[OSI_ETH_ALEN];
+	nveu32_t in_use;
+	nveu64_t dch;
 };
 
 #ifndef OSI_STRIPPED_LIB
@@ -1300,6 +1322,17 @@ struct osi_macsec_sc_info {
 	/** flag indicating the prosition of vlan tag
 	 * valid values are either 0(vlan not in clear) or 1(vlan in clear) */
 	nveu8_t vlan_in_clear;
+        /** Indicates 1 bit for encription configuration
+        0: Indicates disabled
+        1: Indicates enabled
+        */
+        nveu8_t encrypt;
+        /** Indicates 2 bit for confidentiality offset configuration
+        0: Indicates offset as 0
+        1: Indicates offset as 30
+        2: Indicates offset as 50
+        */
+        nveu8_t conf_offset;
 };
 
 /**
@@ -1408,8 +1441,12 @@ struct osi_core_frp_data {
 	/** Entry OK Index - Next Instruction
 	 * valid values are from 0 to 0xFF */
 	nveu8_t ok_index;
+	/** Entry dcht */
+	nveu8_t dcht;
 	/** Entry DMA Channel selection (1-bit for each channel) */
-	nveu32_t dma_chsel;
+	nveu64_t dma_chsel;
+	/** Entry RChlist index */
+	nve32_t rchlist_indx;
 };
 
 /**
@@ -1435,6 +1472,8 @@ struct osi_core_tx_ts {
 	/** Packet ID for corresponding timestamp
 	 * valid values are from 1 to 0x3FF*/
 	nveu32_t pkt_id;
+	/** vdma ID for corresponding timestamp */
+	nveu32_t vdma_id;
 	/** Time in seconds*/
 	nveu32_t sec;
 	/** Time in nano seconds */
@@ -1656,6 +1695,8 @@ struct osi_core_priv_data {
 	 * valid values are NVETHERNETRM_PIF$OSI_MAC_HW_EQOS and
 	 * NVETHERNETRM_PIF$OSI_MAC_HW_MGBE*/
 	nveu32_t mac;
+	/** MACSEC HW type based on DT compatible */
+	nveu32_t macsec;
 	/** MAC version
 	 * valid values are NVETHERNETRM_PIF$OSI_EQOS_MAC_5_00,
 	 * NVETHERNETRM_PIF$OSI_EQOS_MAC_5_30
@@ -1731,7 +1772,7 @@ struct osi_core_priv_data {
 #if !defined(L3L4_WILDCARD_FILTER)
 	/** L3L4 filter bit bask, set index corresponding bit for
 	 * filter if filter enabled */
-	nveu32_t l3l4_filter_bitmask;
+	nveu64_t l3l4_filter_bitmask;
 #endif /* !L3L4_WILDCARD_FILTER */
 	/** Flag which decides virtualization is enabled(1) or disabled(0) */
 	nveu32_t use_virtualization;
@@ -1739,7 +1780,7 @@ struct osi_core_priv_data {
 	struct osi_hw_features *hw_feature;
 	/** MC packets Multiple DMA channel selection flags */
 	nveu32_t mc_dmasel;
-	/** UPHY GBE mode (1 for 10G, 0 for 5G) */
+	/** UPHY GBE mode (2 for 25F, 1 for 10G, 0 for 5G) */
 	nveu32_t uphy_gbe_mode;
 	/** number of PDMA's */
 	nveu32_t num_of_pdma;
@@ -1754,7 +1795,8 @@ struct osi_core_priv_data {
 	/** number of VM IRQ's
 	 * Fixed value filled by NvEthernet unit as 4*/
 	nveu32_t num_vm_irqs;
-	/** PHY interface mode (0/1 for XFI 10/5G, 2/3 for USXGMII 10/5) */
+	/** PHY interface mode (0/1 for XFI 10/5G, 2/3 for USXGMII 10/5)
+	 * (4 for XFI 25G) (5 for USXGMII 25G */
 	nveu32_t phy_iface_mode;
 	/** MGBE MAC instance ID's
 	 * valid values are from 0 to 4 
@@ -1774,6 +1816,8 @@ struct osi_core_priv_data {
 #endif
 	/** pre-silicon flag */
 	nveu32_t pre_sil;
+	/** rCHlist bookkeeping **/
+	struct rchlist_index rch_index[RCHLIST_SIZE];
 };
 
 /**

include/osi_dma.h

@@ -59,6 +59,7 @@
 #define OSI_ONE_MEGA_HZ		1000000U
 /** @brief MAX ULLONG value */
 #define OSI_ULLONG_MAX		(~0ULL)
+#define OSI_MSEC_PER_SEC	1000U
 
 /* Compiler hints for branch prediction */
 #define osi_likely(x)			__builtin_expect(!!(x), 1)
@@ -141,6 +142,9 @@
 #define OSI_PKT_CX_IP_CSUM		OSI_BIT(12)
 /** @} */
 
+/** VDMA ID in TDESC0 **/
+#define OSI_PTP_VDMA_SHIFT		10U
+
 #ifndef OSI_STRIPPED_LIB
 /**
  * @addtogroup SLOT function context fields
@@ -265,6 +269,7 @@
 #define OSI_DMA_IOCTL_CMD_STRUCTS_DUMP	2U
 #define OSI_DMA_IOCTL_CMD_DEBUG_INTR_CONFIG	3U
 #endif /* OSI_DEBUG */
+#define OSI_DMA_IOCTL_CMD_RX_RIIT_CONFIG	4U
 /** @} */
 
 /**
@@ -318,6 +323,16 @@ struct osi_pkt_err_stats {
 };
 #endif /* !OSI_STRIPPED_LIB */
 
+/**
+ * @brief RX RIIT value for speed
+ */
+struct osi_rx_riit {
+	/** speed */
+	nveu32_t speed;
+	/** riit value */
+	nveu32_t riit;
+};
+
 /**
  * @brief Receive Descriptor
  */
@@ -452,6 +467,8 @@ struct osi_tx_swcx {
 	 * Max value is NVETHERNETCL_PIF$UINT_MAX
 	 */
 	nveu32_t pktid;
+	/** VDMA id of packet for which TX packet sent for timestamp needed */
+	nveu32_t vdmaid;
 	/** dma channel number for osd use.
 	 *  Max value is NVETHERNETCL_PIF$OSI_EQOS_MAX_NUM_CHANS or
 	 *  NVETHERNETCL_PIF$OSI_MGBE_MAX_NUM_CHANS
@@ -539,6 +556,8 @@ struct osi_txdone_pkt_cx {
 	 *  Max value is NVETHERNETCL_PIF$UINT_MAX
 	 */
 	nveu32_t pktid;
+	/** Passing vdma id to map TX time to packet */
+	nveu32_t vdmaid;
 };
 
 /**
@@ -606,12 +625,12 @@ struct osi_tx_ring {
  * @brief osi_xtra_dma_stat_counters -  OSI DMA extra stats counters
  */
 struct osi_xtra_dma_stat_counters {
-	/** Per Q TX packet count */
+	/** Per chan TX packet count */
-	nveu64_t q_tx_pkt_n[OSI_MGBE_MAX_NUM_QUEUES];
+	nveu64_t chan_tx_pkt_n[OSI_MGBE_MAX_NUM_CHANS];
-	/** Per Q RX packet count */
+	/** Per chan RX packet count */
-	nveu64_t q_rx_pkt_n[OSI_MGBE_MAX_NUM_QUEUES];
+	nveu64_t chan_rx_pkt_n[OSI_MGBE_MAX_NUM_CHANS];
-	/** Per Q TX complete call count */
+	/** Per chan TX complete call count */
-	nveu64_t tx_clean_n[OSI_MGBE_MAX_NUM_QUEUES];
+	nveu64_t tx_clean_n[OSI_MGBE_MAX_NUM_CHANS];
 	/** Total number of tx packets count */
 	nveu64_t tx_pkt_n;
 	/** Total number of rx packet count */
@@ -657,7 +676,7 @@ struct osd_dma_ops {
 #endif /* OSI_DEBUG */
 };
 
-#ifdef OSI_DEBUG
+//#ifdef OSI_DEBUG
 /**
  * @brief The OSI DMA IOCTL data structure.
  */
@@ -667,7 +686,7 @@ struct osi_dma_ioctl_data {
 	/** IOCTL command argument */
 	nveu32_t arg_u32;
 };
-#endif /* OSI_DEBUG */
+//#endif /* OSI_DEBUG */
 
 /**
  * @brief The OSI DMA private data structure.
@@ -721,6 +740,12 @@ struct osi_dma_priv_data {
 	 *  NVETHERNETCL_PIF$OSI_DISABLE
 	 */
 	nveu32_t use_riwt;
+	/** Receive Interrupt Idle Timer in nsec */
+	struct osi_rx_riit rx_riit[OSI_MGBE_MAX_NUM_RIIT];
+	/** num of rx riit configs for different speeds */
+	nveu32_t num_of_riit;
+	/** Flag which decides riit is enabled(1) or disabled(0) */
+	nveu32_t use_riit;
 	/** Max no of pkts to be received before triggering Rx interrupt.
 	 * Max value is NVETHERNETCL_PIF$UINT_MAX
 	 */
@@ -772,9 +797,9 @@ struct osi_dma_priv_data {
 	 * NVETHENETCL_PIF$OSI_PTP_SYNC_TWOSTEP - two step mode
 	 */
 	nveu32_t ptp_flag;
-#ifdef OSI_DEBUG
 	/** OSI DMA IOCTL data */
 	struct osi_dma_ioctl_data ioctl_data;
+#ifdef OSI_DEBUG
 	/** Flag to enable/disable descriptor dump */
 	nveu32_t enable_desc_dump;
 #endif /* OSI_DEBUG */
@@ -1444,7 +1469,7 @@ nveu32_t osi_is_mac_enabled(struct osi_dma_priv_data *const osi_dma);
 nve32_t osi_handle_dma_intr(struct osi_dma_priv_data *osi_dma,
 			    nveu32_t chan, nveu32_t tx_rx, nveu32_t en_dis);
 
-#ifdef OSI_DEBUG
+//#ifdef OSI_DEBUG
 /**
  * @brief
  * Description: OSI DMA IOCTL
@@ -1468,7 +1493,7 @@ nve32_t osi_handle_dma_intr(struct osi_dma_priv_data *osi_dma,
  * @retval -1 on failure - invalid ioctl command within osi data structure
  */
 nve32_t osi_dma_ioctl(struct osi_dma_priv_data *osi_dma);
-#endif /* OSI_DEBUG */
+//#endif /* OSI_DEBUG */
 #ifndef OSI_STRIPPED_LIB
 /**
  * @brief

include/osi_macsec.h

@@ -26,6 +26,7 @@
 #include <osi_core.h>
 
 #ifdef MACSEC_SUPPORT
+
 //////////////////////////////////////////////////////////////////////////
 	/* MACSEC OSI data structures */
 //////////////////////////////////////////////////////////////////////////
@@ -51,6 +52,7 @@
 #endif /* DEBUG_MACSEC */
 /** @brief maximum key index */
 #define OSI_KEY_INDEX_MAX		31U
+#define OSI_KEY_INDEX_MAX_T26X		95U
 /** @brief maximum PN by default */
 #define OSI_PN_MAX_DEFAULT		0xFFFFFFFFU
 /** @brief threshold PN by default */
@@ -59,6 +61,8 @@
 #define OSI_TCI_DEFAULT 		0x1
 /** @brief maximum SCs index */
 #define OSI_SC_INDEX_MAX		15U
+/** @brief maximum SCs index for T26X */
+#define OSI_SC_INDEX_MAX_T26X		47U
 /**
  * @brief Length of ethernet type field
  */
@@ -127,6 +131,10 @@
  * @brief Helper macros for generic table CONFIG register programming
  * @{
  */
+/** @brief MACSEC max ip types */
+#define MAX_MACSEC_IP_TYPES 2
+#define OSI_MACSEC_T23X 0U
+#define OSI_MACSEC_T26X 1U
 /** @brief TX MACSEC controller */
 #define OSI_CTLR_SEL_TX		0U
 /** @brief RX MACSEC controller */
@@ -137,13 +145,15 @@
 /** @brief LUT write operation */
 #define OSI_LUT_WRITE		1U
 #define OSI_RW_MAX		1U
-/** @brief Maximum table index */
-#define OSI_TABLE_INDEX_MAX	31U
 /** @brief Maximum bypass lut table index */
-#define OSI_BYP_LUT_MAX_INDEX	OSI_TABLE_INDEX_MAX
+#define OSI_BYP_LUT_MAX_INDEX	31U
-/** @brief Maximum number of SCs */
+/** @brief Maximum bypass lut table index for T26X */
-#define OSI_SC_LUT_MAX_INDEX	15U
+#define OSI_BYP_LUT_MAX_INDEX_T26X	47U
-#define OSI_SA_LUT_MAX_INDEX	OSI_TABLE_INDEX_MAX
+/** @brief Maximum number of SAs */
+#define OSI_SA_LUT_MAX_INDEX	31U
+/** @brief Maximum number of SAs for T26X */
+#define OSI_SA_LUT_MAX_INDEX_T26X	95U
+
 /** @} */
 
 #ifdef DEBUG_MACSEC
@@ -242,6 +252,10 @@ struct osi_sc_param_outputs {
 	/** Indicates 1 bit VLAN IN CLEAR config
 	 * vlaid values are 0(vlan not in clear) and 1(vlan in clear) */
 	nveu8_t vlan_in_clear;
+	/** Indicates 1 bit Encription config */
+	nveu8_t encrypt;
+	/** Indicates 2 bit confidentiality offset config */
+	nveu8_t conf_offset;
 };
 
 /**

osi/core/common.h

@@ -37,13 +37,6 @@
 #define RETRY_DELAY	1U
 /** @} */
 
-/** MAC version type for EQOS version previous to 5.30 */
-#define MAC_CORE_VER_TYPE_EQOS		0U
-/** MAC version type for EQOS version 5.30 */
-#define MAC_CORE_VER_TYPE_EQOS_5_30	1U
-/** MAC version type for MGBE IP */
-#define MAC_CORE_VER_TYPE_MGBE		2U
-
 /**
  * @addtogroup MGBE PBL settings.
  *
@@ -54,13 +47,24 @@
 #define MGBE_TXQ_SIZE		131072U
 /* Rx Queue size is 192KB */
 #define MGBE_RXQ_SIZE		196608U
-/* MAX PBL value */
+/* uFPGA config Tx Queue size is 64KB */
-#define MGBE_DMA_CHX_MAX_PBL		256U
+#define MGBE_TXQ_SIZE_UFPGA	65536U
-#define MGBE_DMA_CHX_MAX_PBL_VAL	0x200000U
+
+/* PBL values */
+#define MGBE_DMA_CHX_MAX_PBL	32U
+#define MGBE_DMA_CHX_PBL_16	16U
+#define MGBE_DMA_CHX_PBL_8	8U
+#define MGBE_DMA_CHX_PBL_4	4U
+#define MGBE_DMA_CHX_PBL_1	1U
 /* AXI Data width */
 #define MGBE_AXI_DATAWIDTH	128U
 /** @} */
 
+/**
+ * @brief MTL Q size depth helper macro
+ */
+#define Q_SZ_DEPTH(x)		(((x) * 1024U) / (MGBE_AXI_DATAWIDTH / 8U))
+
 /**
  * @brief osi_readl_poll_timeout - Periodically poll an address until
  * a condition is met or a timeout occurs
@@ -254,6 +258,7 @@ static inline void osi_writela(OSI_UNUSED void *priv, nveu32_t val, void *addr)
 /**
  * @brief validate_mac_ver_update_chans - Validates mac version and update chan
  *
+ * @param[in] mac: MAC HW type.
  * @param[in] mac_ver: MAC version read.
  * @param[out] num_max_chans: Maximum channel number.
  * @param[out] l_mac_ver: local mac version.
@@ -269,10 +274,16 @@ static inline void osi_writela(OSI_UNUSED void *priv, nveu32_t val, void *addr)
  * @retval 0 - for not Valid MAC
  * @retval 1 - for Valid MAC
  */
-static inline nve32_t validate_mac_ver_update_chans(nveu32_t mac_ver,
+static inline nve32_t validate_mac_ver_update_chans(nveu32_t mac,
+						    nveu32_t mac_ver,
 						    nveu32_t *num_max_chans,
 						    nveu32_t *l_mac_ver)
 {
+	const nveu32_t max_dma_chan[OSI_MAX_MAC_IP_TYPES] = {
+		OSI_EQOS_MAX_NUM_CHANS,
+		OSI_MGBE_T23X_MAX_NUM_CHANS,
+		OSI_MGBE_MAX_NUM_CHANS
+	};
 	nve32_t ret;
 
 	switch (mac_ver) {
@@ -288,14 +299,20 @@ static inline nve32_t validate_mac_ver_update_chans(nveu32_t mac_ver,
 		*l_mac_ver = MAC_CORE_VER_TYPE_EQOS_5_30;
 		ret = 1;
 		break;
+	case OSI_EQOS_MAC_5_40:
+		*num_max_chans = OSI_EQOS_MAX_NUM_CHANS;
+		*l_mac_ver = MAC_CORE_VER_TYPE_EQOS_5_40;
+		ret = 1;
+		break;
 	case OSI_MGBE_MAC_3_10:
 	//TBD: T264 uFPGA reports mac version 3.2
 	case OSI_MGBE_MAC_3_20:
+	case OSI_MGBE_MAC_4_20:
 #ifndef OSI_STRIPPED_LIB
 	case OSI_MGBE_MAC_4_00:
 #endif /* !OSI_STRIPPED_LIB */
 		//TBD: T264 number of dma channels?
-		*num_max_chans = OSI_MGBE_MAX_NUM_CHANS;
+		*num_max_chans = max_dma_chan[mac];
 		*l_mac_ver = MAC_CORE_VER_TYPE_MGBE;
 		ret = 1;
 		break;
@@ -375,4 +392,46 @@ static inline nve32_t osi_memcmp(const void *dest, const void *src, nve32_t n)
 fail:
 	return ret;
 }
+
+/**
+ * @brief osi_valid_pbl_value - returns the allowed pbl value.
+ * @note
+ * Algorithm:
+ *  - Check the pbl range and return allowed pbl value
+ *
+ * @param[in] pbl: Calculated PBL value
+ *
+ * @note Input parameter should be only nveu32_t type
+ *
+ * @note
+ * API Group:
+ * - Initialization: No
+ * - Run time: Yes
+ * - De-initialization: No
+ *
+ * @retval allowed pbl value
+ */
+static inline nveu32_t osi_valid_pbl_value(nveu32_t pbl_value)
+{
+	nveu32_t allowed_pbl;
+	nveu32_t pbl;
+
+	/* 8xPBL mode is set */
+	pbl = pbl_value / 8U;
+
+	if (pbl >= MGBE_DMA_CHX_MAX_PBL) {
+		allowed_pbl = MGBE_DMA_CHX_MAX_PBL;
+	} else if (pbl >= MGBE_DMA_CHX_PBL_16) {
+		allowed_pbl = MGBE_DMA_CHX_PBL_16;
+	} else if (pbl >= MGBE_DMA_CHX_PBL_8) {
+		allowed_pbl = MGBE_DMA_CHX_PBL_8;
+	} else if (pbl >= MGBE_DMA_CHX_PBL_4) {
+		allowed_pbl = MGBE_DMA_CHX_PBL_4;
+	} else {
+		allowed_pbl = MGBE_DMA_CHX_PBL_1;
+	}
+
+	return allowed_pbl;
+}
+
 #endif

osi/core/core_common.c

@@ -26,6 +26,7 @@
 #include "eqos_core.h"
 #include "xpcs.h"
 #include "macsec.h"
+#include "osi_macsec.h"
 
 nve32_t poll_check(struct osi_core_priv_data *const osi_core, nveu8_t *addr,
 				 nveu32_t bit_check, nveu32_t *value)
@@ -172,6 +173,7 @@ fail:
 	return ret;
 }
 
+#if 0
 static nve32_t xpcs_init_start(struct osi_core_priv_data *const osi_core)
 {
 	nve32_t  ret = 0;
@@ -203,6 +205,7 @@ static nve32_t xpcs_init_start(struct osi_core_priv_data *const osi_core)
 fail:
 	return ret;
 }
+#endif
 
 nve32_t hw_set_speed(struct osi_core_priv_data *const osi_core, const nve32_t speed)
 {
@@ -261,8 +264,39 @@ nve32_t hw_set_speed(struct osi_core_priv_data *const osi_core, const nve32_t sp
 
 	if (ret != -1) {
 		osi_writela(osi_core, value, ((nveu8_t *)osi_core->base + mac_mcr[osi_core->mac]));
-		/* Validate PCS initialization */
+		if (osi_core->mac != OSI_MAC_HW_EQOS) {
-		ret = xpcs_init_start(osi_core);
+			if (speed == OSI_SPEED_25000) {
+				ret = xlgpcs_init(osi_core);
+				if (ret < 0) {
+					goto fail;
+				}
+
+				ret = xlgpcs_start(osi_core);
+				if (ret < 0) {
+					goto fail;
+				}
+			} else {
+				ret = xpcs_init(osi_core);
+				if (ret < 0) {
+					goto fail;
+				}
+
+				ret = xpcs_start(osi_core);
+				if (ret < 0) {
+					goto fail;
+				}
+			}
+			value = osi_readla(osi_core, (nveu8_t *)osi_core->base + MGBE_MAC_IER);
+			/* Enable Link Status interrupt only after lane bring up success */
+			value |= MGBE_IMR_RGSMIIIE;
+			osi_writela(osi_core, value, (nveu8_t *)osi_core->base + MGBE_MAC_IER);
+		} else if (osi_core->mac_ver == MAC_CORE_VER_TYPE_EQOS_5_40) {
+			//TDB: eqos sgmii pcs changes
+//			ret = eqos_xpcs_init(osi_core);
+//			if (ret < 0) {
+//				goto fail;
+//			}
+		}
 	}
 fail:
 	return ret;
@@ -496,7 +530,7 @@ void hw_config_tscr(struct osi_core_priv_data *const osi_core, OSI_UNUSED const
 	const nveu32_t mac_pps[OSI_MAX_MAC_IP_TYPES] = {
 		EQOS_MAC_PPS_CTL,
 		MGBE_MAC_PPS_CTL,
-		MGBE_MAC_TCR
+		MGBE_MAC_PPS_CTL
 	};
 
 	(void)ptp_filter; // unused
@@ -656,11 +690,6 @@ nve32_t hw_config_mac_pkt_filter_reg(struct osi_core_priv_data *const osi_core,
 
 	value = osi_readla(osi_core, ((nveu8_t *)osi_core->base + MAC_PKT_FILTER_REG));
 
-	/*Retain all other values */
-	value &= (MAC_PFR_DAIF | MAC_PFR_DBF  | MAC_PFR_SAIF |
-		  MAC_PFR_SAF  | MAC_PFR_PCF  | MAC_PFR_VTFE |
-		  MAC_PFR_IPFE | MAC_PFR_DNTU | MAC_PFR_RA);
-
 	if ((filter->oper_mode & OSI_OPER_EN_PERFECT) != OSI_DISABLE) {
 		value |= MAC_PFR_HPF;
 	}
@@ -1324,7 +1353,7 @@ static nve32_t hw_config_fpe_pec_enable(struct osi_core_priv_data *const osi_cor
 	osi_writela(osi_core, val, (nveu8_t *)osi_core->base +
 		    MAC_RQC1R[osi_core->mac & 0x1U]);
 
-	if (osi_core->mac == OSI_MAC_HW_MGBE) {
+	if (osi_core->mac != OSI_MAC_HW_EQOS) {
 		val = osi_readla(osi_core, (nveu8_t *)osi_core->base +
 				MGBE_MAC_RQC4R);
 		val &= ~MGBE_MAC_RQC4R_PMCBCQ;
@@ -1402,10 +1431,11 @@ nve32_t hw_config_fpe(struct osi_core_priv_data *const osi_core,
 		goto error;
 	}
 
-	if (osi_core->mac == OSI_MAC_HW_MGBE) {
+	if (osi_core->mac != OSI_MAC_HW_EQOS) {
 #ifdef MACSEC_SUPPORT
 		osi_lock_irq_enabled(&osi_core->macsec_fpe_lock);
-		/* MACSEC and FPE cannot coexist on MGBE refer bug 3484034 */
+		/* MACSEC and FPE cannot coexist on MGBE of T234 refer bug 3484034
+		 * Both EQOS and MGBE of T264 cannot have macsec and fpe enabled simultaneously */
 		if (osi_core->is_macsec_enabled == OSI_ENABLE) {
 			OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID,
 				     "FPE and MACSEC cannot co-exist\n", 0ULL);
@@ -1431,7 +1461,7 @@ nve32_t hw_config_fpe(struct osi_core_priv_data *const osi_core,
 		osi_writela(osi_core, val, (nveu8_t *)osi_core->base +
 			    MAC_FPE_CTS[osi_core->mac & 0x1U]);
 
-		if (osi_core->mac == OSI_MAC_HW_MGBE) {
+		if (osi_core->mac != OSI_MAC_HW_EQOS) {
 #ifdef MACSEC_SUPPORT
 			osi_core->is_fpe_enabled = OSI_DISABLE;
 #endif /*  MACSEC_SUPPORT */
@@ -1445,7 +1475,7 @@ nve32_t hw_config_fpe(struct osi_core_priv_data *const osi_core,
 	}
 done:
 
-	if (osi_core->mac == OSI_MAC_HW_MGBE) {
+	if (osi_core->mac != OSI_MAC_HW_EQOS) {
 #ifdef MACSEC_SUPPORT
 		osi_unlock_irq_enabled(&osi_core->macsec_fpe_lock);
 #endif /*  MACSEC_SUPPORT */
@@ -1701,7 +1731,7 @@ void hw_tsn_init(struct osi_core_priv_data *osi_core)
 	osi_writela(osi_core, val, (nveu8_t *)osi_core->base +
 			MAC_RQC1R[osi_core->mac & 0x1U]);
 
-	if (osi_core->mac == OSI_MAC_HW_MGBE) {
+	if (osi_core->mac != OSI_MAC_HW_EQOS) {
 		val = osi_readla(osi_core, (nveu8_t *)osi_core->base +
 				 MGBE_MAC_RQC4R);
 		val &= ~MGBE_MAC_RQC4R_PMCBCQ;
@@ -1741,6 +1771,12 @@ nve32_t hsi_common_error_inject(struct osi_core_priv_data *osi_core,
 				nveu32_t error_code)
 {
 	nve32_t ret = 0;
+	const nveu32_t rx_isr_set[MAX_MACSEC_IP_TYPES] = {
+				MACSEC_RX_ISR_SET,
+				MACSEC_RX_ISR_SET_T26X};
+	const nveu32_t common_isr_set[MAX_MACSEC_IP_TYPES] = {
+				MACSEC_COMMON_ISR_SET,
+				MACSEC_COMMON_ISR_SET_T26X};
 
 	switch (error_code) {
 	case OSI_INBOUND_BUS_CRC_ERR:
@@ -1756,7 +1792,7 @@ nve32_t hsi_common_error_inject(struct osi_core_priv_data *osi_core,
 	case OSI_MACSEC_RX_CRC_ERR:
 		osi_writela(osi_core, MACSEC_RX_MAC_CRC_ERROR,
 			    (nveu8_t *)osi_core->macsec_base +
-			    MACSEC_RX_ISR_SET);
+			    rx_isr_set[osi_core->macsec]);
 		break;
 	case OSI_MACSEC_TX_CRC_ERR:
 		osi_writela(osi_core, MACSEC_TX_MAC_CRC_ERROR,
@@ -1766,12 +1802,12 @@ nve32_t hsi_common_error_inject(struct osi_core_priv_data *osi_core,
 	case OSI_MACSEC_RX_ICV_ERR:
 		osi_writela(osi_core, MACSEC_RX_ICV_ERROR,
 			    (nveu8_t *)osi_core->macsec_base +
-			    MACSEC_RX_ISR_SET);
+			    rx_isr_set[osi_core->macsec]);
 		break;
 	case OSI_MACSEC_REG_VIOL_ERR:
 		osi_writela(osi_core, MACSEC_SECURE_REG_VIOL,
 			    (nveu8_t *)osi_core->macsec_base +
-			    MACSEC_COMMON_ISR_SET);
+			    common_isr_set[osi_core->macsec]);
 		break;
 	case OSI_PHY_WRITE_VERIFY_ERR:
 		osi_core->hsi.err_code[PHY_WRITE_VERIFY_FAIL_IDX] = OSI_PHY_WRITE_VERIFY_ERR;
@@ -1971,7 +2007,10 @@ static void prepare_l3l4_ctr_reg(const struct osi_core_priv_data *const osi_core
 	/* Enable L4 filters for SOURCE Port No matching */
 	value |= (l3_l4->data.src.port_match << MAC_L3L4_CTR_L4SPM_SHIFT) |
 		 (l3_l4->data.src.port_match_inv << MAC_L3L4_CTR_L4SPIM_SHIFT);
-
+	if (osi_core->mac == OSI_MAC_HW_MGBE_T26X) {
+		/* Enable combined L3 and L4 filters */
+		value |= l3_l4->data.is_l3l4_match_en << MAC_L3L4_CTR_L5TEN_SHIFT;
+	}
 	/* set udp / tcp port matching bit (for l4) */
 	value |= l3_l4->data.is_udp << MAC_L3L4_CTR_L4PEN_SHIFT;
 

osi/core/core_common.h

@@ -110,6 +110,7 @@
 #ifndef OSI_STRIPPED_LIB
 #define MAC_L3L4_CTR_L3DAIM_SHIFT	5
 #define MAC_L3L4_CTR_L4PEN_SHIFT	16
+#define MAC_L3L4_CTR_L5TEN_SHIFT	17
 #define MAC_L3L4_CTR_L4SPM_SHIFT	18
 #define MAC_L3L4_CTR_L4SPIM_SHIFT	19
 #define MAC_L3L4_CTR_L4DPM_SHIFT	20

osi/core/core_local.h

@@ -229,6 +229,12 @@ struct core_ops {
 				    struct osi_core_frp_data *const data);
 	/** Called to update FRP NVE and  */
 	void (*update_frp_nve)(struct osi_core_priv_data *const osi_core, const nveu32_t nve);
+	/** Called to get RCHList index */
+	nve32_t (*get_rchlist_index)(struct osi_core_priv_data *const osi_core,
+				     nveu8_t const *mac_addr);
+	/** Called to free RCHLIST index */
+	void (*free_rchlist_index)(struct osi_core_priv_data *const osi_core,
+				   const nve32_t rch_indx);
 #ifdef HSI_SUPPORT
 	/** Interface function called to initialize HSI */
 	nve32_t (*core_hsi_configure)(struct osi_core_priv_data *const osi_core,
@@ -316,7 +322,7 @@ struct core_l2 {
 struct dynamic_cfg {
 	nveu32_t flags;
 	/** L3_L4 filters */
-	struct osi_l3_l4_filter l3_l4[OSI_MGBE_MAX_L3_L4_FILTER];
+	struct osi_l3_l4_filter l3_l4[OSI_MGBE_MAX_L3_L4_FILTER_T264];
 	/** flow control */
 	nveu32_t flow_ctrl;
 	/** AVB */

osi/core/eqos_core.c

@@ -2072,7 +2072,7 @@ static nve32_t eqos_update_mac_addr_low_high_reg(
 	nveu32_t idx = filter->index;
 	nveu32_t dma_routing_enable = filter->dma_routing;
 	nveu32_t dma_chan = filter->dma_chan;
-	nveu32_t dma_chansel = filter->dma_chansel;
+	nveu64_t dma_chansel = filter->dma_chansel;
 	nveu32_t addr_mask = filter->addr_mask;
 	nveu32_t src_dest = filter->src_dest;
 	nveu32_t value = OSI_DISABLE;
@@ -4022,6 +4022,43 @@ static nve32_t eqos_post_pad_calibrate(
 	return ret;
 }
 
+/**
+ * @brief eqos_free_rchlist_index - Free index.
+ *
+ * Algorithm: This function just free the Receive channel index.
+ *
+ * @param[in] osi_core: OSI core private data structure.
+ * @param[in] rch_idx: Receive channel index.
+ *
+ */
+static void eqos_free_rchlist_index(struct osi_core_priv_data *osi_core,
+				    const nve32_t rch_idx)  {
+	(void) osi_core;
+	(void) rch_idx;
+	OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
+		     "Free RCHLIST not supported by EQOS\n", 0ULL);
+}
+
+/**
+ * @brief eqos_rchlist_get_index - find free index
+ *
+ * Algorithm: This function gets free index for receive channel list.
+ *
+ * @param[in] osi_core: OSI core private data structure.
+ * @param[in] mac_addr: Mac address.
+ *
+ * @retval -1 on failure.
+
+**/
+static nve32_t eqos_get_rchlist_index(struct osi_core_priv_data *osi_core,
+				      nveu8_t const *mac_addr)  {
+	(void) osi_core;
+	(void) mac_addr;
+	OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
+		     "RCHLIST not supported by EQOS\n", 0ULL);
+	return -1;
+}
+
 #ifndef OSI_STRIPPED_LIB
 /**
  * @brief eqos_config_rss - Configure RSS
@@ -4151,6 +4188,8 @@ void eqos_init_core_ops(struct core_ops *ops)
 	ops->config_frp = eqos_config_frp;
 	ops->update_frp_entry = eqos_update_frp_entry;
 	ops->update_frp_nve = eqos_update_frp_nve;
+	ops->get_rchlist_index = eqos_get_rchlist_index;
+	ops->free_rchlist_index = eqos_free_rchlist_index;
 #if defined MACSEC_SUPPORT && !defined OSI_STRIPPED_LIB
 	ops->read_macsec_reg = eqos_read_macsec_reg;
 	ops->write_macsec_reg = eqos_write_macsec_reg;

osi/core/frp.c

@@ -200,7 +200,7 @@ static nve32_t validate_frp_args(struct osi_core_priv_data *const osi_core,
 				 OSI_UNUSED nveu8_t pos,
 				 nveu32_t *req_entries)
 {
-	nveu32_t dma_sel_val[OSI_MAX_MAC_IP_TYPES] = {0xFFU, 0x3FFU, 0x3FFU};
+	nveu64_t dma_sel_val[OSI_MAX_MAC_IP_TYPES] = {0xFFU, 0x3FFU, 0xFFFFFFFFFFFFU};
 	nve32_t ret = 0;
 	(void)pos;
 
@@ -253,7 +253,9 @@ done:
  * @param[in] offset: Actual match data offset position.
  * @param[in] filter_mode: Filter mode from FRP command.
  * @param[in] next_frp_id: FRP ID to link this ID.
- * @param[in] dma_sel: Indicate the DMA Channel Number (1-bit for each).
+ * @param[in] dcht: DMA Channel Selection Type.
+ * @param[in] rchlist_indx: Receive Channel list index.
+ *
  *
  * @retval 0 on success.
  * @retval -1 on failure.
@@ -266,7 +268,9 @@ static nve32_t frp_entry_add(struct osi_core_priv_data *const osi_core,
 			     nveu8_t offset,
 			     nveu8_t filter_mode,
 			     nve32_t next_frp_id,
-			     nveu32_t dma_sel)
+			     nveu32_t dma_sel,
+			     nveu8_t dcht,
+			     nve32_t rchlist_indx)
 {
 	struct osi_core_frp_entry *entry = OSI_NULL;
 	struct osi_core_frp_data *data = OSI_NULL;
@@ -340,6 +344,9 @@ static nve32_t frp_entry_add(struct osi_core_priv_data *const osi_core,
 		/* Fill DCH */
 		data->dma_chsel = dma_sel;
 
+		/* Fill dcht & rchlist_indx */
+		data->rchlist_indx = rchlist_indx;
+		data->dcht = dcht;
 		/* Check for the remain data and update FRP flags */
 		if (md_pos < length) {
 			/* Reset AF, RF and set NIC, OKI */
@@ -456,13 +463,15 @@ frp_hw_write_error:
  * @param[in] osi_core: OSI core private data structure.
  * @param[in] cmd: OSI FRP command structure.
  * @param[in] pos: Pointer to the FRP entry position.
+ * @param[in] rchlist_indx: Index to the rchlist.
  *
  * @retval 0 on success.
  * @retval -1 on failure.
  */
 static nve32_t frp_add_proto(struct osi_core_priv_data *const osi_core,
 			     struct osi_core_frp_cmd *const cmd,
-			     nveu8_t *pos)
+			     nveu8_t *pos,
+			     nve32_t rchlist_indx)
 {
 	nve32_t ret, proto_oki;
 	nveu8_t proto_entry = OSI_DISABLE;
@@ -538,7 +547,8 @@ static nve32_t frp_add_proto(struct osi_core_priv_data *const osi_core,
 		ret = frp_entry_add(osi_core, cmd->frp_id, *pos,
 				    proto_match, proto_lendth,
 				    proto_offset, OSI_FRP_MODE_LINK,
-				    proto_oki, cmd->dma_sel);
+				    proto_oki, cmd->dma_sel, cmd->dcht,
+				    rchlist_indx);
 		if (ret < 0) {
 			OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
 				"Fail add FRP protocol entry\n",
@@ -627,6 +637,7 @@ static nve32_t frp_delete(struct osi_core_priv_data *const osi_core,
 	nveu8_t i = 0U, pos = 0U, count = 0U;
 	nve32_t frp_id = cmd->frp_id;
 	nveu32_t frp_cnt = osi_core->frp_cnt;
+	struct osi_core_frp_entry *entry = OSI_NULL;
 
 	/* Check for FRP entries  */
 	if (frp_cnt == 0U) {
@@ -646,6 +657,11 @@ static nve32_t frp_delete(struct osi_core_priv_data *const osi_core,
 		goto done;
 	}
 
+	/* Free the RCHLIST index */
+	entry = &osi_core->frp_table[frp_id];
+	ops_p->free_rchlist_index(osi_core,
+				 entry->data.rchlist_indx);
+
 	/* Update the frp_table entry */
 	osi_memset(&osi_core->frp_table[pos], 0U,
 		   (sizeof(struct osi_core_frp_entry) * count));
@@ -692,6 +708,8 @@ static nve32_t frp_update(struct osi_core_priv_data *const osi_core,
 	nveu8_t pos = 0U, count = 0U, req = 0U;
 	nveu16_t req_16bit = 0U;
 	nve32_t frp_id = cmd->frp_id;
+	struct osi_core_frp_entry *entry = OSI_NULL;
+	nve32_t rchlist_indx = 0;
 
 	/* Validate given frp_id */
 	if (frp_entry_find(osi_core, frp_id, &pos, &count) < 0) {
@@ -702,6 +720,9 @@ static nve32_t frp_update(struct osi_core_priv_data *const osi_core,
 		goto done;
 	}
 
+	entry = &osi_core->frp_table[frp_id];
+	rchlist_indx = entry->data.rchlist_indx;
+
 	/* Parse match type and update command offset */
 	frp_parse_mtype(cmd);
 
@@ -732,8 +753,8 @@ static nve32_t frp_update(struct osi_core_priv_data *const osi_core,
 		goto done;
 	}
 
-	/* Process and update FRP Command Protocal Entry */
+	/* Process and update FRP Command Protocol Entry */
-	ret = frp_add_proto(osi_core, cmd, &pos);
+	ret = frp_add_proto(osi_core, cmd, &pos, rchlist_indx);
 	if (ret < 0) {
 		OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
 			"Fail to parse match type\n",
@@ -745,7 +766,8 @@ static nve32_t frp_update(struct osi_core_priv_data *const osi_core,
 	ret = frp_entry_add(osi_core, frp_id, pos,
 			    cmd->match, cmd->match_length,
 			    cmd->offset, cmd->filter_mode,
-			    cmd->next_frp_id, cmd->dma_sel);
+			    cmd->next_frp_id, cmd->dma_sel,
+			    cmd->dcht, rchlist_indx);
 	if (ret < 0) {
 		OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
 			"Fail to update FRP entry\n",
@@ -784,6 +806,7 @@ static nve32_t frp_add(struct osi_core_priv_data *const osi_core,
 	nve32_t ret;
 	nveu8_t pos = 0U, count = 0U;
 	nve32_t frp_id = cmd->frp_id;
+	nve32_t rchlist_indx = 0;
 
 	/* Check for MAX FRP entries */
 	if (osi_core->frp_cnt >= OSI_FRP_MAX_ENTRY) {
@@ -807,8 +830,20 @@ static nve32_t frp_add(struct osi_core_priv_data *const osi_core,
 	/* Parse match type and update command offset */
 	frp_parse_mtype(cmd);
 
+	if (cmd->dcht == OSI_ENABLE) {
+		/* Find rchlist Free index */
+		rchlist_indx = ops_p->get_rchlist_index(osi_core, OSI_NULL);
+		if (rchlist_indx < 0) {
+			OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
+				"Fail to get rchlist index\n",
+				OSI_NONE);
+			goto done;
+		}
+		osi_core->rch_index[rchlist_indx/*ret*/].in_use = OSI_ENABLE;
+	}
+
 	/* Process and add FRP Command Protocal Entry */
-	ret = frp_add_proto(osi_core, cmd, (nveu8_t *)&osi_core->frp_cnt);
+	ret = frp_add_proto(osi_core, cmd, (nveu8_t *)&osi_core->frp_cnt, rchlist_indx);
 	if (ret < 0) {
 		OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
 			"Fail to parse match type\n",
@@ -820,7 +855,8 @@ static nve32_t frp_add(struct osi_core_priv_data *const osi_core,
 	ret = frp_entry_add(osi_core, frp_id, (nveu8_t)(osi_core->frp_cnt & 0xFFU),
 			    cmd->match, cmd->match_length,
 			    cmd->offset, cmd->filter_mode,
-			    cmd->next_frp_id, cmd->dma_sel);
+			    cmd->next_frp_id, cmd->dma_sel,
+			    cmd->dcht, rchlist_indx);
 	if (ret < 0) {
 		OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
 			"Fail to add FRP entry\n",

osi/core/macsec.h

@@ -46,55 +46,89 @@
 #define MACSEC_TX_IMR				0x4008
 #define MACSEC_TX_ISR				0x400C
 #define MACSEC_RX_IMR				0x4048
+#define MACSEC_RX_IMR_T26X			0x4050
 #define MACSEC_RX_ISR				0x404C
+#define MACSEC_RX_ISR_T26X			0x4054
 #define MACSEC_TX_SC_PN_THRESHOLD_STATUS0_0	0x4018
-#define MACSEC_TX_SC_PN_THRESHOLD_STATUS1_0	0x401C
+#define MACSEC_TX_SC_PN_THRESHOLD_STATUS0_0_T26X	0x4018
 #define MACSEC_TX_SC_PN_EXHAUSTED_STATUS0_0	0x4024
-#define MACSEC_TX_SC_PN_EXHAUSTED_STATUS1_0	0x4028
+#define MACSEC_TX_SC_PN_EXHAUSTED_STATUS0_0_T26X	0x4030
 #define MACSEC_TX_SC_ERROR_INTERRUPT_STATUS_0	0x402C
+#define MACSEC_TX_SC_ERROR_INTERRUPT_STATUS0_0_T26X	0x4048
 #define MACSEC_RX_SC_PN_EXHAUSTED_STATUS0_0	0x405C
-#define MACSEC_RX_SC_PN_EXHAUSTED_STATUS1_0	0x4060
+#define MACSEC_RX_SC_PN_EXHAUSTED_STATUS0_0_T26X	0x4064
 #define MACSEC_RX_SC_REPLAY_ERROR_STATUS0_0	0x4090
-#define MACSEC_RX_SC_REPLAY_ERROR_STATUS1_0	0x4094
+#define MACSEC_RX_SC_REPLAY_ERROR_STATUS0_0_T26X	0x4084
 #define MACSEC_STATS_CONTROL_0			0x900C
 #define MACSEC_TX_PKTS_UNTG_LO_0		0x9010
 #define MACSEC_TX_OCTETS_PRTCTD_LO_0		0x9018
+#define MACSEC_TX_OCTETS_ENCRYPTED_LO_0		0x91A8
 #define MACSEC_TX_PKTS_TOO_LONG_LO_0		0x9020
 #define MACSEC_TX_PKTS_PROTECTED_SCx_LO_0(x)	((0x9028UL) + ((x) * 8UL))
+#define MACSEC_TX_PKTS_ENCRYPTED_SCx_LO_0(x)	((0x91B0UL) + ((x) * 8UL))
 #define MACSEC_RX_PKTS_NOTG_LO_0		0x90B0
+#define MACSEC_RX_PKTS_NOTG_LO_0_T26X		0x9338
 #define MACSEC_RX_PKTS_UNTG_LO_0		0x90A8
+#define MACSEC_RX_PKTS_UNTG_LO_0_T26X		0x9330
 #define MACSEC_RX_PKTS_BADTAG_LO_0		0x90B8
+#define MACSEC_RX_PKTS_BADTAG_LO_0_T26X		0x9040
 #define MACSEC_RX_PKTS_NOSA_LO_0		0x90C0
+#define MACSEC_RX_PKTS_NOSA_LO_0_T26X		0x9348
 #define MACSEC_RX_PKTS_NOSAERROR_LO_0		0x90C8
+#define MACSEC_RX_PKTS_NOSAERROR_LO_0_T26X	0x9350
 #define MACSEC_RX_PKTS_OVRRUN_LO_0		0x90D0
+#define MACSEC_RX_PKTS_OVRRUN_LO_0_T26X		0x9358
 #define MACSEC_RX_OCTETS_VLDTD_LO_0		0x90D8
-#define MACSEC_RX_PKTS_LATE_SCx_LO_0(x) 	((0x90E0UL) + ((x) * 8UL))
+#define MACSEC_RX_OCTETS_DECRYPD_LO_0		0x9368
-#define MACSEC_RX_PKTS_NOTVALID_SCx_LO_0(x)	((0x9160UL) + ((x) * 8UL))
+#define MACSEC_RX_OCTETS_VLDTD_LO_0_T26X	0x9360
-#define MACSEC_RX_PKTS_OK_SCx_LO_0(x)		((0x91E0UL) + ((x) * 8UL))
+#define MACSEC_RX_PKTS_LATE_SCx_LO_0(x) 	((0x90E0U) + ((x) * 8U))
+#define MACSEC_RX_PKTS_LATE_SCx_LO_0_T26X(x)	((0x9370U) + ((x) * 8U))
+#define MACSEC_RX_PKTS_NOTVALID_SCx_LO_0(x)	((0x9160U) + ((x) * 8U))
+#define MACSEC_RX_PKTS_NOTVALID_SCx_LO_0_T26X(x)	((0x94F0U) + ((x) * 8U))
+#define MACSEC_RX_PKTS_OK_SCx_LO_0(x)		((0x91E0U) + ((x) * 8U))
+#define MACSEC_RX_PKTS_OK_SCx_LO_0_T26X(x)		((0x9670U) + ((x) * 8U))
 
 #define MACSEC_CONTROL0 		0xD000
 #define MACSEC_LUT_CONFIG		0xD004
 #define MACSEC_LUT_DATA(x)		((0xD008U) + ((x) * 4U))
 #define MACSEC_TX_BYP_LUT_VALID 	0xD024
+#define MACSEC_TX_BYP_LUT_VALID0_T26X 	0xD024U
+#define MACSEC_TX_BYP_LUT_VALID1_T26X 	0xD028U
 #define MACSEC_TX_SCI_LUT_VALID 	0xD028
+#define MACSEC_TX_SCI_LUT_VALID0_T26X 	0xD02CU
+#define MACSEC_TX_SCI_LUT_VALID1_T26X 	0xD030U
 #define MACSEC_RX_BYP_LUT_VALID 	0xD02C
+#define MACSEC_RX_BYP_LUT_VALID0_T26X 	0xD034U
+#define MACSEC_RX_BYP_LUT_VALID1_T26X 	0xD038U
 #define MACSEC_RX_SCI_LUT_VALID 	0xD030
+#define MACSEC_RX_SCI_LUT_VALID0_T26X 	0xD03CU
+#define MACSEC_RX_SCI_LUT_VALID1_T26X 	0xD040U
 #define MACSEC_COMMON_IMR		0xD054
+#define MACSEC_COMMON_IMR_T26X		0xD064
 #define MACSEC_COMMON_ISR		0xD058
+#define MACSEC_COMMON_ISR_T26X		0xD068
 #define MACSEC_TX_SC_KEY_INVALID_STS0_0	0xD064
-#define MACSEC_TX_SC_KEY_INVALID_STS1_0	0xD068
+#define MACSEC_TX_SC_KEY_INVALID_STS0_0_T26X	0xD074
 #define MACSEC_RX_SC_KEY_INVALID_STS0_0	0xD080
-#define MACSEC_RX_SC_KEY_INVALID_STS1_0	0xD084
+#define MACSEC_RX_SC_KEY_INVALID_STS0_0_T26X	0xD08C
-
 #define MACSEC_TX_DEBUG_STATUS_0		0xD0C4
+#define MACSEC_TX_DEBUG_STATUS_0_T26X		0xD0D0
 #define MACSEC_TX_DEBUG_TRIGGER_EN_0		0xD09C
+#define MACSEC_TX_DEBUG_TRIGGER_EN_0_T26X	0xD0A8
 #define MACSEC_RX_DEBUG_STATUS_0		0xD0F8
+#define MACSEC_RX_DEBUG_STATUS_0_T26X		0xD104
 #define MACSEC_RX_DEBUG_TRIGGER_EN_0		0xD0E0
+#define MACSEC_RX_DEBUG_TRIGGER_EN_0_T26X	0xD0EC
+
 #ifdef DEBUG_MACSEC
 #define MACSEC_TX_DEBUG_CONTROL_0	0xD098
+#define MACSEC_TX_DEBUG_CONTROL_0_T26X	0xD0A4
 #define MACSEC_DEBUG_BUF_CONFIG_0	0xD0C8
+#define MACSEC_DEBUG_BUF_CONFIG_0_T26X	0xD0D4
 #define MACSEC_DEBUG_BUF_DATA_0(x)	((0xD0CCU) + ((x) * 4U))
+#define MACSEC_DEBUG_BUF_DATA_0_T26X(x)	((0xD0D8U) + ((x) * 4U))
 #define MACSEC_RX_DEBUG_CONTROL_0	0xD0DC
+#define MACSEC_RX_DEBUG_CONTROL_0_T26X	0xD0E8
 #endif /* DEBUG_MACSEC */
 
 #define MACSEC_CONTROL1			0xE000
@@ -115,7 +149,8 @@
 #define MACSEC_KT_CONFIG_UPDATE 	OSI_BIT(31)
 #define MACSEC_KT_CONFIG_CTLR_SEL	OSI_BIT(25)
 #define MACSEC_KT_CONFIG_RW		OSI_BIT(24)
-#define MACSEC_KT_CONFIG_INDEX_MASK	(OSI_BIT(4) | OSI_BIT(3) | OSI_BIT(2) |\
+#define MACSEC_KT_CONFIG_INDEX_MASK	(OSI_BIT(6) | OSI_BIT(5) |\
+					 OSI_BIT(4) | OSI_BIT(3) | OSI_BIT(2) |\
 					 OSI_BIT(1) | OSI_BIT(0))
 #define MACSEC_KT_ENTRY_VALID		OSI_BIT(0)
 /** @} */
@@ -144,7 +179,8 @@
 #define MACSEC_LUT_CONFIG_LUT_SEL_MASK	(OSI_BIT(18) | OSI_BIT(17) |\
 					 OSI_BIT(16))
 #define MACSEC_LUT_CONFIG_LUT_SEL_SHIFT	16
-#define MACSEC_LUT_CONFIG_INDEX_MASK	(OSI_BIT(4) | OSI_BIT(3) | OSI_BIT(2) |\
+#define MACSEC_LUT_CONFIG_INDEX_MASK	(OSI_BIT(6) | OSI_BIT(5) |\
+					 OSI_BIT(4) | OSI_BIT(3) | OSI_BIT(2) |\
 					 OSI_BIT(1) | OSI_BIT(0))
 /** @} */
 /**
@@ -464,8 +500,12 @@
 #define MACSEC_LUT_AN3_VALID			OSI_BIT(16)
 /* DVLAN packet in LUT_DATA[6] register */
 #define MACSEC_TX_SCI_LUT_DVLAN_PKT		OSI_BIT(21)
+#define MACSEC_TX_SCI_LUT_DVLAN_PKT_T26X	OSI_BIT(23)
+
 /* DVLAN outer/inner tag select in LUT_DATA[6] register */
 #define MACSEC_TX_SCI_LUT_DVLAN_OUTER_INNER_TAG_SEL		OSI_BIT(22)
+#define MACSEC_TX_SCI_LUT_DVLAN_OUTER_INNER_TAG_SEL_T26X	OSI_BIT(24)
+
 /* SA State LUT entry valid in LUT_DATA[0] register */
 #define MACSEC_SA_STATE_LUT_ENTRY_VALID 	OSI_BIT(0)
 
@@ -486,10 +526,12 @@
 #ifdef HSI_SUPPORT
 /* Set RX ISR set interrupt status bit */
 #define MACSEC_RX_ISR_SET		0x4050U
+#define MACSEC_RX_ISR_SET_T26X		0x4058U
 /* Set TX ISR set interrupt status bit */
 #define MACSEC_TX_ISR_SET		0x4010U
 /* Set Common ISR set interrupt status bit */
-#define MACSEC_COMMON_ISR_SET		0xd05cU
+#define MACSEC_COMMON_ISR_SET		0xD05cU
+#define MACSEC_COMMON_ISR_SET_T26X	0xD06cU
 #endif
 
 #endif /* INCLUDED_MACSEC_H */

osi/core/mgbe_core.h

@@ -25,7 +25,6 @@
 #define INCLUDED_MGBE_CORE_H_
 
 #ifndef OSI_STRIPPED_LIB
-#define MGBE_MAC_PFR				0x0008
 #define MGBE_MAC_RX_FLW_CTRL			0x0090
 #define MGBE_MAC_RQC2R				0x00A8
 #define MGBE_MAC_QX_TX_FLW_CTRL(x)		((0x0004U * (x)) + 0x0070U)
@@ -45,6 +44,8 @@
 #define MGBE_WRAP_AXI_ASID0_CTRL		0x8400
 #define MGBE_WRAP_AXI_ASID1_CTRL		0x8404
 #define MGBE_WRAP_AXI_ASID2_CTRL		0x8408
+#define MGBE_MAC_PFR_DHLFRS			OSI_BIT(12)
+#define MGBE_MAC_PFR_DHLFRS_MASK		(OSI_BIT(12) | OSI_BIT(11))
 #define MGBE_MAC_PFR_VTFE			OSI_BIT(16)
 #define MGBE_MAC_PFR_IPFE			OSI_BIT(20)
 #define MGBE_MAC_PFR_IPFE_SHIFT			20
@@ -58,6 +59,10 @@
 #define MGBE1_SID				((nveu32_t)0x49U)
 #define MGBE2_SID				((nveu32_t)0x4AU)
 #define MGBE3_SID				((nveu32_t)0x4BU)
+#define MGBE0_SID_T264				((nveu32_t)0x0U)
+#define MGBE1_SID_T264				((nveu32_t)0x0U)
+#define MGBE2_SID_T264				((nveu32_t)0x0U)
+#define MGBE3_SID_T264				((nveu32_t)0x0U)
 #define MGBE_MAC_PAUSE_TIME			0xFFFF0000U
 #define MGBE_MAC_PAUSE_TIME_MASK		0xFFFF0000U
 #define MGBE_MAC_VLAN_TR_VTHM			OSI_BIT(25)
@@ -80,9 +85,21 @@
 #define MGBE_MAC_RQC1R_PTPQ_SHIFT		24U
 #define MGBE_MAC_RQC1R_PTPQ			(OSI_BIT(27) | OSI_BIT(26) | \
 						 OSI_BIT(25) | OSI_BIT(24))
+#define MGBE_PKTID_MASK				(OSI_BIT(9) | OSI_BIT(8) | \
+						 OSI_BIT(7) | OSI_BIT(6) | \
+						 OSI_BIT(5) | OSI_BIT(4) | \
+						 OSI_BIT(3) | OSI_BIT(2) | \
+						 OSI_BIT(1) | OSI_BIT(0))
+/* T264 VDMA ID bits */
+#define MGBE_VDMAID_MASK			(OSI_BIT(23) | OSI_BIT(22) | \
+						 OSI_BIT(21) | OSI_BIT(20) | \
+						 OSI_BIT(19) | OSI_BIT(18) | \
+						 OSI_BIT(17) | OSI_BIT(16))
 #define MGBE_MAC_RMCR_LM			OSI_BIT(10)
 #define MGBE_MAC_RMCR_ARPEN			OSI_BIT(31)
 #define MGBE_MAC_QX_TX_FLW_CTRL_TFE		OSI_BIT(1)
+#define MGBE_MAC_TMCR_IFP			OSI_BIT(11)
+#define MGBE_MAC_TMCR_IPG			OSI_BIT(8) | OSI_BIT(9)
 #define MGBE_MAC_RQC1R_TPQC0			OSI_BIT(21)
 #define MGBE_MAC_RQC1R_OMCBCQ			OSI_BIT(20)
 #define MGBE_MAC_RSS_CTRL_RSSE			OSI_BIT(0)
@@ -150,11 +167,26 @@
 
 #endif /* !OSI_STRIPPED_LIB */
 
+#define MGBE_PKTID_MASK				(OSI_BIT(9) | OSI_BIT(8) | \
+						 OSI_BIT(7) | OSI_BIT(6) | \
+						 OSI_BIT(5) | OSI_BIT(4) | \
+						 OSI_BIT(3) | OSI_BIT(2) | \
+						 OSI_BIT(1) | OSI_BIT(0))
+/* T264 VDMA ID bits */
+#define MGBE_VDMAID_MASK			(OSI_BIT(23) | OSI_BIT(22) | \
+						 OSI_BIT(21) | OSI_BIT(20) | \
+						 OSI_BIT(19) | OSI_BIT(18) | \
+						 OSI_BIT(17) | OSI_BIT(16))
+
+#define MGBE_MAC_PFR_DHLFRS			OSI_BIT(12)
+#define MGBE_MAC_PFR_DHLFRS_MASK		(OSI_BIT(12) | OSI_BIT(11))
+
 #define MGBE_CORE_MAC_STSR			0x0D08
 #define MGBE_CORE_MAC_STNSR			0x0D0C
 #define MGBE_CORE_MAC_STNSR_TSSS_MASK		0x7FFFFFFFU
 #define MGBE_MAC_TMCR_IPG_MASK			0x700U
 #define MGBE_MAC_TMCR_IFP			OSI_BIT(11)
+#define MGBE_MAC_TMCR_IPG			OSI_BIT(8) | OSI_BIT(9)
 #define MGBE_MAC_RX_TX_STS			0x00B8
 #define MGBE_MTL_EST_CONTROL			0x1050
 #define MGBE_MTL_EST_OVERHEAD			0x1054
@@ -268,6 +300,10 @@
 						 OSI_BIT(5) | OSI_BIT(4) | \
 						 OSI_BIT(3) | OSI_BIT(2) | \
 						 OSI_BIT(1) | OSI_BIT(0))
+
+#define MGBE_MTL_RCHlist_READ_UDELAY		1U
+#define MGBE_MTL_RCHlist_READ_RETRY		1000U
+
 /* FRP Interrupt Control and Status register */
 #define MGBE_MTL_RXP_INTR_CS_PDRFIE		OSI_BIT(19)
 #define MGBE_MTL_RXP_INTR_CS_FOOVIE		OSI_BIT(18)
@@ -296,6 +332,7 @@
 						 OSI_BIT(11) | OSI_BIT(10) | \
 						 OSI_BIT(9) | OSI_BIT(8))
 #define MGBE_MTL_FRP_IE2_FO_SHIFT		8U
+#define MGBE_MTL_FRP_IE2_DCHT			OSI_BIT(7)
 #define MGBE_MTL_FRP_IE2_NC			OSI_BIT(3)
 #define MGBE_MTL_FRP_IE2_IM			OSI_BIT(2)
 #define MGBE_MTL_FRP_IE2_RF			OSI_BIT(1)
@@ -303,7 +340,10 @@
 #define MGBE_MTL_FRP_IE3_DCH_MASK		0xFFFFU
 /* Indirect register defines */
 #define MGBE_MTL_RXP_IND_CS_BUSY		OSI_BIT(31)
+#define MGBE_MTL_RXP_IND_RCH_ACCSEL		OSI_BIT(25)
 #define MGBE_MTL_RXP_IND_CS_ACCSEL		OSI_BIT(24)
+#define MGBE_MTL_RXP_IND_CS_CRWEN		OSI_BIT(18)
+#define MGBE_MTL_RXP_IND_CS_CRWSEL		OSI_BIT(17)
 #define MGBE_MTL_RXP_IND_CS_WRRDN		OSI_BIT(16)
 #define MGBE_MTL_RXP_IND_CS_ADDR		(OSI_BIT(9) | OSI_BIT(8) | \
 						 OSI_BIT(7) | OSI_BIT(6) | \
@@ -346,6 +386,7 @@
 #define MGBE_MMC_TX_INTR_EN		0x0810
 #define MGBE_MMC_RX_INTR_EN		0x080C
 #define MGBE_MMC_CNTRL			0x0800
+#define MGBE_MMC_IPC_RX_INT_MASK	0x0A5C
 #define MGBE_MAC_L3L4_ADDR_CTR		0x0C00
 #define MGBE_MAC_L3L4_DATA		0x0C04
 #define MGBE_MAC_TCR			0x0D00
@@ -367,6 +408,7 @@
  * @{
  */
 #define MGBE_WRAP_COMMON_INTR_ENABLE		0x8704
+#define MGBE_T26X_WRAP_COMMON_INTR_ENABLE	0x880C
 
 #ifdef HSI_SUPPORT
 #define MGBE_REGISTER_PARITY_ERR	OSI_BIT(5)
@@ -383,6 +425,7 @@
 #endif
 #define MGBE_MAC_SBD_INTR		OSI_BIT(2)
 #define MGBE_WRAP_COMMON_INTR_STATUS		0x8708
+#define MGBE_T26X_WRAP_COMMON_INTR_STATUS	0x8810
 #define MGBE_VIRT_INTR_APB_CHX_CNTRL(x)	(0x8200U + ((x) * 4U))
 #define MGBE_VIRTUAL_APB_ERR_CTRL	0x8300
 /** @} */
@@ -396,15 +439,22 @@
  * @{
  */
 #define MGBE_MAC_XDCS_DMA_MAX		0x3FFU
+#define MGBE_MAC_XDCS_DMA_MAX_T26X	0xFFFFFFFFFFFFU
+#define MGBE_MAC_XDCST_DMA_MAX		OSI_BIT(16)
 #define MGBE_MAC_INDIR_AC_OB_WAIT	10U
 #define MGBE_MAC_INDIR_AC_OB_RETRY	10U
 
+#define MGBE_MAC_INDIR_AC_MSEL_T26X	(OSI_BIT(26) | OSI_BIT(27) | \
+					 OSI_BIT(28) | OSI_BIT(29))
 #define MGBE_MAC_DCHSEL			0U
+#define MGBE_MAC_DPCSEL			0x3U
+#define MGBE_MAC_DPCSEL_DDS		OSI_BIT(1)
 
 /* MGBE_MAC_INDIR_AC register defines */
 #define MGBE_MAC_INDIR_AC_MSEL		(OSI_BIT(19) | OSI_BIT(18) | \
 					 OSI_BIT(17) | OSI_BIT(16))
 #define MGBE_MAC_INDIR_AC_MSEL_SHIFT	16U
+#define MGBE_MAC_INDIR_AC_MSEL_SHIFT_T264	26U
 #define MGBE_MAC_INDIR_AC_AOFF		(OSI_BIT(15) | OSI_BIT(14) | \
 					 OSI_BIT(13) | OSI_BIT(12) | \
 					 OSI_BIT(11) | OSI_BIT(10) | \
@@ -514,6 +564,7 @@
 #define MGBE_MMC_CNTRL_RSTONRD			OSI_BIT(2)
 #define MGBE_MMC_CNTRL_CNTMCT			(OSI_BIT(4) | OSI_BIT(5))
 #define MGBE_MMC_CNTRL_CNTPRST			OSI_BIT(7)
+#define MGBE_MMC_IPC_RX_INT_MASK_VALUE		0x3FFF3FFFU
 #define MGBE_MAC_RQC1R_MCBCQEN			OSI_BIT(15)
 #define MGBE_MAC_RQC1R_MCBCQ			(OSI_BIT(11) | OSI_BIT(10) | \
 						 OSI_BIT(9) | OSI_BIT(8))
@@ -539,6 +590,9 @@
 						 OSI_BIT(19) | OSI_BIT(18) | \
 						 OSI_BIT(17) | OSI_BIT(16))
 #define MGBE_MAC_ADDRH_DCS_SHIFT		16
+#define MGBE_MAC_L3L4_ADDR_CTR_IDDR_FNUM_T264	(OSI_BIT(12) | OSI_BIT(13) | \
+						 OSI_BIT(14) | OSI_BIT(15) | \
+						 OSI_BIT(16) | OSI_BIT(17))
 #define MGBE_MAC_L3L4_ADDR_CTR_IDDR_FNUM	(OSI_BIT(12) | OSI_BIT(13) | \
 						 OSI_BIT(14) | OSI_BIT(15))
 #define MGBE_MAC_L3L4_ADDR_CTR_IDDR_FNUM_SHIFT	12
@@ -572,12 +626,12 @@
 #define MGBE_MAC_RMCR_RE			OSI_BIT(0)
 #define MGBE_MTL_TXQ_SIZE_SHIFT			16U
 #define MGBE_MTL_RXQ_SIZE_SHIFT			16U
+#define MGBE_MTL_Q_SIZE_MASK			(OSI_BIT(21) | OSI_BIT(20) | OSI_BIT(19) | \
+						OSI_BIT(18) | OSI_BIT(17) | OSI_BIT(16))
 #define MGBE_RXQ_TO_DMA_CHAN_MAP0		0x03020100U
 #define MGBE_RXQ_TO_DMA_CHAN_MAP1		0x07060504U
 #define MGBE_RXQ_TO_DMA_CHAN_MAP2		0x0B0A0908U
 #define MGBE_RXQ_TO_DMA_MAP_DDMACH		0x80808080U
-#define MGBE_MTL_TXQ_SIZE_SHIFT			16U
-#define MGBE_MTL_RXQ_SIZE_SHIFT			16U
 #define MGBE_MAC_RMCR_GPSL_MSK			0x3FFF0000U
 #define MGBE_MAC_TCR_TSUPDT			OSI_BIT(3)
 #define MGBE_MAC_STNSUR_ADDSUB_SHIFT		31U
@@ -586,6 +640,7 @@
 #define MGBE_MTL_RXQ_OP_MODE_RFA_MASK		0x0000007EU
 #define MGBE_MTL_RXQ_OP_MODE_RFD_SHIFT		17U
 #define MGBE_MTL_RXQ_OP_MODE_RFD_MASK		0x007E0000U
+#define MGBE_DMA_MODE_DSCB			OSI_BIT(16)
 #if defined(MACSEC_SUPPORT)
 /**
  * MACSEC Recommended value
@@ -623,7 +678,8 @@
 #define MGBE_MAC_TSS_TXTSC			OSI_BIT(15)
 /* MGBE DMA IND CTRL register field masks */
 #define MGBE_DMA_INDIR_CTRL_MSEL_MASK		(OSI_BIT(24) | OSI_BIT(25) | \
-						OSI_BIT(26) | OSI_BIT(27))
+						OSI_BIT(26) | OSI_BIT(27) | \
+						OSI_BIT(28))
 #define MGBE_DMA_INDIR_CTRL_MSEL_SHIFT		24
 #define MGBE_DMA_INDIR_CTRL_AOFF_MASK		(OSI_BIT(8) | OSI_BIT(9) | \
 						OSI_BIT(10) | OSI_BIT(11) | \
@@ -640,23 +696,21 @@
 #define MGBE_PDMA_CHX_TXRX_EXTCFG_P2TCMP_MASK	(OSI_BIT(16) | \
 						OSI_BIT(17) | OSI_BIT(18))
 #define MGBE_PDMA_CHX_TXRX_EXTCFG_PBLX8		OSI_BIT(19)
-#define MGBE_PDMA_CHX_TXRX_EXTCFG_PBL_MASK	(OSI_BIT(24) | OSI_BIT(25) | \
+#define MGBE_PDMA_CHX_EXTCFG_PBL_SHIFT		24U
-						OSI_BIT(26) | OSI_BIT(27) | \
+
-						OSI_BIT(28) | OSI_BIT(29))
+#define MGBE_PDMA_CHX_RX_EXTCFG_RXPEN		OSI_BIT(31)
-#define MGBE_PDMA_CHX_TXRX_EXTCFG_PBL_SHIFT	24
-#define MGBE_PDMA_CHX_EXTCFG_MAX_PBL		256U
-#define MGBE_PDMA_CHX_EXTCFG_MAX_PBL_VAL	0x20000000U
 
 /* MGBE PDMA_CH(#i)_Tx/RxDescCtrl register field masks */
 #define MGBE_VDMA_CHX_TX_DESC_CTRL		4U
 #define MGBE_VDMA_CHX_RX_DESC_CTRL		5U
-#define MGBE_XDMA_CHX_TXRX_DESC_CTRL_DCSZ	3U
+#define MGBE_VDMA_CHX_TXRX_DESC_CTRL_DCSZ	5U
-#define MGBE_XDMA_CHX_TXRX_DESC_CTRL_DCSZ_MASK	(OSI_BIT(0) | OSI_BIT(1) | \
+#define MGBE_VDMA_CHX_TXRX_DESC_CTRL_DCSZ_UFPGA	3U
+#define MGBE_VDMA_CHX_TXRX_DESC_CTRL_DCSZ_MASK	(OSI_BIT(0) | OSI_BIT(1) | \
 						OSI_BIT(2))
-#define MGBE_XDMA_CHX_TXRX_DESC_CTRL_DPS	4U
+#define MGBE_VDMA_CHX_TXRX_DESC_CTRL_DPS	3U
-#define MGBE_XDMA_CHX_TXRX_DESC_CTRL_DPS_MASK	(OSI_BIT(3)  | OSI_BIT(4) | \
+#define MGBE_VDMA_CHX_TXRX_DESC_CTRL_DPS_MASK	(OSI_BIT(3)  | OSI_BIT(4) | \
 						OSI_BIT(5))
-#define MGBE_XDMA_CHX_TXRX_DESC_CTRL_DPS_SHIFT	3
+#define MGBE_VDMA_CHX_TXRX_DESC_CTRL_DPS_SHIFT	3
 /** @} */
 
 #ifndef OSI_STRIPPED_LIB
@@ -785,7 +839,9 @@
 #endif /* !OSI_STRIPPED_LIB */
 
 /* TXQ Size 128KB is divided equally across 10 MTL Queues*/
-#define TX_FIFO_SZ	(((((128U * 1024U)/OSI_MGBE_MAX_NUM_QUEUES)) / 256U) - 1U)
+#define TX_FIFO_SZ	(((((MGBE_TXQ_SIZE)/OSI_MGBE_MAX_NUM_QUEUES)) / 256U) - 1U)
+#define TX_FIFO_SZ_UFPGA	(((((MGBE_TXQ_SIZE_UFPGA)/OSI_MGBE_MAX_NUM_QUEUES)) / 256U) - 1U)
+
 
 /**
  * @addtogroup MGBE-MAC-HWFR MGBE MAC HW feature registers
@@ -854,7 +910,9 @@
 #define MGBE_MAC_HFR0_RXCOESEL_SHIFT	16U
 
 #define MGBE_MAC_HFR0_ADDMACADRSEL_MASK	0x1FU
+#define MGBE_T26X_MAC_HFR0_ADDMACADRSEL_MASK	0x3FU
 #define MGBE_MAC_HFR0_ADDMACADRSEL_SHIFT	18U
+#define MGBE_T26X_MAC_HFR0_ADDMACADRSEL_SHIFT	17U
 
 #define MGBE_MAC_HFR0_PHYSEL_MASK	0x3U
 #define MGBE_MAC_HFR0_PHYSEL_SHIFT	23U

osi/core/osi_hal.c

@@ -522,7 +522,7 @@ static nve32_t osi_get_mac_version(struct osi_core_priv_data *const osi_core, nv
 	*mac_ver = osi_readla(osi_core, ((nveu8_t *)osi_core->base + (nve32_t)MAC_VERSION)) &
 			      MAC_VERSION_SNVER_MASK;
 
-	if (validate_mac_ver_update_chans(*mac_ver, &l_core->num_max_chans,
+	if (validate_mac_ver_update_chans(osi_core->mac, *mac_ver, &l_core->num_max_chans,
 					  &l_core->l_mac_ver) == 0) {
 		OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID,
 			     "Invalid MAC version\n", (nveu64_t)*mac_ver)
@@ -885,15 +885,11 @@ static nve32_t l3l4_find_match(const struct core_local *const l_core,
 static nve32_t configure_l3l4_filter_valid_params(const struct osi_core_priv_data *const osi_core,
 						  const struct osi_l3_l4_filter *const l3_l4)
 {
-	const nveu32_t max_dma_chan[OSI_MAX_MAC_IP_TYPES] = {
+	struct core_local *l_core = (struct core_local *)(void *)osi_core;
-		OSI_EQOS_MAX_NUM_CHANS,
-		OSI_MGBE_MAX_NUM_CHANS,
-		OSI_MGBE_MAX_NUM_CHANS
-	};
 	nve32_t ret = -1;
 
 	/* validate dma channel */
-	if (l3_l4->dma_chan > max_dma_chan[osi_core->mac]) {
+	if (l3_l4->dma_chan > l_core->num_max_chans) {
 		OSI_CORE_ERR((osi_core->osd), (OSI_LOG_ARG_OUTOFBOUND),
 			("L3L4: Wrong DMA channel: "), (l3_l4->dma_chan));
 		goto exit_func;
@@ -973,6 +969,7 @@ static nve32_t configure_l3l4_filter_helper(struct osi_core_priv_data *const osi
 {
 	struct osi_l3_l4_filter *cfg_l3_l4;
 	struct core_local *const l_core = (struct core_local *)(void *)osi_core;
+	const nveu32_t filter_mask[OSI_MAX_MAC_IP_TYPES] = { 0x1F, 0x1F, 0x3F };
 	nve32_t ret;
 
 	ret = l_core->ops_p->config_l3l4_filters(osi_core, filter_no, l3_l4);
@@ -994,7 +991,8 @@ static nve32_t configure_l3l4_filter_helper(struct osi_core_priv_data *const osi
 
 #if !defined(L3L4_WILDCARD_FILTER)
 		/* update filter mask bit */
-		osi_core->l3l4_filter_bitmask |= ((nveu32_t)1U << (filter_no & 0x1FU));
+		osi_core->l3l4_filter_bitmask |= ((nveu64_t)1U <<
+				(filter_no & filter_mask[osi_core->mac]));
 #endif /* !L3L4_WILDCARD_FILTER */
 	} else {
 		/* Clear the filter data.
@@ -1007,7 +1005,8 @@ static nve32_t configure_l3l4_filter_helper(struct osi_core_priv_data *const osi
 
 #if !defined(L3L4_WILDCARD_FILTER)
 		/* update filter mask bit */
-		osi_core->l3l4_filter_bitmask &= ~((nveu32_t)1U << (filter_no & 0x1FU));
+		osi_core->l3l4_filter_bitmask &= ~((nveu64_t)1U <<
+				(filter_no & filter_mask[osi_core->mac]));
 #endif /* !L3L4_WILDCARD_FILTER */
 	}
 
@@ -1120,7 +1119,7 @@ static nve32_t configure_l3l4_filter(struct osi_core_priv_data *const osi_core,
 	const nveu32_t max_filter_no[OSI_MAX_MAC_IP_TYPES] = {
 		EQOS_MAX_L3_L4_FILTER - 1U,
 		OSI_MGBE_MAX_L3_L4_FILTER - 1U,
-		OSI_MGBE_MAX_L3_L4_FILTER - 1U,
+		OSI_MGBE_MAX_L3_L4_FILTER_T264 - 1U,
 	};
 	nve32_t ret = -1;
 
@@ -1748,12 +1747,21 @@ static inline void free_tx_ts(struct osi_core_priv_data *osi_core,
 	nveu32_t count = 0U;
 
 	while ((temp != head) && (count < MAX_TX_TS_CNT)) {
+		if (osi_core->mac != OSI_MAC_HW_MGBE_T26X) {
 			if (((temp->pkt_id >> CHAN_START_POSITION) & chan) == chan) {
 				temp->next->prev = temp->prev;
 				temp->prev->next = temp->next;
 				/* reset in_use for temp node from the link */
 				temp->in_use = OSI_DISABLE;
 			}
+		} else {
+			if (temp->vdma_id == chan) {
+				temp->next->prev = temp->prev;
+				temp->prev->next = temp->next;
+				/* reset in_use for temp node from the link */
+				temp->in_use = OSI_DISABLE;
+			}
+		}
 		count++;
 		temp = temp->next;
 	}
@@ -1842,6 +1850,7 @@ static inline nve32_t get_tx_ts(struct osi_core_priv_data *osi_core,
 			temp = temp->next;
 			continue;
 		} else if ((temp->pkt_id == ts->pkt_id) &&
+			   (temp->vdma_id == ts->vdma_id) &&
 			   (temp->in_use != OSI_NONE)) {
 			ts->sec = temp->sec;
 			ts->nsec = temp->nsec;
@@ -2222,8 +2231,13 @@ fail:
 static void cfg_l3_l4_filter(struct core_local *l_core)
 {
 	nveu32_t i = 0U;
+	const nveu32_t max_filter_no[OSI_MAX_MAC_IP_TYPES] = {
+		EQOS_MAX_L3_L4_FILTER,
+		OSI_MGBE_MAX_L3_L4_FILTER,
+		OSI_MGBE_MAX_L3_L4_FILTER_T264,
+	};
 
-	for (i = 0U; i < OSI_MGBE_MAX_L3_L4_FILTER; i++) {
+	for (i = 0U; i < max_filter_no[l_core->osi_core.mac]; i++) {
 		if (l_core->cfg.l3_l4[i].filter_enb_dis == OSI_L3L4_DISABLE) {
 			/* filter not enabled */
 			continue;

osi/core/xpcs.c

@@ -263,6 +263,91 @@ fail:
 	return ret;
 }
 
+/**
+ * @brief xlgpcs_start - Start XLGPCS
+ *
+ * Algorithm: This routine enables AN and set speed based on AN status
+ *
+ * @param[in] osi_core: OSI core data structure.
+ *
+ * @retval 0 on success
+ * @retval -1 on failure.
+ */
+nve32_t xlgpcs_start(struct osi_core_priv_data *osi_core)
+{
+	void *xpcs_base = osi_core->xpcs_base;
+	nveu32_t retry = RETRY_COUNT;
+	nveu32_t count = 0;
+	nveu32_t ctrl = 0;
+	nve32_t ret = 0;
+	nve32_t cond = COND_NOT_MET;
+
+	if (xpcs_base == OSI_NULL) {
+		OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
+			     "XLGPCS base is NULL", 0ULL);
+		ret = -1;
+		goto fail;
+	}
+	/* * XLGPCS programming guideline IAS section 7.1.3.2.2.2
+	 */
+	/* 4 Poll SR_PCS_CTRL1 reg RST bit */
+	ctrl = xpcs_read(xpcs_base, XLGPCS_SR_PCS_CTRL1);
+	ctrl |= XLGPCS_SR_PCS_CTRL1_RST;
+	xpcs_write(xpcs_base, XLGPCS_SR_PCS_CTRL1, ctrl);
+
+	count = 0;
+	while (cond == 1) {
+		if (count > retry) {
+			ret = -1;
+			goto fail;
+		}
+		count++;
+		ctrl = xpcs_read(xpcs_base, XLGPCS_SR_PCS_CTRL1);
+		if ((ctrl & XLGPCS_SR_PCS_CTRL1_RST) == 0U) {
+			cond = 0;
+		} else {
+			/* Maximum wait delay as per HW team is 10msec.
+			 * So add a loop for 1000 iterations with 1usec delay,
+			 * so that if check get satisfies before 1msec will come
+			 * out of loop and it can save some boot time
+			 */
+			osi_core->osd_ops.udelay(10U);
+		}
+	}
+	/* 5 Program SR_AN_CTRL reg AN_EN bit to disable auto-neg */
+	ctrl = xpcs_read(xpcs_base, XLGPCS_SR_AN_CTRL);
+	ctrl &= ~XLGPCS_SR_AN_CTRL_AN_EN;
+	ret = xpcs_write_safety(osi_core, XLGPCS_SR_AN_CTRL, ctrl);
+	if (ret != 0) {
+		goto fail;
+	}
+
+	/* 6 Wait for SR_PCS_STS1 reg RLU bit to set */
+	cond = COND_NOT_MET;
+	count = 0;
+	while (cond == COND_NOT_MET) {
+		if (count > retry) {
+			ret = -1;
+			break;
+		}
+		count++;
+		ctrl = xpcs_read(xpcs_base, XLGPCS_SR_PCS_STS1);
+		if ((ctrl & XLGPCS_SR_PCS_STS1_RLU) ==
+		    XLGPCS_SR_PCS_STS1_RLU) {
+			cond = COND_MET;
+		} else {
+			/* Maximum wait delay as per HW team is 10msec.
+			 * So add a loop for 1000 iterations with 1usec delay,
+			 * so that if check get satisfies before 1msec will come
+			 * out of loop and it can save some boot time
+			 */
+			osi_core->osd_ops.udelay(10U);
+		}
+	}
+fail:
+	return ret;
+}
+
 /**
  * @brief xpcs_uphy_lane_bring_up - Bring up UPHY Tx/Rx lanes
  *
@@ -697,7 +782,7 @@ nve32_t xpcs_init(struct osi_core_priv_data *osi_core)
 		ctrl = xpcs_read(xpcs_base, XPCS_VR_XS_PCS_KR_CTRL);
 		ctrl &= ~(XPCS_VR_XS_PCS_KR_CTRL_USXG_MODE_MASK);
 
-		if (osi_core->uphy_gbe_mode == OSI_DISABLE) {
+		if (osi_core->uphy_gbe_mode == OSI_GBE_MODE_5G) {
 			ctrl |= XPCS_VR_XS_PCS_KR_CTRL_USXG_MODE_5G;
 		}
 	}
@@ -717,6 +802,129 @@ fail:
 	return ret;
 }
 
+
+/**
+ * @brief xlgpcs_init - XLGPCS initialization
+ *
+ * Algorithm: This routine initialize XLGPCS in USXMII mode.
+ *
+ * @param[in] osi_core: OSI core data structure.
+ *
+ * @retval 0 on success
+ * @retval -1 on failure.
+ */
+nve32_t xlgpcs_init(struct osi_core_priv_data *osi_core)
+{
+	void *xpcs_base = osi_core->xpcs_base;
+	nveu32_t retry = 1000;
+	nveu32_t count;
+	nveu32_t ctrl = 0;
+	nve32_t cond = COND_NOT_MET;
+	nve32_t ret = 0;
+	nveu32_t value = 0;
+
+	if (osi_core->xpcs_base == OSI_NULL) {
+		OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
+			     "XLGPCS base is NULL", 0ULL);
+		ret = -1;
+		goto fail;
+	}
+
+	if (osi_core->pre_sil == 0x1U) {
+		OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
+			     "Pre-silicon, skipping lane bring up", 0ULL);
+	} else {
+		/* Select XLGPCS in wrapper register */
+		if ((osi_core->mac == OSI_MAC_HW_MGBE_T26X) &&
+		    (osi_core->uphy_gbe_mode == OSI_UPHY_GBE_MODE_25G)) {
+			value = osi_readla(osi_core, (nveu8_t *)osi_core->xpcs_base +
+					   T26X_XPCS_WRAP_CONFIG_0);
+			value |= OSI_BIT(0);
+			osi_writela(osi_core, value, (nveu8_t *)osi_core->xpcs_base +
+				    T26X_XPCS_WRAP_CONFIG_0);
+		}
+
+		if (xpcs_lane_bring_up(osi_core) < 0) {
+			ret = -1;
+			goto fail;
+		}
+	}
+	/* Switching to USXGMII Mode to 25G based on
+	 * XLGPCS programming guideline IAS section 7.1.3.2.2.1
+	 */
+	/* 1.Program SR_PCS_CTRL1 reg SS_5_2 bits */
+	ctrl = xpcs_read(xpcs_base, XLGPCS_SR_PCS_CTRL1);
+	ctrl &= ~XLGPCS_SR_PCS_CTRL1_SS5_2_MASK;
+	ctrl |= XLGPCS_SR_PCS_CTRL1_SS5_2;
+	ret = xpcs_write_safety(osi_core, XLGPCS_SR_PCS_CTRL1, ctrl);
+	if (ret != 0) {
+		goto fail;
+	}
+	/* 2.Program SR_PCS_CTRL2 reg PCS_TYPE_SEL bits */
+	ctrl = xpcs_read(xpcs_base, XLGPCS_SR_PCS_CTRL2);
+	ctrl &= ~XLGPCS_SR_PCS_CTRL2_PCS_TYPE_SEL_MASK;
+	ctrl |= XLGPCS_SR_PCS_CTRL2_PCS_TYPE_SEL;
+	ret = xpcs_write_safety(osi_core, XLGPCS_SR_PCS_CTRL2, ctrl);
+	if (ret != 0) {
+		goto fail;
+	}
+	/* 3.Program SR_PMA_CTRL2 reg PMA_TYPE bits */
+	ctrl = xpcs_read(xpcs_base, XLGPCS_SR_PMA_CTRL2);
+	ctrl &= ~XLGPCS_SR_PMA_CTRL2_PMA_TYPE_MASK;
+	ctrl |= XLGPCS_SR_PMA_CTRL2_PMA_TYPE;
+	ret = xpcs_write_safety(osi_core, XLGPCS_SR_PMA_CTRL2, ctrl);
+	if (ret != 0) {
+		goto fail;
+	}
+	/* 4.NA [Program VR_PCS_MMD Digital Control3 reg EN_50G bit
+	 * to disable 50G] 25G mode selected for T264 */
+	/* 5.Program VR_PCS_MMD Digital Control3 reg CNS_EN bit to 1 to
+	 * enable 25G as per manual */
+	ctrl = xpcs_read(xpcs_base, XLGPCS_VR_PCS_DIG_CTRL3);
+	ctrl |= XLGPCS_VR_PCS_DIG_CTRL3_CNS_EN;
+	ret = xpcs_write_safety(osi_core, XLGPCS_VR_PCS_DIG_CTRL3, ctrl);
+	if (ret != 0) {
+		goto fail;
+	}
+
+	/* 6.NA. Enable RS FEC */
+	/* 7. Enable BASE-R FEC */
+	ctrl = xpcs_read(xpcs_base, XLGPCS_SR_PMA_KR_FEC_CTRL);
+	ctrl |= XLGPCS_SR_PMA_KR_FEC_CTRL_FEC_EN;
+	ret = xpcs_write_safety(osi_core, XLGPCS_SR_PMA_KR_FEC_CTRL, ctrl);
+	if (ret != 0) {
+		goto fail;
+	}
+
+	/* 8.NA, Configure PHY to 25G rate */
+	/* 9.Program VR_PCS_DIG_CTRL1 reg VR_RST bit */
+	ctrl = xpcs_read(xpcs_base, XLGPCS_VR_PCS_DIG_CTRL1);
+	ctrl |= XLGPCS_VR_PCS_DIG_CTRL1_VR_RST;
+	xpcs_write(xpcs_base, XLGPCS_VR_PCS_DIG_CTRL1, ctrl);
+	/* 10.Wait for VR_PCS_DIG_CTRL1 reg VR_RST bit to self clear */
+	count = 0;
+	while (cond == COND_NOT_MET) {
+		if (count > retry) {
+			ret = -1;
+			goto fail;
+		}
+		count++;
+		ctrl = xpcs_read(xpcs_base, XLGPCS_VR_PCS_DIG_CTRL1);
+		if ((ctrl & XLGPCS_VR_PCS_DIG_CTRL1_VR_RST) == 0U) {
+			cond = 0;
+		} else {
+			/* Maximum wait delay as per HW team is 10msec.
+			 * So add a loop for 1000 iterations with 1usec delay,
+			 * so that if check get satisfies before 1msec will come
+			 * out of loop and it can save some boot time
+			 */
+			osi_core->osd_ops.udelay(10U);
+		}
+	}
+fail:
+	return ret;
+}
+
 #ifndef OSI_STRIPPED_LIB
 /**
  * @brief xpcs_eee - XPCS enable/disable EEE
@@ -781,4 +989,93 @@ nve32_t xpcs_eee(struct osi_core_priv_data *osi_core, nveu32_t en_dis)
 fail:
 	return ret;
 }
+
+/**
+ * @brief xlgpcs_eee - XLGPCS enable/disable EEE
+ *
+ * Algorithm: This routine update register related to EEE
+ * for XLGPCS.
+ *
+ * @param[in] osi_core: OSI core data structure.
+ * @param[in] en_dis: enable - 1 or disable - 0
+ *
+ * @retval 0 on success
+ * @retval -1 on failure.
+ */
+nve32_t xlgpcs_eee(struct osi_core_priv_data *osi_core, nveu32_t en_dis)
+{
+	void *xpcs_base = osi_core->xpcs_base;
+	nveu32_t val = 0x0U;
+	nve32_t ret = 0;
+	nveu32_t retry = 1000U;
+	nveu32_t count = 0;
+	nve32_t cond = COND_NOT_MET;
+
+	if ((en_dis != OSI_ENABLE) && (en_dis != OSI_DISABLE)) {
+		ret = -1;
+		goto fail;
+	}
+
+	if (xpcs_base == OSI_NULL) {
+		ret = -1;
+		goto fail;
+	}
+
+	if (en_dis == OSI_DISABLE) {
+		val = xpcs_read(xpcs_base, XLGPCS_VR_PCS_EEE_MCTRL);
+		val &= ~XPCS_VR_XS_PCS_EEE_MCTRL0_LTX_EN;
+		val &= ~XPCS_VR_XS_PCS_EEE_MCTRL0_LRX_EN;
+		ret = xpcs_write_safety(osi_core, XLGPCS_VR_PCS_EEE_MCTRL, val);
+		/* To disable EEE on TX side, the software must wait for
+		 * TX LPI to enter TX_ACTIVE state by reading
+		 * VR_PCS_DIG_STS Register
+		 */
+		while (cond == COND_NOT_MET) {
+			if (count > retry) {
+				ret = -1;
+				OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
+					"EEE active state timeout!", 0ULL);
+				goto fail;
+			}
+			count++;
+			val = xpcs_read(xpcs_base, XLGPCS_VR_PCS_DIG_STS);
+			if ((val & XLGPCS_VR_PCS_DIG_STSLTXRX_STATE) == 0U) {
+				cond = 0;
+			} else {
+				osi_core->osd_ops.udelay(100U);
+			}
+		}
+	} else {
+
+		/* 1. Check if DWC_xlgpcs supports the EEE feature
+		 * by reading the SR_PCS_EEE_ABL reg. For 25G always enabled
+		 * by default
+		 */
+
+		/* 2. Program various timers used in the EEE mode depending on
+		 * the clk_eee_i clock frequency. default timers are same as
+		 * IEEE std clk_eee_i() is 108MHz. MULT_FACT_100NS = 9
+		 * because 9.2ns*10 = 92 which is between 80 and 120 this
+		 * leads to default setting match.
+		 */
+
+		/* 3. NA. [If FEC is enabled in the KR mode] */
+		/* 4. NA. [Enable fast_sim mode] */
+		/* 5. NA [If RS FEC is enabled, program AM interval and RS FEC]
+		 */
+		/* 6. NA [Fast wake is not enabled default] */
+		/* 7. Enable the EEE feature on Tx and Rx path */
+		val = xpcs_read(xpcs_base, XLGPCS_VR_PCS_EEE_MCTRL);
+		val |= (XPCS_VR_XS_PCS_EEE_MCTRL0_LTX_EN |
+			XPCS_VR_XS_PCS_EEE_MCTRL0_LRX_EN);
+		ret = xpcs_write_safety(osi_core, XLGPCS_VR_PCS_EEE_MCTRL, val);
+		if (ret != 0) {
+			goto fail;
+		}
+		/* 8. NA [If PMA service interface is XLAUI or CAUI] */
+	}
+fail:
+	return ret;
+}
+
 #endif /* !OSI_STRIPPED_LIB */

osi/core/xpcs.h

@@ -48,16 +48,65 @@
 #define T26X_XPCS_WRAP_UPHY_HW_INIT_CTRL	0x8034
 #define T26X_XPCS_WRAP_UPHY_STATUS		0x8074
 #define T26X_XPCS_WRAP_INTERRUPT_STATUS		0x8080
+#define T26X_XPCS_WRAP_CONFIG_0			0x8094
+
+/** @} */
+
+/**
+ * @addtogroup XLGPCS Register offsets
+ *
+ * @brief XLGPCS register offsets
+ * @{
+ */
+#define XLGPCS_SR_PMA_CTRL2			0x4001c
+#define XLGPCS_SR_PMA_KR_FEC_CTRL		0x402ac
+#define XLGPCS_SR_PCS_CTRL1			0xc0000
+#define XLGPCS_SR_PCS_STS1			0xc0004
+#define XLGPCS_SR_PCS_CTRL2			0xc001c
+#define XLGPCS_VR_PCS_DIG_CTRL1			0xe0000
+#define XLGPCS_VR_PCS_DIG_CTRL3			0xe000c
+#define XLGPCS_SR_AN_CTRL			0x1c0000
+
+/** @} */
+
+/**
+ * @addtogroup XLGPCS-BIT Register bit fileds
+ *
+ * @brief XLGPCS register bit fields and values
+ * @{
+ */
+#define XLGPCS_SR_PCS_CTRL1_RST			OSI_BIT(15)
+#define XLGPCS_SR_AN_CTRL_AN_EN			OSI_BIT(12)
+#define XLGPCS_SR_PCS_STS1_RLU			OSI_BIT(2)
+#define XLGPCS_SR_PCS_CTRL1_SS5_2		OSI_BIT(2) | OSI_BIT(4)
+#define XLGPCS_SR_PCS_CTRL1_SS5_2_MASK		OSI_BIT(5) | OSI_BIT(4) | \
+						OSI_BIT(3) | OSI_BIT(2)
+#define XLGPCS_SR_PCS_CTRL2_PCS_TYPE_SEL	OSI_BIT(2) | OSI_BIT(1) | \
+						OSI_BIT(0)
+#define XLGPCS_SR_PCS_CTRL2_PCS_TYPE_SEL_MASK	OSI_BIT(3) | OSI_BIT(2) | \
+						OSI_BIT(1) | OSI_BIT(0)
+#define XLGPCS_SR_PMA_CTRL2_PMA_TYPE		OSI_BIT(5) | OSI_BIT(4) | \
+						OSI_BIT(3) | OSI_BIT(0)
+#define XLGPCS_SR_PMA_CTRL2_PMA_TYPE_MASK	0x7F
+#define XLGPCS_VR_PCS_DIG_CTRL3_CNS_EN		OSI_BIT(0)
+#define XLGPCS_VR_PCS_DIG_CTRL1_VR_RST		OSI_BIT(15)
+#define XLGPCS_SR_PMA_KR_FEC_CTRL_FEC_EN	OSI_BIT(0)
 
 /** @} */
 
 #ifndef OSI_STRIPPED_LIB
 #define XPCS_VR_XS_PCS_EEE_MCTRL0		0xE0018
 #define XPCS_VR_XS_PCS_EEE_MCTRL1		0xE002C
+#define XLGPCS_VR_PCS_EEE_MCTRL			0xe0018
+#define XLGPCS_VR_PCS_DIG_STS			0xe0040
 
 #define XPCS_VR_XS_PCS_EEE_MCTRL1_TRN_LPI	OSI_BIT(0)
 #define XPCS_VR_XS_PCS_EEE_MCTRL0_LTX_EN	OSI_BIT(0)
 #define XPCS_VR_XS_PCS_EEE_MCTRL0_LRX_EN	OSI_BIT(1)
+#define XLGPCS_VR_PCS_DIG_STSLTXRX_STATE	(OSI_BIT(15) | OSI_BIT(14) | \
+						OSI_BIT(13) | OSI_BIT(12) | \
+						OSI_BIT(11) | OSI_BIT(10))
+
 #endif /* !OSI_STRIPPED_LIB */
 
 /**
@@ -124,8 +173,11 @@
 
 nve32_t xpcs_init(struct osi_core_priv_data *osi_core);
 nve32_t xpcs_start(struct osi_core_priv_data *osi_core);
+nve32_t xlgpcs_init(struct osi_core_priv_data *osi_core);
+nve32_t xlgpcs_start(struct osi_core_priv_data *osi_core);
 #ifndef OSI_STRIPPED_LIB
 nve32_t xpcs_eee(struct osi_core_priv_data *osi_core, nveu32_t en_dis);
+nve32_t xlgpcs_eee(struct osi_core_priv_data *osi_core, nveu32_t en_dis);
 #endif /* !OSI_STRIPPED_LIB */
 
 /**

osi/dma/dma_local.h

@@ -41,6 +41,7 @@
 /**
  * @brief validate_dma_mac_ver_update_chans - Validates mac version and update chan
  *
+ * @param[in] mac: MAC HW type.
  * @param[in] mac_ver: MAC version read.
  * @param[out] num_max_chans: Maximum channel number.
  * @param[out] l_mac_ver: local mac version.
@@ -56,10 +57,16 @@
  * @retval 0 - for not Valid MAC
  * @retval 1 - for Valid MAC
  */
-static inline nve32_t validate_dma_mac_ver_update_chans(nveu32_t mac_ver,
+static inline nve32_t validate_dma_mac_ver_update_chans(nveu32_t mac,
+						        nveu32_t mac_ver,
 						        nveu32_t *num_max_chans,
 						        nveu32_t *l_mac_ver)
 {
+	const nveu32_t max_dma_chan[OSI_MAX_MAC_IP_TYPES] = {
+		OSI_EQOS_MAX_NUM_CHANS,
+		OSI_MGBE_T23X_MAX_NUM_CHANS,
+		OSI_MGBE_MAX_NUM_CHANS
+	};
 	nve32_t ret;
 
 	switch (mac_ver) {
@@ -69,17 +76,21 @@ static inline nve32_t validate_dma_mac_ver_update_chans(nveu32_t mac_ver,
 		*l_mac_ver = MAC_CORE_VER_TYPE_EQOS;
 		ret = 1;
 		break;
-#endif
+#endif /* !OSI_STRIPPED_LIB */
 	case OSI_EQOS_MAC_5_30:
 		*num_max_chans = OSI_EQOS_MAX_NUM_CHANS;
 		*l_mac_ver = MAC_CORE_VER_TYPE_EQOS_5_30;
 		ret = 1;
 		break;
 	case OSI_MGBE_MAC_3_10:
+	//TBD: T264 uFPGA reports mac version 3.2
+	case OSI_MGBE_MAC_3_20:
+	case OSI_MGBE_MAC_4_20:
 #ifndef OSI_STRIPPED_LIB
 	case OSI_MGBE_MAC_4_00:
 #endif /* !OSI_STRIPPED_LIB */
-		*num_max_chans = OSI_MGBE_MAX_NUM_CHANS;
+		//TBD: T264 number of dma channels?
+		*num_max_chans = max_dma_chan[mac];
 		*l_mac_ver = MAC_CORE_VER_TYPE_MGBE;
 		ret = 1;
 		break;
@@ -135,10 +146,13 @@ static inline void osi_dma_writel(nveu32_t val, void *addr)
  */
 #define CHAN_START_POSITION 6U
 #define PKT_ID_CNT	((nveu32_t)1 << CHAN_START_POSITION)
+#define PKT_ID_CNT_T264 ((nveu32_t)1 << 10)
 /* First 6 bytes of idx and last 4 bytes of chan(+1 to avoid pkt_id to be 0) */
 #define INC_TX_TS_PKTID(idx) ((idx) = (((idx) & 0x7FFFFFFFU) + 1U))
 #define GET_TX_TS_PKTID(idx, c) (((idx) & (PKT_ID_CNT - 1U)) | \
 				 (((c) + 1U) << CHAN_START_POSITION))
+/* T264 has saperate logic to tell vdma number so we can use all 10 bits for pktid */
+#define GET_TX_TS_PKTID_T264(idx) ((++(idx)) & (PKT_ID_CNT_T264 - 1U))
 /** @} */
 
 /**
@@ -210,8 +224,11 @@ struct dma_local {
 	 * PacketID for PTP TS.
 	 * MSB 4-bits of channel number and LSB 6-bits of local
 	 * index(PKT_ID_CNT).
+	 * In T264, it is 9 bits PKTID
 	 */
 	nveu32_t pkt_id;
+	/** VDMA number for T264 */
+	nveu32_t vdma_id;
 	/** Flag to represent OSI DMA software init done */
 	nveu32_t init_done;
 	/** Holds the MAC version of MAC controller */
@@ -329,7 +346,9 @@ static inline void update_rx_tail_ptr(const struct osi_dma_priv_data *const osi_
 				      nveu32_t dma_chan,
 				      nveu64_t tailptr)
 {
-	nveu32_t chan = dma_chan & 0xFU;
+	const nveu32_t chan_mask[OSI_MAX_MAC_IP_TYPES] = {0xFU, 0xFU, 0x3FU};
+
+	nveu32_t chan = dma_chan & chan_mask[osi_dma->mac];
 	const nveu32_t tail_ptr_reg[OSI_MAX_MAC_IP_TYPES] = {
 		EQOS_DMA_CHX_RDTP(chan),
 		MGBE_DMA_CHX_RDTLP(chan),

osi/dma/mgbe_dma.h

@@ -57,6 +57,8 @@
 #define MGBE_DMA_CHX_RDLH(x)		((0x0080U * (x)) + 0x3118U)
 #define MGBE_DMA_CHX_RDLA(x)		((0x0080U * (x)) + 0x311CU)
 #define MGBE_DMA_CHX_RDTLP(x)		((0x0080U * (x)) + 0x312CU)
+#define MGBE_DMA_CHX_RX_DESC_WR_RNG_OFFSET(x)	((0x0080U * (x)) + 0x317CU)
+
 /** @} */
 
 /** @} */
@@ -71,6 +73,12 @@
 #define MGBE_DMA_CHX_RX_WDT_RWTU		2048U
 #define MGBE_DMA_CHX_RX_WDT_RWTU_2048_CYCLE	0x3000U
 #define MGBE_DMA_CHX_RX_WDT_RWTU_MASK		0x3000U
+#define MGBE_DMA_CHX_RX_WDT_ITW_MASK		0x7C000000U
+#define MGBE_DMA_CHX_RX_WDT_ITW_SHIFT		26U
+#define MGBE_DMA_CHX_RX_WDT_ITW_MAX		0x1FU
+#define MGBE_DMA_CHX_RX_WDT_ITW_DEFAULT		1100U
+#define MGBE_DMA_CHX_RX_WDT_ITCU		256U
+
 #ifdef OSI_DEBUG
 #define MGBE_DMA_CHX_INTR_TBUE			OSI_BIT(2)
 #define MGBE_DMA_CHX_INTR_RBUE			OSI_BIT(7)
@@ -92,6 +100,8 @@
 #define MGBE_TX_VDMA_TC_SHIFT			4
 #define MGBE_RX_VDMA_TC_MASK			(OSI_BIT(28) | OSI_BIT(29) | OSI_BIT(30))
 #define MGBE_RX_VDMA_TC_SHIFT			28
+#define MGBE_RX_DESC_WR_RNG_RWDC_SHIFT		16
+
 /** @} */
 
 /**

osi/dma/osi_dma.c

@@ -33,6 +33,44 @@
 #endif /* OSI_DEBUG */
 #include "hw_common.h"
 
+#if 1 // copied from osi/core/common.h
+
+/**
+ * @brief MTL Q size depth helper macro
+ */
+#define Q_SZ_DEPTH(x)		(((x) * 1024U) / (MGBE_AXI_DATAWIDTH / 8U))
+
+/* PBL values */
+//redefined #define MGBE_DMA_CHX_MAX_PBL	32U
+#define MGBE_DMA_CHX_PBL_16	16U
+#define MGBE_DMA_CHX_PBL_8	8U
+#define MGBE_DMA_CHX_PBL_4	4U
+#define MGBE_DMA_CHX_PBL_1	1U
+
+static inline nveu32_t osi_valid_pbl_value(nveu32_t pbl_value)
+{
+	nveu32_t allowed_pbl;
+	nveu32_t pbl;
+
+	/* 8xPBL mode is set */
+	pbl = pbl_value / 8U;
+
+	if (pbl >= MGBE_DMA_CHX_MAX_PBL) {
+		allowed_pbl = MGBE_DMA_CHX_MAX_PBL;
+	} else if (pbl >= MGBE_DMA_CHX_PBL_16) {
+		allowed_pbl = MGBE_DMA_CHX_PBL_16;
+	} else if (pbl >= MGBE_DMA_CHX_PBL_8) {
+		allowed_pbl = MGBE_DMA_CHX_PBL_8;
+	} else if (pbl >= MGBE_DMA_CHX_PBL_4) {
+		allowed_pbl = MGBE_DMA_CHX_PBL_4;
+	} else {
+		allowed_pbl = MGBE_DMA_CHX_PBL_1;
+	}
+
+	return allowed_pbl;
+}
+#endif
+
 /**
  * @brief g_dma - DMA local data array.
  */
@@ -470,7 +508,8 @@ done:
 }
 static inline void start_dma(const struct osi_dma_priv_data *const osi_dma, nveu32_t dma_chan)
 {
-	nveu32_t chan = dma_chan & 0xFU;
+	const nveu32_t chan_mask[OSI_MAX_MAC_IP_TYPES] = {0xFU, 0xFU, 0x3FU};
+	nveu32_t chan = dma_chan & chan_mask[osi_dma->mac];
 	const nveu32_t tx_dma_reg[OSI_MAX_MAC_IP_TYPES] = {
 		EQOS_DMA_CHX_TX_CTRL(chan),
 		MGBE_DMA_CHX_TX_CTRL(chan),
@@ -498,8 +537,10 @@ static inline void start_dma(const struct osi_dma_priv_data *const osi_dma, nveu
 static nve32_t init_dma_channel(const struct osi_dma_priv_data *const osi_dma,
 			     nveu32_t dma_chan)
 {
+	const nveu32_t chan_mask[OSI_MAX_MAC_IP_TYPES] = {0xFU, 0xFU, 0x3FU};
+	nveu32_t pbl = 0;
 	nveu32_t pdma_chan = 0xFFU;
-	nveu32_t chan = dma_chan & 0xFU;
+	nveu32_t chan = dma_chan & chan_mask[osi_dma->mac];
 	nveu32_t riwt = osi_dma->rx_riwt & 0xFFFU;
 	const nveu32_t intr_en_reg[OSI_MAX_MAC_IP_TYPES] = {
 		EQOS_DMA_CHX_INTR_ENA(chan),
@@ -532,7 +573,8 @@ static nve32_t init_dma_channel(const struct osi_dma_priv_data *const osi_dma,
 	};
 	const nveu32_t rx_pbl[2] = {
 		EQOS_DMA_CHX_RX_CTRL_RXPBL_RECOMMENDED,
-		((MGBE_RXQ_SIZE / osi_dma->num_dma_chans) / 2U)
+		((Q_SZ_DEPTH(MGBE_RXQ_SIZE/OSI_MGBE_MAX_NUM_QUEUES) /
+		osi_dma->num_dma_chans) / 2U)
 	};
 	const nveu32_t rwt_val[OSI_MAX_MAC_IP_TYPES] = {
 		(((riwt * (EQOS_AXI_CLK_FREQ / OSI_ONE_MEGA_HZ)) /
@@ -558,8 +600,7 @@ static nve32_t init_dma_channel(const struct osi_dma_priv_data *const osi_dma,
 		DMA_CHX_TX_CTRL_TSE
 	};
 	const nveu32_t owrq = (MGBE_DMA_CHX_RX_CNTRL2_OWRQ_MCHAN / osi_dma->num_dma_chans);
-	//TBD: owrq_arr add more entries for T264?
+	const nveu32_t owrq_arr[OSI_MGBE_T23X_MAX_NUM_CHANS] = {
-	const nveu32_t owrq_arr[OSI_MGBE_MAX_NUM_CHANS] = {
 		MGBE_DMA_CHX_RX_CNTRL2_OWRQ_SCHAN, owrq, owrq, owrq,
 		owrq, owrq, owrq, owrq, owrq, owrq
 	};
@@ -620,12 +661,8 @@ static nve32_t init_dma_channel(const struct osi_dma_priv_data *const osi_dma,
 		 * as the TxPBL else we should be using the value whcih we get after
 		 * calculation by using above formula
 		 */
-		if (tx_pbl[osi_dma->mac] >= MGBE_DMA_CHX_MAX_PBL) {
+		pbl = osi_valid_pbl_value(tx_pbl[osi_dma->mac]);
-			val |= MGBE_DMA_CHX_MAX_PBL_VAL;
+		val |= (pbl << MGBE_DMA_CHX_CTRL_PBL_SHIFT);
-		} else {
-			val |= ((tx_pbl[osi_dma->mac] / 8U) <<
-				MGBE_DMA_CHX_CTRL_PBL_SHIFT);
-		}
 	} else if (osi_dma->mac == OSI_MAC_HW_MGBE_T26X) {
 		/* Map Tx VDMA's to TC. TC and PDMA mapped 1 to 1 */
 		val &= ~MGBE_TX_VDMA_TC_MASK;
@@ -648,12 +685,8 @@ static nve32_t init_dma_channel(const struct osi_dma_priv_data *const osi_dma,
 	if (osi_dma->mac == OSI_MAC_HW_EQOS) {
 		val |= rx_pbl[osi_dma->mac];
 	} else if (osi_dma->mac == OSI_MAC_HW_MGBE){
-		if (rx_pbl[osi_dma->mac] >= MGBE_DMA_CHX_MAX_PBL) {
+		pbl = osi_valid_pbl_value(rx_pbl[osi_dma->mac]);
-			val |= MGBE_DMA_CHX_MAX_PBL_VAL;
+		val |= (pbl << MGBE_DMA_CHX_CTRL_PBL_SHIFT);
-		} else {
-			val |= ((rx_pbl[osi_dma->mac] / 8U) <<
-				MGBE_DMA_CHX_CTRL_PBL_SHIFT);
-		}
 	} else if (osi_dma->mac == OSI_MAC_HW_MGBE_T26X) {
 	/* Map Rx VDMA's to TC. TC and PDMA mapped 1 to 1 */
 		val &= ~MGBE_RX_VDMA_TC_MASK;
@@ -777,7 +810,7 @@ nve32_t osi_hw_dma_init(struct osi_dma_priv_data *osi_dma)
 
 	l_dma->mac_ver = osi_dma_readl((nveu8_t *)osi_dma->base + MAC_VERSION) &
 				       MAC_VERSION_SNVER_MASK;
-	if (validate_dma_mac_ver_update_chans(l_dma->mac_ver,
+	if (validate_dma_mac_ver_update_chans(osi_dma->mac, l_dma->mac_ver,
 			       		      &l_dma->num_max_chans,
 					      &l_dma->l_mac_ver) == 0) {
 		OSI_DMA_ERR(osi_dma->osd, OSI_LOG_ARG_INVALID,
@@ -825,7 +858,8 @@ fail:
 static inline void stop_dma(const struct osi_dma_priv_data *const osi_dma,
 			    nveu32_t dma_chan)
 {
-	nveu32_t chan = dma_chan & 0xFU;
+	const nveu32_t chan_mask[OSI_MAX_MAC_IP_TYPES] = {0xFU, 0xFU, 0x3FU};
+	nveu32_t chan = dma_chan & chan_mask[osi_dma->mac];
 	const nveu32_t dma_tx_reg[OSI_MAX_MAC_IP_TYPES] = {
 		EQOS_DMA_CHX_TX_CTRL(chan),
 		MGBE_DMA_CHX_TX_CTRL(chan),
@@ -850,6 +884,71 @@ static inline void stop_dma(const struct osi_dma_priv_data *const osi_dma,
 	osi_dma_writel(val, (nveu8_t *)osi_dma->base + dma_rx_reg[osi_dma->mac]);
 }
 
+static inline void set_rx_riit_dma(
+			const struct osi_dma_priv_data *const osi_dma,
+			nveu32_t chan, nveu32_t riit)
+{
+	const nveu32_t rx_wdt_reg[OSI_MAX_MAC_IP_TYPES] = {
+		EQOS_DMA_CHX_RX_WDT(chan),
+		MGBE_DMA_CHX_RX_WDT(chan),
+		MGBE_DMA_CHX_RX_WDT(chan)
+	};
+	/* riit is in ns */
+	const nveu32_t itw_val = {
+		(((riit * ((nveu32_t)MGBE_AXI_CLK_FREQ / OSI_ONE_MEGA_HZ)) /
+		 (MGBE_DMA_CHX_RX_WDT_ITCU * OSI_MSEC_PER_SEC))
+		 & MGBE_DMA_CHX_RX_WDT_ITW_MAX)
+	};
+	nveu32_t val;
+
+	if (osi_dma->use_riit != OSI_DISABLE &&
+		osi_dma->mac == OSI_MAC_HW_MGBE_T26X) {
+		val = osi_dma_readl((nveu8_t *)osi_dma->base +
+			rx_wdt_reg[osi_dma->mac]);
+		val &= ~MGBE_DMA_CHX_RX_WDT_ITW_MASK;
+		val |= (itw_val << MGBE_DMA_CHX_RX_WDT_ITW_SHIFT);
+		osi_dma_writel(val, (nveu8_t *)osi_dma->base +
+			rx_wdt_reg[osi_dma->mac]);
+	}
+
+	return;
+}
+
+static inline void set_rx_riit(
+		const struct osi_dma_priv_data *const osi_dma, nveu32_t speed)
+{
+	nveu32_t i, chan, riit;
+	nveu32_t found =OSI_DISABLE;
+
+	for (i = 0; i < osi_dma->num_of_riit; i++) {
+		if (osi_dma->rx_riit[i].speed == speed) {
+			riit = osi_dma->rx_riit[i].riit;
+			found = OSI_ENABLE;
+			break;
+		}
+	}
+
+	if (found != OSI_ENABLE) {
+		/* use default ~1us value */
+		riit = MGBE_DMA_CHX_RX_WDT_ITW_DEFAULT;
+		OSI_DMA_ERR(osi_dma->osd, OSI_LOG_ARG_INVALID,
+			    "Invalid speed value, using default riit 1us\n",
+			    speed);
+	}
+
+	/* riit is in nsec */
+	if ((riit  > (osi_dma->rx_riwt * OSI_MSEC_PER_SEC))) {
+		OSI_DMA_ERR(osi_dma->osd, OSI_LOG_ARG_INVALID,
+			    "Invalid riit value, using default 1us\n", riit);
+	}
+
+	for (i = 0; i < osi_dma->num_dma_chans; i++) {
+		chan = osi_dma->dma_chans[i];
+		set_rx_riit_dma(osi_dma, chan, riit);
+	}
+	return;
+}
+
 nve32_t osi_hw_dma_deinit(struct osi_dma_priv_data *osi_dma)
 {
 	struct dma_local *l_dma = (struct dma_local *)(void *)osi_dma;
@@ -1331,7 +1430,7 @@ fail:
 	return ret;
 }
 
-#ifdef OSI_DEBUG
+
 nve32_t osi_dma_ioctl(struct osi_dma_priv_data *osi_dma)
 {
 	struct dma_local *l_dma = (struct dma_local *)osi_dma;
@@ -1347,6 +1446,7 @@ nve32_t osi_dma_ioctl(struct osi_dma_priv_data *osi_dma)
 	data = &osi_dma->ioctl_data;
 
 	switch (data->cmd) {
+#ifdef OSI_DEBUG
 	case OSI_DMA_IOCTL_CMD_REG_DUMP:
 		reg_dump(osi_dma);
 		break;
@@ -1356,6 +1456,10 @@ nve32_t osi_dma_ioctl(struct osi_dma_priv_data *osi_dma)
 	case OSI_DMA_IOCTL_CMD_DEBUG_INTR_CONFIG:
 		l_dma->ops_p->debug_intr_config(osi_dma);
 		break;
+#endif /* OSI_DEBUG */
+	case OSI_DMA_IOCTL_CMD_RX_RIIT_CONFIG:
+		set_rx_riit(osi_dma, data->arg_u32);
+		break;
 	default:
 		OSI_DMA_ERR(osi_dma->osd, OSI_LOG_ARG_INVALID,
 			    "DMA: Invalid IOCTL command", 0ULL);
@@ -1367,7 +1471,6 @@ nve32_t osi_dma_ioctl(struct osi_dma_priv_data *osi_dma)
 #endif /* OSI_CL_FTRACE */
 	return 0;
 }
-#endif /* OSI_DEBUG */
 
 #ifndef OSI_STRIPPED_LIB
 

osi/dma/osi_dma_txrx.c

@@ -194,6 +194,42 @@ static inline void check_for_more_data_avail(struct osi_rx_ring *rx_ring, nve32_
 #ifdef OSI_CL_FTRACE
 nveu32_t osi_process_rx_completions_cnt = 0;
 #endif /* OSI_CL_FTRACE */
+
+/**
+ * @brief compltd_rxdesc_cnt - number of Rx descriptors completed by HW
+ *
+ * @note
+ * Algorithm:
+ *  - This routine will be invoked by OSI layer internally to get the
+ *    available Rx descriptor to process by SW.
+ *
+ * @note
+ * API Group:
+ * - Initialization: No
+ * - Run time: Yes
+ * - De-initialization: No
+ *
+ * @param[in, out] osi_dma: Pointer to OSI DMA private data structure.
+ * @param[in] chan: DMA channel number for which stats should be incremented.
+ */
+static inline nveu32_t compltd_rx_desc_cnt(struct osi_dma_priv_data *osi_dma,
+					    nveu32_t chan)
+{
+	struct osi_rx_ring *rx_ring = osi_dma->rx_ring[chan];
+	nveu32_t value, rx_desc_wr_idx, descr_compltd;
+
+	value = osi_dma_readl((nveu8_t *)osi_dma->base +
+			  MGBE_DMA_CHX_RX_DESC_WR_RNG_OFFSET(chan));
+	/* completed desc write back offset */
+	rx_desc_wr_idx = ((value >> MGBE_RX_DESC_WR_RNG_RWDC_SHIFT ) &
+			  (osi_dma->rx_ring_sz - 1));
+	descr_compltd = (rx_desc_wr_idx - rx_ring->cur_rx_idx) &
+			 (osi_dma->rx_ring_sz - 1U);
+	/* offset/index start from 0, so add 1 to get final count */
+	descr_compltd += 1U;
+	return descr_compltd;
+}
+
 nve32_t osi_process_rx_completions(struct osi_dma_priv_data *osi_dma,
 				   nveu32_t chan, nve32_t budget,
 				   nveu32_t *more_data_avail)
@@ -209,6 +245,7 @@ nve32_t osi_process_rx_completions(struct osi_dma_priv_data *osi_dma,
 	nve32_t received_resv = 0;
 #endif /* !OSI_STRIPPED_LIB */
 	nve32_t ret = 0;
+	nveu32_t rx_desc_compltd;
 
 #ifdef OSI_CL_FTRACE
 	if ((osi_process_rx_completions_cnt % 1000) == 0)
@@ -229,6 +266,11 @@ nve32_t osi_process_rx_completions(struct osi_dma_priv_data *osi_dma,
 	/* Reset flag to indicate if more Rx frames available to OSD layer */
 	*more_data_avail = OSI_NONE;
 
+	if (osi_dma->mac == OSI_MAC_HW_MGBE_T26X) {
+		rx_desc_compltd = compltd_rx_desc_cnt(osi_dma, chan);
+		budget = (budget > ((nve32_t)rx_desc_compltd)? ((nve32_t)rx_desc_compltd): budget);
+	}
+
 	while ((received < budget)
 #ifndef OSI_STRIPPED_LIB
 	       && (received_resv < budget)
@@ -298,9 +340,9 @@ nve32_t osi_process_rx_completions(struct osi_dma_priv_data *osi_dma,
 		process_rx_desc(osi_dma, rx_ring, rx_desc, rx_swcx, rx_pkt_cx, chan, rx_ring_mask);
 
 #ifndef OSI_STRIPPED_LIB
-		osi_dma->dstats.q_rx_pkt_n[chan] =
+		osi_dma->dstats.chan_rx_pkt_n[chan] =
 			dma_update_stats_counter(
-					osi_dma->dstats.q_rx_pkt_n[chan],
+					osi_dma->dstats.chan_rx_pkt_n[chan],
 					1UL);
 		osi_dma->dstats.rx_pkt_n =
 			dma_update_stats_counter(osi_dma->dstats.rx_pkt_n, 1UL);
@@ -341,8 +383,8 @@ fail:
 static inline void inc_tx_pkt_stats(struct osi_dma_priv_data *osi_dma,
 				    nveu32_t chan)
 {
-	osi_dma->dstats.q_tx_pkt_n[chan] =
+	osi_dma->dstats.chan_tx_pkt_n[chan] =
-		dma_update_stats_counter(osi_dma->dstats.q_tx_pkt_n[chan], 1UL);
+		dma_update_stats_counter(osi_dma->dstats.chan_tx_pkt_n[chan], 1UL);
 	osi_dma->dstats.tx_pkt_n =
 		dma_update_stats_counter(osi_dma->dstats.tx_pkt_n, 1UL);
 }
@@ -549,7 +591,7 @@ static inline nve32_t process_last_desc(struct osi_dma_priv_data *osi_dma,
 	/* check for Last Descriptor */
 	if ((tx_desc->tdes3 & TDES3_LD) == TDES3_LD) {
 		if (((tx_desc->tdes3 & TDES3_ES_BITS) != 0U) &&
-		    (osi_dma->mac != OSI_MAC_HW_MGBE)) {
+		    (osi_dma->mac == OSI_MAC_HW_EQOS)) {
 			txdone_pkt_cx->flags |= OSI_TXDONE_CX_ERROR;
 #ifndef OSI_STRIPPED_LIB
 			/* fill packet error stats */
@@ -633,7 +675,7 @@ nve32_t osi_process_tx_completions(struct osi_dma_priv_data *osi_dma,
 		processed = process_last_desc(osi_dma, tx_desc, txdone_pkt_cx, processed);
 #endif
 
-		if (osi_dma->mac != OSI_MAC_HW_MGBE) {
+		if (osi_dma->mac == OSI_MAC_HW_EQOS) {
 			update_tx_done_ts(tx_desc, txdone_pkt_cx);
 		} else if (((tx_swcx->flags & OSI_PKT_CX_PTP) == OSI_PKT_CX_PTP) &&
 			   // if not master in onestep mode
@@ -642,6 +684,9 @@ nve32_t osi_process_tx_completions(struct osi_dma_priv_data *osi_dma,
 			    OSI_ENABLE) &&
 			   ((tx_desc->tdes3 & TDES3_CTXT) == 0U)) {
 			txdone_pkt_cx->pktid = tx_swcx->pktid;
+			if (osi_dma->mac == OSI_MAC_HW_MGBE_T26X) {
+				txdone_pkt_cx->vdmaid = tx_swcx->vdmaid;
+			}
 			txdone_pkt_cx->flags |= OSI_TXDONE_CX_TS_DELAYED;
 		} else {
 			/* Do nothing here */
@@ -1073,6 +1118,7 @@ nve32_t hw_transmit(struct osi_dma_priv_data *osi_dma,
 		    struct osi_tx_ring *tx_ring,
 		    nveu32_t dma_chan)
 {
+	const nveu32_t chan_mask[OSI_MAX_MAC_IP_TYPES] = {0xFU, 0xFU, 0x3FU};
 	struct dma_local *l_dma = (struct dma_local *)(void *)osi_dma;
 	struct osi_tx_pkt_cx *tx_pkt_cx = OSI_NULL;
 	struct osi_tx_desc *first_desc = OSI_NULL;
@@ -1084,7 +1130,7 @@ nve32_t hw_transmit(struct osi_dma_priv_data *osi_dma,
 #ifdef OSI_DEBUG
 	nveu32_t f_idx = tx_ring->cur_tx_idx;
 #endif /* OSI_DEBUG */
-	nveu32_t chan = dma_chan & 0xFU;
+	nveu32_t chan = dma_chan & chan_mask[osi_dma->mac];
 	const nveu32_t tail_ptr_reg[OSI_MAX_MAC_IP_TYPES] = {
 		EQOS_DMA_CHX_TDTP(chan),
 		MGBE_DMA_CHX_TDTLP(chan),
@@ -1092,6 +1138,7 @@ nve32_t hw_transmit(struct osi_dma_priv_data *osi_dma,
 	};
 	nve32_t cntx_desc_consumed;
 	nveu32_t pkt_id = 0x0U;
+	nveu32_t vdma_id = 0x0U;
 	nveu32_t desc_cnt = 0U;
 	nveu64_t tailptr;
 	nveu32_t entry = 0U;
@@ -1140,11 +1187,16 @@ nve32_t hw_transmit(struct osi_dma_priv_data *osi_dma,
 				/* packet ID for Onestep is 0x0 always */
 				pkt_id = OSI_NONE;
 			} else {
-				INC_TX_TS_PKTID(l_dma->pkt_id);
+				if (osi_dma->mac != OSI_MAC_HW_MGBE_T26X) {
 					pkt_id = GET_TX_TS_PKTID(l_dma->pkt_id, chan);
+				} else {
+					pkt_id = GET_TX_TS_PKTID_T264(l_dma->pkt_id);
+					vdma_id = chan;
+					tx_desc->tdes0 = (vdma_id << OSI_PTP_VDMA_SHIFT);
+				}
 			}
 			/* update packet id */
-			tx_desc->tdes0 = pkt_id;
+			tx_desc->tdes0 |= pkt_id;
 		}
 		INCR_TX_DESC_INDEX(entry, osi_dma->tx_ring_sz);
 
@@ -1254,7 +1306,8 @@ fail:
 static nve32_t rx_dma_desc_initialization(const struct osi_dma_priv_data *const osi_dma,
 					  nveu32_t dma_chan)
 {
-	nveu32_t chan = dma_chan & 0xFU;
+	const nveu32_t chan_mask[OSI_MAX_MAC_IP_TYPES] = {0xFU, 0xFU, 0x3FU};
+	nveu32_t chan = dma_chan & chan_mask[osi_dma->mac];
 	const nveu32_t start_addr_high_reg[OSI_MAX_MAC_IP_TYPES] = {
 		EQOS_DMA_CHX_RDLH(chan),
 		MGBE_DMA_CHX_RDLH(chan),
@@ -1399,7 +1452,8 @@ static inline void set_tx_ring_len_and_start_addr(const struct osi_dma_priv_data
 						  nveu32_t dma_chan,
 						  nveu32_t len)
 {
-	nveu32_t chan = dma_chan & 0xFU;
+	const nveu32_t chan_mask[OSI_MAX_MAC_IP_TYPES] = {0xFU, 0xFU, 0x3FU};
+	nveu32_t chan = dma_chan & chan_mask[osi_dma->mac];
 	const nveu32_t ring_len_reg[OSI_MAX_MAC_IP_TYPES] = {
 		EQOS_DMA_CHX_TDRL(chan),
 		MGBE_DMA_CHX_TX_CNTRL2(chan),