nv-tegra-mirror/nvethernetrm
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/kernel/nvethernetrm.git synced 2025-12-22 09:12:10 +03:00
Code Issues Packages Projects Releases Wiki Activity

osi: Add PCS BASE-R FEC setting

Browse Source 
Adding PCS BASE-R FEC setting using on
sysfs node

Bug 4674473

Change-Id: Icdc2300705d11ce2c96e2c8e1663599a3bb4fadd
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3201974
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
This commit is contained in:
Mahesh Patil
2024-08-26 15:55:53 -07:00
committed by mobile promotions
parent cc7aae9570
commit 45f67fb52f
3 changed files with 38 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
include/osi_core.h
View File

@@ -1825,6 +1825,8 @@ struct osi_core_priv_data {
struct rchlist_index rch_index[RCHLIST_SIZE];
/** Parameter indicates the current operating speed */
nve32_t speed;
/** PCS BASE-R FEC enable */
nveu32_t pcs_base_r_fec_en;
};
/**

35
osi/core/xpcs.c
View File

@@ -1025,6 +1025,22 @@ nve32_t xpcs_init(struct osi_core_priv_data *osi_core)
if (ret != 0) {
goto fail;
}
/* Enable BASE-R FEC */
ctrl = xpcs_read(xpcs_base, XPCS_SR_PMA_KR_FEC_CTRL);
if (osi_core->pcs_base_r_fec_en == OSI_ENABLE) {
ctrl |= (XPCS_SR_PMA_KR_FEC_CTRL_FEC_EN |
XPCS_SR_PMA_KR_FEC_CTRL_EN_ERR_IND);
} else {
ctrl &= ~(XPCS_SR_PMA_KR_FEC_CTRL_FEC_EN |
XPCS_SR_PMA_KR_FEC_CTRL_EN_ERR_IND);
}
ret = xpcs_write_safety(osi_core, XPCS_SR_PMA_KR_FEC_CTRL, ctrl);
if (ret != 0) {
goto fail;
}
/* 4. Program PHY to operate at 10Gbps/5Gbps/2Gbps
* this step not required since PHY speed programming
* already done as part of phy INIT
@@ -1050,14 +1066,14 @@ fail:
nve32_t xlgpcs_init(struct osi_core_priv_data *osi_core)
{
#if 0 //FIXME: matching with HW script sequence for 25G
void *xpcs_base = osi_core->xpcs_base;
nveu32_t retry = 1000;
nveu32_t count;
nveu32_t ctrl = 0;
nve32_t cond = COND_NOT_MET;
#endif
void *xpcs_base = osi_core->xpcs_base;
nve32_t ret = 0;
nveu32_t value = 0;
nveu32_t ctrl = 0;
if (osi_core->xpcs_base == OSI_NULL) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
@@ -1156,6 +1172,21 @@ nve32_t xlgpcs_init(struct osi_core_priv_data *osi_core)
}
/* Enable BASE-R FEC */
ctrl = xpcs_read(xpcs_base, XPCS_SR_PMA_KR_FEC_CTRL);
if (osi_core->pcs_base_r_fec_en == OSI_ENABLE) {
ctrl |= (XPCS_SR_PMA_KR_FEC_CTRL_FEC_EN |
XPCS_SR_PMA_KR_FEC_CTRL_EN_ERR_IND);
} else {
ctrl &= ~(XPCS_SR_PMA_KR_FEC_CTRL_FEC_EN |
XPCS_SR_PMA_KR_FEC_CTRL_EN_ERR_IND);
}
ret = xpcs_write_safety(osi_core, XPCS_SR_PMA_KR_FEC_CTRL, ctrl);
if (ret != 0) {
goto fail;
}
/* As a part of bringup debug, below programming is leading to the failures in block lock
* in XFI mode. This programming is not done in the HW scripts, but mentioned as a part of IAS.
* For now commenting it and need to be checked with HW team and enable it when required

5
osi/core/xpcs.h
View File

@@ -39,6 +39,7 @@
#define XPCS_VR_XS_PCS_DIG_CTRL1 0xE0000
#define XPCS_VR_XS_PCS_KR_CTRL 0xE001C
#define XPCS_SR_AN_CTRL 0x1C0000
#define XPCS_SR_PMA_KR_FEC_CTRL 0x402ac
#define XPCS_SR_MII_CTRL 0x7C0000
#define XPCS_SR_MII_STS_0 0x7C0004
#define XPCS_VR_MII_AN_INTR_STS 0x7E0008
@@ -82,7 +83,6 @@
* @{
*/
#define XLGPCS_SR_PMA_CTRL2 0x4001c
#define XLGPCS_SR_PMA_KR_FEC_CTRL 0x402ac
#define XLGPCS_SR_PCS_CTRL1 0xc0000
#define XLGPCS_SR_PCS_STS1 0xc0004
#define XLGPCS_SR_PCS_CTRL2 0xc001c
@@ -113,7 +113,6 @@
#define XLGPCS_SR_PMA_CTRL2_PMA_TYPE_MASK 0x7F
#define XLGPCS_VR_PCS_DIG_CTRL3_CNS_EN OSI_BIT(0)
#define XLGPCS_VR_PCS_DIG_CTRL1_VR_RST OSI_BIT(15)
#define XLGPCS_SR_PMA_KR_FEC_CTRL_FEC_EN OSI_BIT(0)
#define XLGPCS_WRAP_UPHY_TO_CTRL2_EQ_DONE_TOV 0xFFFFU
#define XLGPCS_WRAP_UPHY_RX_CTRL5_RX_EQ_ENABLE 0x80000000U
@@ -210,6 +209,8 @@
#define XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_SW_OVRD OSI_BIT(31)
#define XPCS_WRAP_UPHY_STATUS_TX_P_UP_STATUS OSI_BIT(0)
#define XPCS_WRAP_UPHY_STATUS_RX_P_UP_STATUS OSI_BIT(2)
#define XPCS_SR_PMA_KR_FEC_CTRL_FEC_EN OSI_BIT(0)
#define XPCS_SR_PMA_KR_FEC_CTRL_EN_ERR_IND OSI_BIT(1)
#ifdef HSI_SUPPORT
#define XPCS_WRAP_INTERRUPT_CONTROL 0x8048