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osi: core: combine flush_mtl_tx_queue

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Bug 3701869

Change-Id: Ifea025c0eb2d4373a348283aaa93eb7d0eca193a
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2739121
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Narayan Reddy
2022-07-03 20:08:37 +00:00
committed by Bhadram Varka
parent a19a5a80bd
commit 58b59f709e
7 changed files with 23 additions and 140 deletions
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18
osi/core/core_common.c
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@@ -196,6 +196,24 @@ fail:
}
nve32_t hw_flush_mtl_tx_queue(struct osi_core_priv_data *const osi_core,
const nveu32_t qinx)
{
void *addr = osi_core->base;
nveu32_t tx_op_mode_val = 0U;
nveu32_t value;
const nveu32_t tx_op_mode[2] = { EQOS_MTL_CHX_TX_OP_MODE(qinx),
MGBE_MTL_CHX_TX_OP_MODE(qinx)};
/* Read Tx Q Operating Mode Register and flush TxQ */
value = osi_readla(osi_core, ((nveu8_t *)addr + tx_op_mode[osi_core->mac]));
value |= MTL_QTOMR_FTQ;
osi_writela(osi_core, value, ((nveu8_t *)addr + tx_op_mode[osi_core->mac]));
/* Poll Until FTQ bit resets for Successful Tx Q flush */
return poll_check(osi_core, ((nveu8_t *)addr + tx_op_mode[osi_core->mac]),
MTL_QTOMR_FTQ, &tx_op_mode_val);
}
/**
* @brief hw_est_read - indirect read the GCL to Software own list