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osi: eqos: Increase EQOS_MAX_*_SAFETY_REGS

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Issue: Current array size index for EQOS MTL safety
register storage 4. It created issue when interface
going down/up for Orin EQOS (MTL/DMA queues/channels - 8)
while initializing the safety register structure.

Fix: Increase EQOS_MAX_CORE/DMA_SAFETY_REGS to accommodate
Orin EQOS registers extra registers as well.

Bug 200765067

Change-Id: I79226eadfc0964d5034c685c7c31a7989afaeff7
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2585014
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
This commit is contained in:
Bhadram Varka
2021-08-28 20:33:17 +05:30
committed by mobile promotions
parent e1ffd204f7
commit 64241e1972
2 changed files with 72 additions and 39 deletions
Download Patch File Download Diff File Expand all files Collapse all files

41
osi/core/eqos_core.h
View File

@@ -614,6 +614,9 @@ void update_ehfc_rfa_rfd(nveu32_t rx_fifo, nveu32_t *value);
#define EQOS_MAC_MCR_IDX 0U
#define EQOS_MAC_PFR_IDX 1U
#define EQOS_MAC_HTR0_IDX 2U
#define EQOS_MAC_HTR1_IDX 3U
#define EQOS_MAC_HTR2_IDX 4U
#define EQOS_MAC_HTR3_IDX 5U
#define EQOS_MAC_Q0_TXFC_IDX 6U
#define EQOS_MAC_RQC0R_IDX 7U
#define EQOS_MAC_RQC1R_IDX 8U
@@ -627,24 +630,32 @@ void update_ehfc_rfa_rfd(nveu32_t rx_fifo, nveu32_t *value);
#define EQOS_PAD_AUTO_CAL_CFG_IDX 16U
#define EQOS_MTL_RXQ_DMA_MAP0_IDX 17U
#define EQOS_MTL_CH0_TX_OP_MODE_IDX 18U
#define EQOS_MTL_TXQ0_QW_IDX 22U
#ifndef OSI_STRIPPED_LIB
#define EQOS_MAC_HTR1_IDX 3U
#define EQOS_MAC_HTR2_IDX 4U
#define EQOS_MAC_HTR3_IDX 5U
#define EQOS_MTL_CH1_TX_OP_MODE_IDX 19U
#define EQOS_MTL_CH2_TX_OP_MODE_IDX 20U
#define EQOS_MTL_CH3_TX_OP_MODE_IDX 21U
#define EQOS_MTL_TXQ1_QW_IDX 23U
#define EQOS_MTL_TXQ2_QW_IDX 24U
#define EQOS_MTL_TXQ3_QW_IDX 25U
#define EQOS_MTL_CH1_RX_OP_MODE_IDX 27U
#define EQOS_MTL_CH2_RX_OP_MODE_IDX 28U
#define EQOS_MTL_CH3_RX_OP_MODE_IDX 29U
#endif /* !OSI_STRIPPED_LIB */
#define EQOS_MTL_CH0_RX_OP_MODE_IDX 26U
#define EQOS_DMA_SBUS_IDX 30U
#define EQOS_MAX_CORE_SAFETY_REGS 31U
#define EQOS_MTL_CH4_TX_OP_MODE_IDX 22U
#define EQOS_MTL_CH5_TX_OP_MODE_IDX 23U
#define EQOS_MTL_CH6_TX_OP_MODE_IDX 24U
#define EQOS_MTL_CH7_TX_OP_MODE_IDX 25U
#define EQOS_MTL_TXQ0_QW_IDX 26U
#define EQOS_MTL_TXQ1_QW_IDX 27U
#define EQOS_MTL_TXQ2_QW_IDX 28U
#define EQOS_MTL_TXQ3_QW_IDX 29U
#define EQOS_MTL_TXQ4_QW_IDX 30U
#define EQOS_MTL_TXQ5_QW_IDX 31U
#define EQOS_MTL_TXQ6_QW_IDX 32U
#define EQOS_MTL_TXQ7_QW_IDX 33U
#define EQOS_MTL_CH0_RX_OP_MODE_IDX 34U
#define EQOS_MTL_CH1_RX_OP_MODE_IDX 35U
#define EQOS_MTL_CH2_RX_OP_MODE_IDX 36U
#define EQOS_MTL_CH3_RX_OP_MODE_IDX 37U
#define EQOS_MTL_CH4_RX_OP_MODE_IDX 38U
#define EQOS_MTL_CH5_RX_OP_MODE_IDX 39U
#define EQOS_MTL_CH6_RX_OP_MODE_IDX 40U
#define EQOS_MTL_CH7_RX_OP_MODE_IDX 41U
#define EQOS_MTL_CH8_RX_OP_MODE_IDX 42U
#define EQOS_DMA_SBUS_IDX 43U
#define EQOS_MAX_CORE_SAFETY_REGS 44U
/** @} */
/**

70
osi/dma/eqos_dma.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2018-2021, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -118,32 +118,54 @@
* Using macros instead of enum due to misra error.
*/
#define EQOS_DMA_CH0_CTRL_IDX 0U
#define EQOS_DMA_CH0_TX_CTRL_IDX 4U
#define EQOS_DMA_CH0_RX_CTRL_IDX 8U
#define EQOS_DMA_CH0_RDRL_IDX 16U
#define EQOS_DMA_CH0_TDRL_IDX 12U
#define EQOS_DMA_CH0_INTR_ENA_IDX 20U
#ifndef OSI_STRIPPED_LIB
#define EQOS_DMA_CH1_CTRL_IDX 1U
#define EQOS_DMA_CH2_CTRL_IDX 2U
#define EQOS_DMA_CH3_CTRL_IDX 3U
#define EQOS_DMA_CH1_TX_CTRL_IDX 5U
#define EQOS_DMA_CH2_TX_CTRL_IDX 6U
#define EQOS_DMA_CH3_TX_CTRL_IDX 7U
#define EQOS_DMA_CH1_RX_CTRL_IDX 9U
#define EQOS_DMA_CH2_RX_CTRL_IDX 10U
#define EQOS_DMA_CH3_RX_CTRL_IDX 11U
#define EQOS_DMA_CH1_TDRL_IDX 13U
#define EQOS_DMA_CH2_TDRL_IDX 14U
#define EQOS_DMA_CH3_TDRL_IDX 15U
#define EQOS_DMA_CH1_RDRL_IDX 17U
#define EQOS_DMA_CH2_RDRL_IDX 18U
#define EQOS_DMA_CH3_RDRL_IDX 19U
#define EQOS_DMA_CH1_INTR_ENA_IDX 21U
#define EQOS_DMA_CH2_INTR_ENA_IDX 22U
#define EQOS_DMA_CH3_INTR_ENA_IDX 23U
#endif /* OSI_STRIPPED_LIB */
#define EQOS_MAX_DMA_SAFETY_REGS 24U
#define EQOS_DMA_CH4_CTRL_IDX 4U
#define EQOS_DMA_CH5_CTRL_IDX 5U
#define EQOS_DMA_CH6_CTRL_IDX 6U
#define EQOS_DMA_CH7_CTRL_IDX 7U
#define EQOS_DMA_CH0_TX_CTRL_IDX 8U
#define EQOS_DMA_CH1_TX_CTRL_IDX 9U
#define EQOS_DMA_CH2_TX_CTRL_IDX 10U
#define EQOS_DMA_CH3_TX_CTRL_IDX 11U
#define EQOS_DMA_CH4_TX_CTRL_IDX 12U
#define EQOS_DMA_CH5_TX_CTRL_IDX 13U
#define EQOS_DMA_CH6_TX_CTRL_IDX 14U
#define EQOS_DMA_CH7_TX_CTRL_IDX 15U
#define EQOS_DMA_CH0_RX_CTRL_IDX 16U
#define EQOS_DMA_CH1_RX_CTRL_IDX 17U
#define EQOS_DMA_CH2_RX_CTRL_IDX 18U
#define EQOS_DMA_CH3_RX_CTRL_IDX 19U
#define EQOS_DMA_CH4_RX_CTRL_IDX 20U
#define EQOS_DMA_CH5_RX_CTRL_IDX 21U
#define EQOS_DMA_CH6_RX_CTRL_IDX 22U
#define EQOS_DMA_CH7_RX_CTRL_IDX 23U
#define EQOS_DMA_CH0_TDRL_IDX 24U
#define EQOS_DMA_CH1_TDRL_IDX 25U
#define EQOS_DMA_CH2_TDRL_IDX 26U
#define EQOS_DMA_CH3_TDRL_IDX 27U
#define EQOS_DMA_CH4_TDRL_IDX 28U
#define EQOS_DMA_CH5_TDRL_IDX 29U
#define EQOS_DMA_CH6_TDRL_IDX 30U
#define EQOS_DMA_CH7_TDRL_IDX 31U
#define EQOS_DMA_CH0_RDRL_IDX 32U
#define EQOS_DMA_CH1_RDRL_IDX 33U
#define EQOS_DMA_CH2_RDRL_IDX 34U
#define EQOS_DMA_CH3_RDRL_IDX 35U
#define EQOS_DMA_CH4_RDRL_IDX 36U
#define EQOS_DMA_CH5_RDRL_IDX 37U
#define EQOS_DMA_CH6_RDRL_IDX 38U
#define EQOS_DMA_CH7_RDRL_IDX 39U
#define EQOS_DMA_CH0_INTR_ENA_IDX 40U
#define EQOS_DMA_CH1_INTR_ENA_IDX 41U
#define EQOS_DMA_CH2_INTR_ENA_IDX 42U
#define EQOS_DMA_CH3_INTR_ENA_IDX 43U
#define EQOS_DMA_CH4_INTR_ENA_IDX 44U
#define EQOS_DMA_CH5_INTR_ENA_IDX 45U
#define EQOS_DMA_CH6_INTR_ENA_IDX 46U
#define EQOS_DMA_CH7_INTR_ENA_IDX 47U
#define EQOS_MAX_DMA_SAFETY_REGS 48U
#define EQOS_AXI_BUS_WIDTH 0x10U
/** @} */