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osi: mgbe: Update HSI error for DOS-SHR-6424

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Issue:
For DOS-SHR-6424 SHR reported ID handling
is offloaded to HV. And new error IDs and
attributes are defined. So this needs
to be updated.

Fix:
Deprecate reported ID update on OSI.
And updated OSI error codes based
on the DOS-SHR-6424 SHR.

Bug 4158001

Change-Id: I28561325f921f51560aeb58fce38a0e61ba43c83
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2931112
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Mohan Thadikamalla
2023-06-30 06:14:06 +00:00
committed by Bhadram Varka
parent 3cae855084
commit 795cc66bde
4 changed files with 76 additions and 65 deletions
Download Patch File Download Diff File Expand all files Collapse all files

65
include/osi_core.h
View File

@@ -419,40 +419,35 @@ typedef my_lint_64 nvel64_t;
* @brief software defined error code
* @{
*/
#define OSI_INBOUND_BUS_CRC_ERR 0x1001U
#define OSI_TX_FRAME_ERR 0x1002U
#define OSI_RECEIVE_CHECKSUM_ERR 0x1003U
#define OSI_PCS_AUTONEG_ERR 0x1004U
#define OSI_MACSEC_RX_CRC_ERR 0x1005U
#define OSI_MACSEC_TX_CRC_ERR 0x1006U
#define OSI_MACSEC_RX_ICV_ERR 0x1007U
#define OSI_MACSEC_REG_VIOL_ERR 0x1008U
#define OSI_XPCS_WRITE_FAIL_ERR 0x1009U
#define OSI_PHY_WRITE_VERIFY_ERR 0x100AU
#define OSI_M2M_TSC_READ_ERR 0x100BU
#define OSI_M2M_TIME_CAL_ERR 0x100CU
#define OSI_M2M_ADJ_FREQ_ERR 0x100DU
#define OSI_M2M_ADJ_TIME_ERR 0x100EU
#define OSI_M2M_SET_TIME_ERR 0x100FU
#define OSI_M2M_CONFIG_PTP_ERR 0x1010U
#define OSI_UNCORRECTABLE_ERR 0x1U
#define OSI_CORRECTABLE_ERR 0x2U
#define OSI_INBOUND_BUS_CRC_ERR 0x3U
#define OSI_TX_FRAME_ERR 0x4U
#define OSI_RECEIVE_CHECKSUM_ERR 0x5U
#define OSI_PCS_AUTONEG_ERR 0x6U
#define OSI_MACSEC_RX_CRC_ERR 0x7U
#define OSI_MACSEC_TX_CRC_ERR 0x8U
#define OSI_MACSEC_RX_ICV_ERR 0x9U
#define OSI_MACSEC_REG_VIOL_ERR 0xAU
#define OSI_XPCS_WRITE_FAIL_ERR 0xBU
#define OSI_PHY_WRITE_VERIFY_ERR 0xCU
#define OSI_M2M_TSC_READ_ERR 0xDU
#define OSI_M2M_TIME_CAL_ERR 0xEU
#define OSI_M2M_ADJ_FREQ_ERR 0xFU
#define OSI_M2M_ADJ_TIME_ERR 0x10U
#define OSI_M2M_SET_TIME_ERR 0x11U
#define OSI_M2M_CONFIG_PTP_ERR 0x12U
#define OSI_HSI_MGBE0_UE_CODE 0x2A00U
#define OSI_HSI_MGBE1_UE_CODE 0x2A01U
#define OSI_HSI_MGBE2_UE_CODE 0x2A02U
#define OSI_HSI_MGBE3_UE_CODE 0x2A03U
#define OSI_HSI_EQOS0_UE_CODE 0x28ADU
#define OSI_HSI_MGBE0_CE_CODE 0x2E08U
#define OSI_HSI_MGBE1_CE_CODE 0x2E09U
#define OSI_HSI_MGBE2_CE_CODE 0x2E0AU
#define OSI_HSI_MGBE3_CE_CODE 0x2E0BU
#define OSI_HSI_EQOS0_CE_CODE 0x2DE6U
#define OSI_HSI_MGBE0_REPORTER_ID 0x8019U
#define OSI_HSI_MGBE1_REPORTER_ID 0x801AU
#define OSI_HSI_MGBE2_REPORTER_ID 0x801BU
#define OSI_HSI_MGBE3_REPORTER_ID 0x801CU
#define OSI_HSI_EQOS0_REPORTER_ID 0x8009U
#define OSI_EQOS_UNCORRECTABLE_ATTR 0x109
#define OSI_EQOS_CORRECTABLE_ATTR 0x309
#define OSI_MGBE0_UNCORRECTABLE_ATTR 0x119
#define OSI_MGBE0_CORRECTABLE_ATTR 0x319
#define OSI_MGBE1_UNCORRECTABLE_ATTR 0x11A
#define OSI_MGBE1_CORRECTABLE_ATTR 0x31A
#define OSI_MGBE2_UNCORRECTABLE_ATTR 0x11B
#define OSI_MGBE2_CORRECTABLE_ATTR 0x31B
#define OSI_MGBE3_UNCORRECTABLE_ATTR 0x11C
#define OSI_MGBE3_CORRECTABLE_ATTR 0x31C
/** @} */
#endif
@@ -1230,12 +1225,16 @@ struct osi_hsi_data {
nveu16_t reporter_id;
/** HSI error codes */
nveu32_t err_code[OSI_HSI_MAX_MAC_ERROR_CODE];
/** HSI error attribute */
nveu32_t err_attr[OSI_HSI_MAX_MAC_ERROR_CODE];
/** HSI MAC report count threshold based error */
nveu32_t report_count_err[OSI_HSI_MAX_MAC_ERROR_CODE];
/** Indicates if error reporting to FSI is pending */
nveu32_t report_err;
/** HSI MACSEC error codes */
nveu32_t macsec_err_code[HSI_MAX_MACSEC_ERROR_CODE];
/** HSI MACSEC error attribute */
nveu32_t macsec_err_attr[HSI_MAX_MACSEC_ERROR_CODE];
/** HSI MACSEC report error based on count threshold */
nveu32_t macsec_report_count_err[HSI_MAX_MACSEC_ERROR_CODE];
/** Indicates if error report to FSI is pending for MACSEC*/

9
osi/core/eqos_core.c
View File

@@ -728,7 +728,6 @@ static nve32_t eqos_hsi_configure(struct osi_core_priv_data *const osi_core,
if (enable == OSI_ENABLE) {
osi_core->hsi.enabled = OSI_ENABLE;
osi_core->hsi.reporter_id = OSI_HSI_EQOS0_REPORTER_ID;
/* T23X-EQOS_HSIv2-19: Enabling of Consistency Monitor for TX Frame Errors */
value = osi_readla(osi_core,
@@ -869,12 +868,12 @@ static nve32_t eqos_hsi_inject_err(struct osi_core_priv_data *const osi_core,
nve32_t ret = 0;
switch (error_code) {
case OSI_HSI_EQOS0_CE_CODE:
case OSI_CORRECTABLE_ERR:
value = (EQOS_MTL_DBG_CTL_EIEC | EQOS_MTL_DBG_CTL_EIEE);
osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
EQOS_MTL_DBG_CTL);
break;
case OSI_HSI_EQOS0_UE_CODE:
case OSI_UNCORRECTABLE_ERR:
value = EQOS_MTL_DPP_ECC_EIC_BLEI;
osi_writela(osi_core, value, (nveu8_t *)osi_core->base +
EQOS_MTL_DPP_ECC_EIC);
@@ -1682,7 +1681,7 @@ static void eqos_handle_hsi_intr(struct osi_core_priv_data *const osi_core)
EQOS_WRAP_COMMON_INTR_STATUS);
if (((val & EQOS_REGISTER_PARITY_ERR) == EQOS_REGISTER_PARITY_ERR) ||
((val & EQOS_CORE_UNCORRECTABLE_ERR) == EQOS_CORE_UNCORRECTABLE_ERR)) {
osi_core->hsi.err_code[UE_IDX] = OSI_HSI_EQOS0_UE_CODE;
osi_core->hsi.err_code[UE_IDX] = OSI_UNCORRECTABLE_ERR;
osi_core->hsi.report_err = OSI_ENABLE;
osi_core->hsi.report_count_err[UE_IDX] = OSI_ENABLE;
/* Disable the interrupt */
@@ -1694,7 +1693,7 @@ static void eqos_handle_hsi_intr(struct osi_core_priv_data *const osi_core)
EQOS_WRAP_COMMON_INTR_ENABLE);
}
if ((val & EQOS_CORE_CORRECTABLE_ERR) == EQOS_CORE_CORRECTABLE_ERR) {
osi_core->hsi.err_code[CE_IDX] = OSI_HSI_EQOS0_CE_CODE;
osi_core->hsi.err_code[CE_IDX] = OSI_CORRECTABLE_ERR;
osi_core->hsi.report_err = OSI_ENABLE;
osi_core->hsi.ce_count =
osi_update_stats_counter(osi_core->hsi.ce_count, 1UL);

33
osi/core/mgbe_core.c
View File

@@ -1517,16 +1517,9 @@ static nve32_t mgbe_hsi_configure(struct osi_core_priv_data *const osi_core,
{
nveu32_t value = 0U;
nve32_t ret = 0;
const nveu16_t osi_hsi_reporter_id[] = {
OSI_HSI_MGBE0_REPORTER_ID,
OSI_HSI_MGBE1_REPORTER_ID,
OSI_HSI_MGBE2_REPORTER_ID,
OSI_HSI_MGBE3_REPORTER_ID,
};
if (enable == OSI_ENABLE) {
osi_core->hsi.enabled = OSI_ENABLE;
osi_core->hsi.reporter_id = osi_hsi_reporter_id[osi_core->instance_id];
/* T23X-MGBE_HSIv2-12:Initialization of Transaction Timeout in PCS */
/* T23X-MGBE_HSIv2-11:Initialization of Watchdog Timer */
@@ -1705,17 +1698,11 @@ static nve32_t mgbe_hsi_inject_err(struct osi_core_priv_data *const osi_core,
nve32_t ret = 0;
switch (error_code) {
case OSI_HSI_MGBE0_CE_CODE:
case OSI_HSI_MGBE1_CE_CODE:
case OSI_HSI_MGBE2_CE_CODE:
case OSI_HSI_MGBE3_CE_CODE:
case OSI_CORRECTABLE_ERR:
osi_writela(osi_core, val_ce, (nveu8_t *)osi_core->base +
MGBE_MTL_DEBUG_CONTROL);
break;
case OSI_HSI_MGBE0_UE_CODE:
case OSI_HSI_MGBE1_UE_CODE:
case OSI_HSI_MGBE2_UE_CODE:
case OSI_HSI_MGBE3_UE_CODE:
case OSI_UNCORRECTABLE_ERR:
osi_writela(osi_core, val_ue, (nveu8_t *)osi_core->base +
MGBE_MTL_DEBUG_CONTROL);
break;
@@ -2913,19 +2900,12 @@ static void mgbe_handle_hsi_intr(struct osi_core_priv_data *osi_core)
nveu32_t val2 = 0;
void *xpcs_base = osi_core->xpcs_base;
nveu64_t ce_count_threshold;
const nveu32_t osi_hsi_err_code[][2] = {
{OSI_HSI_MGBE0_UE_CODE, OSI_HSI_MGBE0_CE_CODE},
{OSI_HSI_MGBE1_UE_CODE, OSI_HSI_MGBE1_CE_CODE},
{OSI_HSI_MGBE2_UE_CODE, OSI_HSI_MGBE2_CE_CODE},
{OSI_HSI_MGBE3_UE_CODE, OSI_HSI_MGBE3_CE_CODE},
};
val = osi_readla(osi_core, (nveu8_t *)osi_core->base +
MGBE_WRAP_COMMON_INTR_STATUS);
if (((val & MGBE_REGISTER_PARITY_ERR) == MGBE_REGISTER_PARITY_ERR) ||
((val & MGBE_CORE_UNCORRECTABLE_ERR) == MGBE_CORE_UNCORRECTABLE_ERR)) {
osi_core->hsi.err_code[UE_IDX] =
osi_hsi_err_code[osi_core->instance_id][UE_IDX];
osi_core->hsi.err_code[UE_IDX] = OSI_UNCORRECTABLE_ERR;
osi_core->hsi.report_err = OSI_ENABLE;
osi_core->hsi.report_count_err[UE_IDX] = OSI_ENABLE;
/* Disable the interrupt */
@@ -2937,8 +2917,7 @@ static void mgbe_handle_hsi_intr(struct osi_core_priv_data *osi_core)
MGBE_WRAP_COMMON_INTR_ENABLE);
}
if ((val & MGBE_CORE_CORRECTABLE_ERR) == MGBE_CORE_CORRECTABLE_ERR) {
osi_core->hsi.err_code[CE_IDX] =
osi_hsi_err_code[osi_core->instance_id][CE_IDX];
osi_core->hsi.err_code[CE_IDX] = OSI_CORRECTABLE_ERR;
osi_core->hsi.report_err = OSI_ENABLE;
osi_core->hsi.ce_count =
osi_update_stats_counter(osi_core->hsi.ce_count, 1UL);
@@ -2977,7 +2956,7 @@ static void mgbe_handle_hsi_intr(struct osi_core_priv_data *osi_core)
XPCS_WRAP_INTERRUPT_STATUS);
if (((val & XPCS_CORE_UNCORRECTABLE_ERR) == XPCS_CORE_UNCORRECTABLE_ERR) ||
((val & XPCS_REGISTER_PARITY_ERR) == XPCS_REGISTER_PARITY_ERR)) {
osi_core->hsi.err_code[UE_IDX] = osi_hsi_err_code[osi_core->instance_id][UE_IDX];
osi_core->hsi.err_code[UE_IDX] = OSI_UNCORRECTABLE_ERR;
osi_core->hsi.report_err = OSI_ENABLE;
osi_core->hsi.report_count_err[UE_IDX] = OSI_ENABLE;
/* Disable uncorrectable interrupts */
@@ -2989,7 +2968,7 @@ static void mgbe_handle_hsi_intr(struct osi_core_priv_data *osi_core)
XPCS_WRAP_INTERRUPT_CONTROL);
}
if ((val & XPCS_CORE_CORRECTABLE_ERR) == XPCS_CORE_CORRECTABLE_ERR) {
osi_core->hsi.err_code[CE_IDX] = osi_hsi_err_code[osi_core->instance_id][CE_IDX];
osi_core->hsi.err_code[CE_IDX] = OSI_CORRECTABLE_ERR;
osi_core->hsi.report_err = OSI_ENABLE;
osi_core->hsi.ce_count =
osi_update_stats_counter(osi_core->hsi.ce_count, 1UL);

34
osi/core/osi_hal.c
View File

@@ -524,6 +524,16 @@ static nve32_t osi_hal_hw_core_init(struct osi_core_priv_data *const osi_core)
struct core_local *l_core = (struct core_local *)(void *)osi_core;
const nveu32_t ptp_ref_clk_rate[3] = {EQOS_X_PTP_CLK_SPEED, EQOS_PTP_CLK_SPEED,
MGBE_PTP_CLK_SPEED};
#ifdef HSI_SUPPORT
const nveu32_t error_attr[5][2] = {
{OSI_EQOS_UNCORRECTABLE_ATTR, OSI_EQOS_CORRECTABLE_ATTR},
{OSI_MGBE0_UNCORRECTABLE_ATTR, OSI_MGBE0_CORRECTABLE_ATTR},
{OSI_MGBE1_UNCORRECTABLE_ATTR, OSI_MGBE1_CORRECTABLE_ATTR},
{OSI_MGBE2_UNCORRECTABLE_ATTR, OSI_MGBE2_CORRECTABLE_ATTR},
{OSI_MGBE3_UNCORRECTABLE_ATTR, OSI_MGBE3_CORRECTABLE_ATTR}};
nveu32_t i = 0U;
nveu32_t instance = 0U;
#endif
nve32_t ret;
ret = osi_get_mac_version(osi_core, &osi_core->mac_ver);
@@ -580,6 +590,30 @@ static nve32_t osi_hal_hw_core_init(struct osi_core_priv_data *const osi_core)
/* Start the MAC */
hw_start_mac(osi_core);
#ifdef HSI_SUPPORT
if (osi_core->mac == OSI_MAC_HW_MGBE) {
/* Update MGBE instance */
instance = osi_core->instance_id + 1U;
} else {
/* Update EQOS instance */
instance = OSI_MAC_HW_EQOS;
}
/* Fill HSI error attribute values */
for (i = 0; i < OSI_HSI_MAX_MAC_ERROR_CODE; i++) {
if (i == CE_IDX) {
osi_core->hsi.err_attr[i] =
error_attr[instance][CE_IDX];
} else {
osi_core->hsi.err_attr[i] =
error_attr[instance][UE_IDX];
}
}
for (i = 0; i < HSI_MAX_MACSEC_ERROR_CODE; i++) {
osi_core->hsi.macsec_err_attr[i] =
error_attr[instance][UE_IDX];
}
#endif
l_core->lane_status = OSI_ENABLE;
l_core->hw_init_successful = OSI_ENABLE;