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osi: core: common: update HADV value

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Issue: HADV values were not correct
Fix: HW suggested new HADV values.
program same based on speed.

Bug 4787164
Bug 4310565

Change-Id: Ic659967e0e342c1b52de1ca067af900eaebf8e86
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3303958
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Rakesh Goyal
2025-02-17 05:43:29 +00:00
committed by mobile promotions
parent 5ef244ecca
commit 82e1005aec
2 changed files with 66 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

42
osi/core/core_common.c
View File

@@ -1435,14 +1435,49 @@ done:
return ret; return ret;
} }
static nveu32_t speed_index(nve32_t speed)
{
nveu32_t ret;
switch (speed) {
case OSI_SPEED_10:
ret = OSI_SPEED_10_INX;
break;
case OSI_SPEED_100:
ret = OSI_SPEED_100_INX;
break;
case OSI_SPEED_1000:
ret = OSI_SPEED_1000_INX;
break;
case OSI_SPEED_2500:
ret = OSI_SPEED_2500_INX;
break;
case OSI_SPEED_5000:
ret = OSI_SPEED_5000_INX;
break;
case OSI_SPEED_10000:
ret = OSI_SPEED_10000_INX;
break;
case OSI_SPEED_25000:
ret = OSI_SPEED_25000_INX;
break;
default:
ret = OSI_SPEED_10000_INX;
break;
}
return ret;
}
static nve32_t hw_config_fpe_pec_enable(struct osi_core_priv_data *const osi_core, static nve32_t hw_config_fpe_pec_enable(struct osi_core_priv_data *const osi_core,
struct osi_fpe_config *const fpe) struct osi_fpe_config *const fpe)
{ {
nveu32_t i = 0U; nveu32_t i = 0U;
nveu32_t index = 0;
nveu32_t val = 0U; nveu32_t val = 0U;
nveu32_t temp = 0U, temp1 = 0U; nveu32_t temp = 0U, temp1 = 0U;
nveu32_t temp_shift = 0U; nveu32_t temp_shift = 0U;
nve32_t ret = 0; nve32_t ret = 0;
const nveu32_t MTL_FPE_CTS[OSI_MAX_MAC_IP_TYPES] = {EQOS_MTL_FPE_CTS, const nveu32_t MTL_FPE_CTS[OSI_MAX_MAC_IP_TYPES] = {EQOS_MTL_FPE_CTS,
MGBE_MTL_FPE_CTS, MGBE_MTL_FPE_CTS,
MGBE_MTL_FPE_CTS}; MGBE_MTL_FPE_CTS};
@@ -1464,6 +1499,9 @@ static nve32_t hw_config_fpe_pec_enable(struct osi_core_priv_data *const osi_cor
const nveu32_t MTL_FPE_ADV[OSI_MAX_MAC_IP_TYPES] = {EQOS_MTL_FPE_ADV, const nveu32_t MTL_FPE_ADV[OSI_MAX_MAC_IP_TYPES] = {EQOS_MTL_FPE_ADV,
MGBE_MTL_FPE_ADV, MGBE_MTL_FPE_ADV,
MGBE_MTL_FPE_ADV}; MGBE_MTL_FPE_ADV};
const nveu32_t MTL_FPE_HADV_VAL[OSI_SPEED_MAX_INX] = {FPE_1G_HADV, FPE_1G_HADV,
FPE_1G_HADV, FPE_10G_HADV, FPE_10G_HADV,
FPE_10G_HADV, FPE_25G_HADV};
val = osi_readla(osi_core, (nveu8_t *)osi_core->base + MTL_FPE_CTS[osi_core->mac]); val = osi_readla(osi_core, (nveu8_t *)osi_core->base + MTL_FPE_CTS[osi_core->mac]);
val &= ~MTL_FPE_CTS_PEC; val &= ~MTL_FPE_CTS_PEC;
@@ -1513,8 +1551,8 @@ static nve32_t hw_config_fpe_pec_enable(struct osi_core_priv_data *const osi_cor
val = osi_readla(osi_core, (nveu8_t *)osi_core->base + (MTL_FPE_ADV[osi_core->mac])); val = osi_readla(osi_core, (nveu8_t *)osi_core->base + (MTL_FPE_ADV[osi_core->mac]));
val &= ~MTL_FPE_ADV_HADV_MASK; val &= ~MTL_FPE_ADV_HADV_MASK;
//(minimum_fragment_size +IPG/EIPG + Preamble) *.8 ~98ns for10G index = speed_index(osi_core->speed);
val |= MTL_FPE_ADV_HADV_VAL; val |= MTL_FPE_HADV_VAL[index];
osi_writela(osi_core, val, (nveu8_t *)osi_core->base + (MTL_FPE_ADV[osi_core->mac])); osi_writela(osi_core, val, (nveu8_t *)osi_core->base + (MTL_FPE_ADV[osi_core->mac]));
if (osi_core->mac == OSI_MAC_HW_MGBE) { if (osi_core->mac == OSI_MAC_HW_MGBE) {

26
osi/core/core_common.h
View File

@@ -129,6 +129,32 @@
#define MAC_RX_FLW_CTRL 0x0090 #define MAC_RX_FLW_CTRL 0x0090
#define MAC_RX_FLW_CTRL_RFE OSI_BIT(0) #define MAC_RX_FLW_CTRL_RFE OSI_BIT(0)
/**
* @addtogroup FPE HADV register value
*
* @brief Defines the supported speeds
* and the corresponding HADV value for
* hardware according to the ASIC recommendations.
* The HADV value is a speed-dependent parameter.
* The speed index is used to map the HADV
* for hardware during initialization.
*
* @{
*/
#define OSI_SPEED_10_INX 0U
#define OSI_SPEED_100_INX 1U
#define OSI_SPEED_1000_INX 2U
#define OSI_SPEED_2500_INX 3U
#define OSI_SPEED_5000_INX 4U
#define OSI_SPEED_10000_INX 5U
#define OSI_SPEED_25000_INX 6U
#define OSI_SPEED_MAX_INX 7U
#define FPE_1G_HADV 0x380U
#define FPE_10G_HADV 0x59U
#define FPE_25G_HADV 0x23U
/** @} */
#ifdef HSI_SUPPORT #ifdef HSI_SUPPORT
/** /**
* @addtogroup MMC HW register offsets * @addtogroup MMC HW register offsets