osi: add support for pps train in digital mode

Issue: Support for PPS train requested Fix: Added support for PPS train Bug 4585654 Bug 5042311 Change-Id: I0f94b8b4a5cb72d0084ae7ac14e1843930f6a1e8 Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3215524 Reviewed-by: svcacv <svcacv@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com> Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
2025-12-22 09:12:10 +03:00 · 2024-09-20 04:36:22 +00:00
parent 98f1e40481
commit 877664c2ec
7 changed files with 161 additions and 21 deletions
--- a/include/osi_common.h
+++ b/include/osi_common.h
@@ -51,6 +51,8 @@
 #define OSI_LOCKED		0x1U
 /** @brief Number of Nano seconds per second */
 #define OSI_NSEC_PER_SEC	1000000000ULL
+#define OSI_NSEC_PER_SEC_U	1000000000U
+
 #define OSI_MGBE_MAX_RX_RIIT_NSEC	17500U
 #define OSI_MGBE_MIN_RX_RIIT_NSEC	535U
 #ifndef OSI_STRIPPED_LIB
@@ -431,4 +433,21 @@ static inline nveu32_t osi_valid_pbl_value(nveu32_t pbl_value)

 	return allowed_pbl;
 }
+
+/**
+ * @addtogroup PTP PPS related information
+ *
+ * @brief PPS frequency configuration
+ * @{
+ */
+/** Max PPS pulse supported */
+#define OSI_MAX_PPS_HZ		8U
+/** PPS_CMD Trigger delay 100 ms*/
+#define OSI_PPS_TRIG_DELAY	100000000U
+/** PPS train stop immediately */
+#define OSI_PPS_START_CMD	2U
+/** PPS train start after trigger time */
+#define OSI_PPS_STOP_CMD	5U
+/** @} */
+
 #endif /* OSI_COMMON_H */
--- a/osi/core/core_common.c
+++ b/osi/core/core_common.c
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: LicenseRef-NvidiaProprietary
-/* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION. All rights reserved.
+/* SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -58,7 +58,6 @@ fail:
 	return ret;
 }

-
 nve32_t hw_poll_for_swr(struct osi_core_priv_data *const osi_core)
 {
 	nveu32_t dma_mode_val = 0U;
@@ -523,6 +522,123 @@ fail:
 	return ret;
 }

+void hw_config_pps(struct osi_core_priv_data *const osi_core)
+{
+	const nveu32_t mac_pps_tt_nsec[OSI_MAX_MAC_IP_TYPES] = {
+		EQOS_MAC_PPS_TT_NSEC,
+		MGBE_MAC_PPS_TT_NSEC,
+		MGBE_MAC_PPS_TT_NSEC
+	};
+	const nveu32_t mac_pps_tt_sec[OSI_MAX_MAC_IP_TYPES] = {
+		EQOS_MAC_PPS_TT_SEC,
+		MGBE_MAC_PPS_TT_SEC,
+		MGBE_MAC_PPS_TT_SEC
+	};
+	const nveu32_t mac_pps_interval[OSI_MAX_MAC_IP_TYPES] = {
+		EQOS_MAC_PPS_INTERVAL,
+		MGBE_MAC_PPS_INTERVAL,
+		MGBE_MAC_PPS_INTERVAL
+	};
+	const nveu32_t mac_pps_width[OSI_MAX_MAC_IP_TYPES] = {
+		EQOS_MAC_PPS_WIDTH,
+		MGBE_MAC_PPS_WIDTH,
+		MGBE_MAC_PPS_WIDTH
+	};
+	const nveu32_t mac_pps[OSI_MAX_MAC_IP_TYPES] = {
+		EQOS_MAC_PPS_CTL,
+		MGBE_MAC_PPS_CTL,
+		MGBE_MAC_PPS_CTL
+	};
+	void *addr = osi_core->base;
+	struct core_local *l_core = (struct core_local *)(void *)osi_core;
+	nveul64_t temp = 0U;
+	nveu32_t value = 0x0U;
+	nveu32_t interval = 0U;
+	nveu32_t width = 0U;
+	nveu32_t sec = 0U;
+	nveu32_t nsec = 0U;
+	nveu32_t ssinc_val = OSI_PTP_SSINC_4;
+	nve32_t ret = 0;
+
+
+	if (l_core->pps_freq > OSI_ENABLE) { // PPS_CMD related code
+		if (osi_core->mac_ver == OSI_EQOS_MAC_5_30) {
+			ssinc_val = OSI_PTP_SSINC_6;
+		}
+
+		value = osi_readla(osi_core, (nveu8_t *)addr + mac_pps[osi_core->mac]);
+		value &= ~MAC_PPS_CTL_PPSCTRL0;
+		value |= MAC_PPS_CTL_PPSEN0; //set enable bit
+		/* Set mode to 0b'10 for with interrupt, 0b'11 for non interrupt */
+		value |= MAC_PPS_CTL_PPS_TRGTMODSEL0;
+		/* If want to stop all ready running the pps train we need to write b'0101
+		 * in mac_pps[osi_core->mac])
+		 */
+		value |= OSI_PPS_STOP_CMD;
+		osi_writela(osi_core, value, ((nveu8_t *)addr + mac_pps[osi_core->mac]));
+
+		/*
+		 * nvidia,pps_op_ctl  = 0  – 1Hz (pps fixed mode)
+		 * nvidia,pps_op_ctl  = 1  – 1Hz (pps fixed mode, 2 Edges)
+		 * nvidia,pps_op_ctl  = x – x Hz ( pps CMD by programming width and interval)
+		 */
+		temp = OSI_NSEC_PER_SEC / ((nveul64_t)l_core->pps_freq * (nveul64_t)ssinc_val);
+		if (temp <= UINT_MAX) {
+			interval = (nveu32_t)temp;
+			width = (interval / 2U);
+		}
+		/* Target time programming */
+		ret = poll_check(osi_core, ((nveu8_t *)addr + mac_pps_tt_nsec[osi_core->mac]),
+				 MAC_PPS_TT_NSEC_TRG_BUSY, &value);
+		if (ret < 0) {
+			OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
+				     "Not able to program PPS trigger time\n", (nveul64_t)value);
+			goto error;
+		}
+
+		core_get_systime_from_mac(osi_core->base, osi_core->mac, &sec, &nsec);
+
+		if ((OSI_NSEC_PER_SEC_U - 100000000U) > nsec) {
+			nsec += 100000000U; //Trigger PPS train after 100ms
+		} else if (sec < UINT_MAX) {
+			sec += 1U;
+			nsec = nsec - OSI_NSEC_PER_SEC_U + OSI_PPS_TRIG_DELAY;
+		} else {
+			/* Do nothing */
+		}
+		osi_writela(osi_core, sec, ((nveu8_t *)addr + mac_pps_tt_sec[osi_core->mac]));
+		osi_writela(osi_core, nsec, ((nveu8_t *)addr + mac_pps_tt_nsec[osi_core->mac]));
+
+		/* interval programming */
+		if (interval >= 1U) {
+			osi_writela(osi_core, (interval - 1U),
+				    ((nveu8_t *)addr + mac_pps_interval[osi_core->mac]));
+		}
+		/* width programming */
+		if (width >= 1U) {
+			osi_writela(osi_core, (width - 1U),
+				    ((nveu8_t *)addr + mac_pps_width[osi_core->mac]));
+		}
+	}
+
+error:
+	value = osi_readla(osi_core, (nveu8_t *)addr + mac_pps[osi_core->mac]);
+	value &= ~MAC_PPS_CTL_PPSCTRL0;
+	if (ret < 0) {
+		value &= ~MAC_PPS_CTL_PPSEN0;
+	} else if (l_core->pps_freq == OSI_ENABLE) {
+		value &= ~MAC_PPS_CTL_PPSEN0;
+		value |= OSI_ENABLE;//Fixed PPS
+	} else if (l_core->pps_freq > OSI_ENABLE) {
+		value |= OSI_PPS_START_CMD; //0b'10 start after TT. PPS_CMD
+	} else {
+		value &= ~MAC_PPS_CTL_PPSEN0;
+	}
+	osi_writela(osi_core, value, ((nveu8_t *)addr + mac_pps[osi_core->mac]));
+
+	return;
+}
+
 #ifndef OSI_STRIPPED_LIB
 void hw_config_tscr(struct osi_core_priv_data *const osi_core, const nveu32_t ptp_filter)
 #else
@@ -530,22 +646,16 @@ void hw_config_tscr(struct osi_core_priv_data *const osi_core, OSI_UNUSED const
 #endif /* !OSI_STRIPPED_LIB */
 {
 	void *addr = osi_core->base;
-	struct core_local *l_core = (struct core_local *)(void *)osi_core;
 	nveu32_t mac_tcr = 0U;
 #ifndef OSI_STRIPPED_LIB
 	nveu32_t i = 0U, temp = 0U;
 #endif /* !OSI_STRIPPED_LIB */
-	nveu32_t value = 0x0U;
+
 	const nveu32_t mac_tscr[OSI_MAX_MAC_IP_TYPES] = {
 		EQOS_MAC_TCR,
 		MGBE_MAC_TCR,
 		MGBE_MAC_TCR
 	};
-	const nveu32_t mac_pps[OSI_MAX_MAC_IP_TYPES] = {
-		EQOS_MAC_PPS_CTL,
-		MGBE_MAC_PPS_CTL,
-		MGBE_MAC_PPS_CTL
-	};

 	(void)ptp_filter; // unused

@@ -609,12 +719,7 @@ void hw_config_tscr(struct osi_core_priv_data *const osi_core, OSI_UNUSED const

 	osi_writela(osi_core, mac_tcr, ((nveu8_t *)addr + mac_tscr[osi_core->mac]));

-	value = osi_readla(osi_core, (nveu8_t *)addr + mac_pps[osi_core->mac]);
-	value &= ~MAC_PPS_CTL_PPSCTRL0;
-	if (l_core->pps_freq == OSI_ENABLE) {
-		value |= OSI_ENABLE;
-	}
-	osi_writela(osi_core, value, ((nveu8_t *)addr + mac_pps[osi_core->mac]));
+	return;
 }

 void hw_config_ssir(struct osi_core_priv_data *const osi_core)
--- a/osi/core/core_common.h
+++ b/osi/core/core_common.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: LicenseRef-NvidiaProprietary
- * SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION & AFFILIATES.
+ * SPDX-FileCopyrightText: Copyright (c) 2022-2025 NVIDIA CORPORATION & AFFILIATES.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -76,6 +76,9 @@
 #define MAC_TCR_TSADDREG		OSI_BIT(5)
 #define MAC_PPS_CTL_PPSCTRL0		(OSI_BIT(3) | OSI_BIT(2) |\
 					OSI_BIT(1) | OSI_BIT(0))
+#define MAC_PPS_CTL_PPSEN0		OSI_BIT(4)
+#define MAC_PPS_CTL_PPS_TRGTMODSEL0	(OSI_BIT(6) | OSI_BIT(5))
+#define MAC_PPS_TT_NSEC_TRG_BUSY	OSI_BIT(31)
 #define MAC_SSIR_SSINC_SHIFT		16U
 #define MAC_PFR_DAIF			OSI_BIT(3)
 #define MAC_PFR_DBF			OSI_BIT(5)
@@ -180,6 +183,7 @@ nve32_t hw_set_systime_to_mac(struct osi_core_priv_data *const osi_core,
 nve32_t hw_config_addend(struct osi_core_priv_data *const osi_core,
 			 const nveu32_t addend);
 void hw_config_tscr(struct osi_core_priv_data *const osi_core, const nveu32_t ptp_filter);
+void hw_config_pps(struct osi_core_priv_data *const osi_core);
 void hw_config_ssir(struct osi_core_priv_data *const osi_core);
 nve32_t hw_ptp_tsc_capture(struct osi_core_priv_data *const osi_core,
 			   struct osi_core_ptp_tsc_data *data);
--- a/osi/core/eqos_core.h
+++ b/osi/core/eqos_core.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: LicenseRef-NvidiaProprietary
- * SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION. All rights reserved.
+ * SPDX-FileCopyrightText: Copyright (c) 2018-2025 NVIDIA CORPORATION. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -287,6 +287,10 @@
 #define EQOS_MAC_STNSUR			0x0B14
 #define EQOS_MAC_TAR			0x0B18
 #define EQOS_MAC_PPS_CTL		0x0B70
+#define EQOS_MAC_PPS_TT_SEC		0x0B80
+#define EQOS_MAC_PPS_TT_NSEC		0x0B84
+#define EQOS_MAC_PPS_INTERVAL		0x0B88
+#define EQOS_MAC_PPS_WIDTH		0x0B8C
 #define EQOS_DMA_BMR			0x1000
 #define EQOS_DMA_SBUS			0x1004
 #define EQOS_DMA_ISR			0x1008
--- a/osi/core/mgbe_core.h
+++ b/osi/core/mgbe_core.h
@@ -1,5 +1,5 @@
 /* SPDX-License-Identifier: LicenseRef-NvidiaProprietary
- * SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES.
+ * SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -402,6 +402,10 @@
 #define MGBE_MAC_TSSEC			0x0D34
 #define MGBE_MAC_TSPKID			0x0D38
 #define MGBE_MAC_PPS_CTL		0x0D70
+#define MGBE_MAC_PPS_TT_SEC		0x0D80
+#define MGBE_MAC_PPS_TT_NSEC		0x0D84
+#define MGBE_MAC_PPS_INTERVAL		0x0D88
+#define MGBE_MAC_PPS_WIDTH		0x0D8C
 /** @} */

 /**
--- a/osi/core/osi_core.c
+++ b/osi/core/osi_core.c
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: LicenseRef-NvidiaProprietary
-/* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION & AFFILIATES.
+/* SPDX-FileCopyrightText: Copyright (c) 2018-2025 NVIDIA CORPORATION & AFFILIATES.
 * All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
@@ -212,7 +212,7 @@ nve32_t osi_init_core_ops(struct osi_core_priv_data *const osi_core)
 		l_core->m2m_tsync = OSI_DISABLE;
 	}

-	if (osi_core->pps_frq <= OSI_ENABLE) {
+	if (osi_core->pps_frq <= OSI_MAX_PPS_HZ) {
 		l_core->pps_freq = osi_core->pps_frq;
 	} else {
 		OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID,
--- a/osi/core/osi_hal.c
+++ b/osi/core/osi_hal.c
@@ -1,5 +1,5 @@
 // SPDX-License-Identifier: LicenseRef-NvidiaProprietary
-/* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION. All rights reserved.
+/* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION. All rights reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
@@ -512,6 +512,8 @@ static nve32_t osi_ptp_configuration(struct osi_core_priv_data *const osi_core,
 #ifndef OSI_STRIPPED_LIB
 	}
 #endif /* !OSI_STRIPPED_LIB */
+
+	hw_config_pps(osi_core);
 fail:
 	return ret;
 }
@@ -2512,6 +2514,7 @@ static nve32_t handle_set_systohw_time_ioctl(struct osi_core_priv_data *osi_core
 		}
 	}

+	hw_config_pps(osi_core);
 exit:
 	return ret;
 }
@@ -2638,6 +2641,7 @@ static nve32_t handle_adjust_time_ioctl(struct osi_core_priv_data *osi_core,

 	ret = handle_time_ether_m2m_role(osi_core);

+	hw_config_pps(osi_core);
 exit:
 	return ret;
 }