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osi: fix pending misra for M7

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Bug 3697619

Change-Id: I9eb2e23bc9d5982064d79a47c9b13090dbb56527
Signed-off-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3045591
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Hareesh Kesireddy
2024-01-04 09:42:10 +05:30
committed by Bhadram Varka
parent 2ce3d07587
commit 9dec60b445
2 changed files with 16 additions and 6 deletions
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6
include/nvethernetrm_l3l4.h
View File

@@ -1,5 +1,5 @@
/* SPDX-License-Identifier: LicenseRef-NvidiaProprietary
* SPDX-FileCopyrightText: Copyright (c) 2022-2023 NVIDIA CORPORATION. All rights reserved.
* SPDX-FileCopyrightText: Copyright (c) 2022-2024 NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -26,10 +26,10 @@
#include <nvethernet_type.h>
/** helper macro for enable */
#define OSI_TRUE ((nveu32_t)1)
#define OSI_TRUE (0x12A456F3U)
/** helper macro to disable */
#define OSI_FALSE ((nveu32_t)0)
#define OSI_FALSE (0xD4EA8494U)
/**
* @brief L3/L4 filter function dependent parameter

16
osi/core/osi_hal.c
View File

@@ -1,5 +1,5 @@
// SPDX-License-Identifier: LicenseRef-NvidiaProprietary
/* SPDX-FileCopyrightText: Copyright (c) 2021-2023 NVIDIA CORPORATION. All rights reserved.
/* SPDX-FileCopyrightText: Copyright (c) 2021-2024 NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -38,6 +38,13 @@
* @brief g_ops - Static core operations array.
*/
/** \cond DO_NOT_DOCUMENT */
static inline nve32_t convert_to_s32_with_same_hex(const void *data)
{
return (*((const nve32_t *)data));
}
/** \endcond */
/**
* @brief Function to validate input arguments of API.
*
@@ -2524,6 +2531,7 @@ static nve32_t osi_hal_handle_ioctl(struct osi_core_priv_data *osi_core,
nve32_t freq_adj_value = 0x0;
nvel64_t secondary_time = 0x0;
nvel64_t primary_time = 0x0;
nveu32_t ret_u32;
ops_p = l_core->ops_p;
@@ -2963,12 +2971,14 @@ static nve32_t osi_hal_handle_ioctl(struct osi_core_priv_data *osi_core,
break;
#ifdef MACSEC_SUPPORT
case OSI_CMD_READ_MACSEC_REG:
ret = (nve32_t) ops_p->read_macsec_reg(osi_core, (nve32_t) data->arg1_u32);
ret_u32 = ops_p->read_macsec_reg(osi_core, (nve32_t) data->arg1_u32);
ret = convert_to_s32_with_same_hex(&ret_u32);
break;
case OSI_CMD_WRITE_MACSEC_REG:
ret = (nve32_t) ops_p->write_macsec_reg(osi_core, (nveu32_t) data->arg1_u32,
ret_u32 = ops_p->write_macsec_reg(osi_core, (nveu32_t) data->arg1_u32,
(nve32_t) data->arg2_u32);
ret = convert_to_s32_with_same_hex(&ret_u32);
break;
#endif /* MACSEC_SUPPORT */
case OSI_CMD_GET_TX_TS: