nv-tegra-mirror/nvethernetrm
1
0
Fork 0
mirror of git://nv-tegra.nvidia.com/kernel/nvethernetrm.git synced 2025-12-22 09:12:10 +03:00
Code Issues Packages Projects Releases Wiki Activity

osi: core: Macsec hw access when disabled

Browse Source 
- Do not allow macsec reg read/write when macsec is not supported or
macsec is disabled in DT
- Fix macsec ops null access crash during mtu when macsec disabled

Bug 3889865

Change-Id: Ia111027c7f880a9697470b4118a9c98483575871
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2820321
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Mahesh Patil
2022-12-02 02:16:32 +00:00
committed by Bhadram Varka
parent 4cf9da77e5
commit ab46262b51
2 changed files with 28 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
osi/core/eqos_core.c
View File

@@ -2944,12 +2944,23 @@ static nveu32_t eqos_write_reg(struct osi_core_priv_data *const osi_core,
* - Initialization: Yes
* - Run time: Yes
* - De-initialization: Yes
* @retval data from register on success
* @retval data from register on success and 0xffffffff on failure
*/
static nveu32_t eqos_read_macsec_reg(struct osi_core_priv_data *const osi_core,
const nve32_t reg)
{
return osi_readla(osi_core, (nveu8_t *)osi_core->macsec_base + reg);
nveu32_t ret = 0;
if (osi_core->macsec_ops != OSI_NULL) {
ret = osi_readla(osi_core, (nveu8_t *)osi_core->macsec_base +
reg);
} else {
/* macsec is not supported or not enabled in DT */
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
"read reg failed", 0ULL);
ret = 0xffffffff;
}
return ret;
}
/**
@@ -2964,13 +2975,23 @@ static nveu32_t eqos_read_macsec_reg(struct osi_core_priv_data *const osi_core,
* - Initialization: Yes
* - Run time: Yes
* - De-initialization: Yes
* @retval 0
* @retval 0 on success or 0xffffffff on error
*/
static nveu32_t eqos_write_macsec_reg(struct osi_core_priv_data *const osi_core,
const nveu32_t val, const nve32_t reg)
{
osi_writela(osi_core, val, (nveu8_t *)osi_core->macsec_base + reg);
return 0;
nveu32_t ret = 0;
if (osi_core->macsec_ops != OSI_NULL) {
osi_writela(osi_core, val, (nveu8_t *)osi_core->macsec_base +
reg);
} else {
/* macsec is not supported or not enabled in DT */
OSI_CORE_ERR(osi_core->osd,
OSI_LOG_ARG_HW_FAIL, "write reg failed", 0ULL);
ret = 0xffffffff;
}
return ret;
}
#endif /* MACSEC_SUPPORT */

3
osi/core/osi_hal.c
View File

@@ -2723,7 +2723,8 @@ static nve32_t osi_hal_handle_ioctl(struct osi_core_priv_data *osi_core,
case OSI_CMD_MAC_MTU:
ret = 0;
#ifdef MACSEC_SUPPORT
if (osi_core->macsec_ops->update_mtu != OSI_NULL) {
if ((osi_core->macsec_ops != OSI_NULL) &&
(osi_core->macsec_ops->update_mtu != OSI_NULL)) {
ret = osi_core->macsec_ops->update_mtu(osi_core, data->arg1_u32);
}
#endif /* MACSEC_SUPPORT */