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nvethernetrm: mgbe: add support for jumbo frames

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Bug 200565893

Change-Id: Id27f78180a7d2562c3306e2290555f1609e03a48
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2292258
This commit is contained in:
Bhadram Varka
2019-11-18 16:24:29 +05:30
parent 00e4638fa3
commit b7979a67f1
4 changed files with 35 additions and 13 deletions
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25
osi/core/mgbe_core.c
View File

@@ -1501,7 +1501,30 @@ static void mgbe_configure_mac(struct osi_core_priv_data *osi_core)
/* Enable CRC stripping for Type packets */
/* Enable Rx checksum offload engine by default */
value |= MGBE_MAC_RMCR_ACS | MGBE_MAC_RMCR_CST | MGBE_MAC_RMCR_IPC;
osi_writel(value, (nveu8_t *)osi_core->base + MGBE_MAC_RMCR);
/* Jumbo Packet Enable */
if (osi_core->mtu > OSI_DFLT_MTU_SIZE &&
osi_core->mtu <= OSI_MTU_SIZE_9000) {
value |= MGBE_MAC_RMCR_JE;
} else if (osi_core->mtu > OSI_MTU_SIZE_9000){
/* if MTU greater 9K use GPSLCE */
value |= MGBE_MAC_RMCR_GPSLCE | MGBE_MAC_RMCR_WD;
value &= ~MGBE_MAC_RMCR_GPSL_MSK;
value |= ((OSI_MAX_MTU_SIZE << 16) & MGBE_MAC_RMCR_GPSL_MSK);
} else {
value &= ~MGBE_MAC_RMCR_JE;
value &= ~MGBE_MAC_RMCR_GPSLCE;
value &= ~MGBE_MAC_RMCR_WD;
}
osi_writel(value, (unsigned char *)osi_core->base + MGBE_MAC_RMCR);
value = osi_readl((unsigned char *)osi_core->base + MGBE_MAC_TMCR);
/* Jabber Disable */
if (osi_core->mtu > OSI_DFLT_MTU_SIZE) {
value |= MGBE_MAC_TMCR_JD;
}
osi_writel(value, (unsigned char *)osi_core->base + MGBE_MAC_TMCR);
/* Enable Multicast and Broadcast Queue, default is Q1 */
value = osi_readl((unsigned char *)osi_core->base + MGBE_MAC_RQC1R);

5
osi/core/mgbe_core.h
View File

@@ -185,6 +185,10 @@
#define MGBE_MDIO_SCCD_CR_MASK 0x7U
#define MGBE_MDIO_SCCD_SDATA_MASK 0xFFFFU
#define MGBE_MDIO_SCCD_CRS OSI_BIT(31)
#define MGBE_MAC_RMCR_GPSLCE OSI_BIT(6)
#define MGBE_MAC_RMCR_WD OSI_BIT(7)
#define MGBE_MAC_RMCR_JE OSI_BIT(8)
#define MGBE_MAC_TMCR_JD OSI_BIT(16)
#define MGBE_MMC_CNTRL_CNTRST OSI_BIT(0)
#define MGBE_MMC_CNTRL_RSTONRD OSI_BIT(2)
#define MGBE_MMC_CNTRL_CNTMCT (OSI_BIT(4) | OSI_BIT(5))
@@ -263,6 +267,7 @@
#define MGBE_RXQ_TO_DMA_CHAN_MAP3 0x0F0E0D0CU
#define MGBE_MTL_TXQ_SIZE_SHIFT 16U
#define MGBE_MTL_RXQ_SIZE_SHIFT 16U
#define MGBE_MAC_RMCR_GPSL_MSK 0x3FFF0000U
/** @} */
/**

17
osi/dma/mgbe_dma.c
View File

@@ -412,6 +412,8 @@ static void mgbe_configure_dma_channel(nveu32_t chan,
value = osi_readl((nveu8_t *)osi_dma->base +
MGBE_DMA_CHX_RX_CTRL(chan));
/* clear previous Rx buffer size */
value &= ~MGBE_DMA_CHX_RBSZ_MASK;
value |= (osi_dma->rx_buf_len << MGBE_DMA_CHX_RBSZ_SHIFT);
/* RXPBL = 16 */
value |= MGBE_DMA_CHX_RX_CTRL_RXPBL_RECOMMENDED;
@@ -512,18 +514,9 @@ static void mgbe_set_rx_buf_len(struct osi_dma_priv_data *osi_dma)
{
nveu32_t rx_buf_len;
if (osi_dma->mtu >= OSI_MTU_SIZE_8K) {
rx_buf_len = OSI_MTU_SIZE_16K;
} else if (osi_dma->mtu >= OSI_MTU_SIZE_4K) {
rx_buf_len = OSI_MTU_SIZE_8K;
} else if (osi_dma->mtu >= OSI_MTU_SIZE_2K) {
rx_buf_len = OSI_MTU_SIZE_4K;
} else if (osi_dma->mtu > MAX_ETH_FRAME_LEN_DEFAULT) {
rx_buf_len = OSI_MTU_SIZE_2K;
} else {
rx_buf_len = MAX_ETH_FRAME_LEN_DEFAULT;
}
/* Add Ethernet header + FCS + NET IP align size to MTU */
rx_buf_len = osi_dma->mtu + OSI_ETH_HLEN +
NV_VLAN_HLEN + OSI_NET_IP_ALIGN;
/* Buffer alignment */
osi_dma->rx_buf_len = ((rx_buf_len + (MGBE_AXI_BUS_WIDTH - 1U)) &
~(MGBE_AXI_BUS_WIDTH - 1U));

1
osi/dma/mgbe_dma.h
View File

@@ -67,6 +67,7 @@
#define MGBE_DMA_CHX_TX_CTRL_TSE OSI_BIT(12)
#define MGBE_DMA_CHX_RX_WDT_RWT_MASK 0xFFU
#define MGBE_DMA_CHX_RX_WDT_RWTU 256U
#define MGBE_DMA_CHX_RBSZ_MASK 0x7FFEU
#define MGBE_DMA_CHX_RBSZ_SHIFT 1U
#define MGBE_DMA_CHX_TX_CTRL_TXPBL_RECOMMENDED 0x100000U
#define MGBE_DMA_CHX_RX_CTRL_RXPBL_RECOMMENDED 0x100000U