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git://nv-tegra.nvidia.com/kernel/nvethernetrm.git
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nvethernetrm: mgbe: Implement PTP RX Queue support
Implement config_ptp_rxq call back to add PTP RX Packets routing support. Bug 200596985 Change-Id: I7a7649ab903c546d40a2c208fad381da8bfbc990 Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
This commit is contained in:
committed by
Bhadram Varka
parent
e540dd4386
commit
c18e66fecb
@@ -1321,6 +1321,89 @@ static inline int mgbe_update_vlan_id(struct osi_core_priv_data *const osi_core,
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return 0;
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}
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/**
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* @brief mgbe_config_ptp_rxq - Config PTP RX packets queue route
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*
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* Algorithm: This function is used to program the PTP RX packets queue.
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*
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* @param[in] osi_core: OSI core private data.
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* @param[in] rxq_idx: PTP RXQ index.
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* @param[in] enable: PTP RXQ route enable(1) or disable(0).
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*
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* @note 1) MAC should be init and started. see osi_start_mac()
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* 2) osi_core->osd should be populated
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*
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* @retval 0 on success
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* @retval -1 on failure.
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*/
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static int mgbe_config_ptp_rxq(struct osi_core_priv_data *const osi_core,
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const unsigned int rxq_idx,
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const unsigned int enable)
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{
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unsigned char *base = osi_core->base;
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unsigned int value = 0U;
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unsigned int i = 0U;
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/* Validate the RX queue index argument */
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if (rxq_idx >= OSI_MGBE_MAX_NUM_QUEUES) {
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OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID,
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"Invalid PTP RX queue index\n",
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rxq_idx);
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return -1;
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}
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/* Validate enable argument */
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if (enable != OSI_ENABLE && enable != OSI_DISABLE) {
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OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID,
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"Invalid enable input\n",
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enable);
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return -1;
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}
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/* Validate PTP RX queue enable */
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for (i = 0; i < osi_core->num_mtl_queues; i++) {
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if (osi_core->mtl_queues[i] == rxq_idx) {
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/* Given PTP RX queue is enabled */
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break;
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}
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}
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if (i == osi_core->num_mtl_queues) {
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OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID,
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"PTP RX queue not enabled\n",
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rxq_idx);
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return -1;
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}
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/* Read MAC_RxQ_Ctrl1 */
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value = osi_readl(base + MGBE_MAC_RQC1R);
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/* Check for enable or disable */
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if (enable == OSI_DISABLE) {
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/** Reset OMCBCQ bit to disable over-riding the MCBC Queue
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* priority for the PTP RX queue.
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**/
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value &= ~MGBE_MAC_RQC1R_OMCBCQ;
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} else {
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/* Store PTP RX queue into OSI private data */
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osi_core->ptp_config.ptp_rx_queue = rxq_idx;
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/* Program PTPQ with ptp_rxq */
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value &= ~MGBE_MAC_RQC1R_PTPQ;
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value |= (rxq_idx << MGBE_MAC_RQC1R_PTPQ_SHIFT);
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/** Set TPQC to 0x1 for VLAN Tagged PTP over
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* ethernet packets are routed to Rx Queue specified
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* by PTPQ field
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**/
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value |= MGBE_MAC_RQC1R_TPQC0;
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/** Set OMCBCQ bit to enable over-riding the MCBC Queue
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* priority for the PTP RX queue.
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**/
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value |= MGBE_MAC_RQC1R_OMCBCQ;
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}
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/* Write MAC_RxQ_Ctrl1 */
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osi_writel(value, base + MGBE_MAC_RQC1R);
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return 0;
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}
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/**
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* @brief mgbe_flush_mtl_tx_queue - Flush MTL Tx queue
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*
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@@ -3072,6 +3155,7 @@ void mgbe_init_core_ops(struct core_ops *ops)
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ops->adjust_mactime = OSI_NULL,
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ops->config_tscr = OSI_NULL;
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ops->config_ssir = OSI_NULL;
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ops->config_ptp_rxq = mgbe_config_ptp_rxq;
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ops->write_phy_reg = mgbe_write_phy_reg;
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ops->read_phy_reg = mgbe_read_phy_reg;
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ops->save_registers = mgbe_save_registers;
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@@ -275,6 +275,12 @@
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#define MGBE_MMC_CNTRL_RSTONRD OSI_BIT(2)
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#define MGBE_MMC_CNTRL_CNTMCT (OSI_BIT(4) | OSI_BIT(5))
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#define MGBE_MMC_CNTRL_CNTPRST OSI_BIT(7)
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#define MGBE_MAC_RQC1R_PTPQ (OSI_BIT(27) | OSI_BIT(26) | \
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OSI_BIT(25) | OSI_BIT(24))
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#define MGBE_MAC_RQC1R_PTPQ_SHIFT 24U
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#define MGBE_MAC_RQC1R_TPQC1 OSI_BIT(22)
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#define MGBE_MAC_RQC1R_TPQC0 OSI_BIT(21)
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#define MGBE_MAC_RQC1R_OMCBCQ OSI_BIT(20)
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#define MGBE_MAC_RQC1R_MCBCQEN OSI_BIT(15)
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#define MGBE_MAC_RQC1R_MCBCQ1 OSI_BIT(8)
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#define MGBE_IMR_RGSMIIIE OSI_BIT(0)
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