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osi: core: fix hsi configuration

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Enable below for the HSI configuration
  RXCRCERPIE of MMC_Receive_Interrupt_Enable
  TMOUTEN of MAC_FSM_Control
  OPE of MTL_DPP_Control
  TMOUTEN of MAC_FSM_Control
  FSM_TO_SEL of VR_XS_PCS_SFTY_TMR_CTRL

Bug 4437102

Change-Id: Iaef9bc3e8e44572fd953dbc4d846d871bb2d16a0
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3051420
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Narayan Reddy
2024-01-11 16:16:02 +00:00
committed by Bhadram Varka
parent 33aad27714
commit d68e9e1bdc
5 changed files with 23 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
osi/core/eqos_core.c
View File

@@ -757,15 +757,14 @@ static nve32_t eqos_hsi_configure(struct osi_core_priv_data *const osi_core,
/* T23X-EQOS_HSIv2-3: Enabling and Initialization of Watchdog */
/* T23X-EQOS_HSIv2-4: Enabling of Consistency Monitor for FSM States */
/* TODO enable EQOS_TMOUTEN. Bug 3584387 */
value = EQOS_PRTYEN;
value = EQOS_PRTYEN | EQOS_TMOUTEN;
osi_writela(osi_core, value,
(nveu8_t *)osi_core->base + EQOS_MAC_FSM_CONTROL);
/* T23X-EQOS_HSIv2-2: Enabling of Bus Parity */
value = osi_readla(osi_core,
(nveu8_t *)osi_core->base + EQOS_MTL_DPP_CONTROL);
value |= EQOS_EDPP;
value |= EQOS_EDPP | EQOS_OPE;
osi_writela(osi_core, value,
(nveu8_t *)osi_core->base + EQOS_MTL_DPP_CONTROL);

7
osi/core/eqos_core.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2023, NVIDIA CORPORATION. All rights reserved.
/* SPDX-License-Identifier: LicenseRef-NvidiaProprietary
* SPDX-FileCopyrightText: Copyright (c) 2018-2024 NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -784,10 +784,11 @@ void update_ehfc_rfa_rfd(nveu32_t rx_fifo, nveu32_t *value);
#define EQOS_TMR_MASK 0x3FFU
#define EQOS_MAC_FSM_CONTROL 0x148U
#define EQOS_PRTYEN OSI_BIT(1)
#define EQOS_TMOUTEN OSI_BIT(0)
#define EQOS_MAC_DPP_FSM_INTERRUPT_STATUS 0x140U
#define EQOS_MTL_DPP_CONTROL 0xCE0U
#define EQOS_EDPP OSI_BIT(0)
#define EQOS_MAC_DPP_FSM_INTERRUPT_STATUS 0x140U
#define EQOS_OPE OSI_BIT(1)
#define EQOS_MTL_DBG_CTL 0xC08U
#define EQOS_MTL_DBG_CTL_EIEC OSI_BIT(18)
#define EQOS_MTL_DBG_CTL_EIEE OSI_BIT(16)

17
osi/core/mgbe_core.c
View File

@@ -1507,6 +1507,7 @@ static nve32_t mgbe_hsi_configure(struct osi_core_priv_data *const osi_core,
/* T23X-MGBE_HSIv2-12:Initialization of Transaction Timeout in PCS */
/* T23X-MGBE_HSIv2-11:Initialization of Watchdog Timer */
value = (0xCCU << XPCS_SFTY_1US_MULT_SHIFT) & XPCS_SFTY_1US_MULT_MASK;
value |= ((nveu32_t)0x01U << XPCS_FSM_TO_SEL_SHIFT) & XPCS_FSM_TO_SEL_MASK;
ret = xpcs_write_safety(osi_core, XPCS_VR_XS_PCS_SFTY_TMR_CTRL, value);
if (ret != 0) {
goto fail;
@@ -1533,11 +1534,17 @@ static nve32_t mgbe_hsi_configure(struct osi_core_priv_data *const osi_core,
/* T23X-MGBE_HSIv2-3: Enabling and Initialization of Watchdog Timer */
/* T23X-MGBE_HSIv2-4: Enabling of Consistency Monitor for XGMAC FSM State */
/* TODO enable MGBE_TMOUTEN. Bug 3584387 */
value = MGBE_PRTYEN;
value = MGBE_PRTYEN | MGBE_TMOUTEN;
osi_writela(osi_core, value,
(nveu8_t *)osi_core->base + MGBE_MAC_FSM_CONTROL);
/* T23X-MGBE_HSIv2-20: Enabling of error reporting for Inbound Bus CRC errors */
value = osi_readla(osi_core,
(nveu8_t *)osi_core->base + MGBE_MMC_RX_INTR_EN);
value |= MGBE_RXCRCERPIE;
osi_writela(osi_core, value,
(nveu8_t *)osi_core->base + MGBE_MMC_RX_INTR_EN);
/* T23X-MGBE_HSIv2-2: Enabling of Bus Parity */
value = osi_readla(osi_core,
(nveu8_t *)osi_core->base + MGBE_MTL_DPP_CONTROL);
@@ -1613,6 +1620,9 @@ static nve32_t mgbe_hsi_configure(struct osi_core_priv_data *const osi_core,
osi_writela(osi_core, 0,
(nveu8_t *)osi_core->base + MGBE_MAC_FSM_CONTROL);
/* T23X-MGBE_HSIv2-20: Enabling of error reporting for Inbound Bus CRC errors */
osi_writela(osi_core, 0, (nveu8_t *)osi_core->base + MGBE_MMC_RX_INTR_EN);
/* T23X-MGBE_HSIv2-2: Disable of Bus Parity */
value = osi_readla(osi_core,
(nveu8_t *)osi_core->base + MGBE_MTL_DPP_CONTROL);
@@ -1781,9 +1791,6 @@ static nve32_t mgbe_configure_mac(struct osi_core_priv_data *osi_core)
/* Disable all MMC Tx nve32_terrupts */
osi_writela(osi_core, OSI_NONE, (nveu8_t *)osi_core->base +
MGBE_MMC_TX_INTR_EN);
/* Disable all MMC RX nve32_terrupts */
osi_writela(osi_core, OSI_NONE, (nveu8_t *)osi_core->base +
MGBE_MMC_RX_INTR_EN);
/* Configure MMC counters */
value = osi_readla(osi_core,

2
osi/core/mgbe_core.h
View File

@@ -987,6 +987,8 @@
#define MGBE_MTL_ECC_DESCED OSI_BIT(5)
#define MGBE_MAC_FSM_CONTROL 0x158U
#define MGBE_PRTYEN OSI_BIT(1)
#define MGBE_TMOUTEN OSI_BIT(0)
#define MGBE_RXCRCERPIE OSI_BIT(5)
#define MGBE_MAC_DPP_FSM_INTERRUPT_STATUS 0x150U
#define MGBE_MTL_DPP_CONTROL 0x10E0U
#define MGBE_DDPP OSI_BIT(0)

3
osi/core/xpcs.h
View File

@@ -109,6 +109,9 @@
#define XPCS_VR_XS_PCS_SFTY_TMR_CTRL 0xE03D4
#define XPCS_SFTY_1US_MULT_MASK 0xFFU
#define XPCS_SFTY_1US_MULT_SHIFT 0U
#define XPCS_FSM_TO_SEL_SHIFT 10U
#define XPCS_FSM_TO_SEL_MASK 0xC00U
#define XPCS_FEC_EN OSI_BIT(0)
#endif
/** @} */