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osi: core: macsec: enable SECURE_REG_VIOL intr

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enable SECURE_REG_VIOL interrupt to generate
uncorrected Error for illegal access errors
for MACSEC Registers

Bug 3590939

Change-Id: I4f50c1b709ed3662eb6062dcbbbe42a8e36f101c
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2767836
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Om Prakash Singh
2022-08-27 18:13:43 +05:30
committed by Bhadram Varka
parent 9bae4a2183
commit e49f5c01ce
3 changed files with 18 additions and 10 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
include/osi_core.h
View File

@@ -366,6 +366,7 @@ typedef my_lint_64 nvel64_t;
#define MACSEC_RX_CRC_ERR_IDX 0U
#define MACSEC_TX_CRC_ERR_IDX 1U
#define MACSEC_RX_ICV_ERR_IDX 2U
#define MACSEC_REG_VIOL_ERR_IDX 3U
/** @} */
extern nveu32_t hsi_err_code[][3];
@@ -388,13 +389,14 @@ extern nveu32_t hsi_err_code[][3];
/**
* @brief Maximum number of different mac error code
* HSI_SW_ERR_CODE + Two (Corrected and Uncorrected error code)
*/
#define HSI_MAX_MAC_ERROR_CODE 6U
/**
* @brief Maximum number of different macsec error code
*/
#define HSI_MAX_MACSEC_ERROR_CODE 3U
#define HSI_MAX_MACSEC_ERROR_CODE 4U
/**
* @addtogroup HSI_SW_ERR_CODE
@@ -409,7 +411,7 @@ extern nveu32_t hsi_err_code[][3];
#define OSI_MACSEC_RX_CRC_ERR 0x1005U
#define OSI_MACSEC_TX_CRC_ERR 0x1006U
#define OSI_MACSEC_RX_ICV_ERR 0x1007U
#define OSI_MACSEC_REG_VIOL_ERR 0x1008U
/** @} */
#endif

16
osi/core/macsec.c
View File

@@ -3669,6 +3669,13 @@ static inline void handle_common_irq(struct osi_core_priv_data *const osi_core)
if ((common_isr & MACSEC_SECURE_REG_VIOL) == MACSEC_SECURE_REG_VIOL) {
CERT_C__POST_INC__U64(osi_core->macsec_irq_stats.secure_reg_viol);
clear |= MACSEC_SECURE_REG_VIOL;
#ifdef HSI_SUPPORT
if (osi_core->hsi.enabled == OSI_ENABLE) {
osi_core->hsi.macsec_err_code[MACSEC_REG_VIOL_ERR_IDX] =
OSI_MACSEC_REG_VIOL_ERR;
osi_core->hsi.macsec_report_err = OSI_ENABLE;
}
#endif
}
if ((common_isr & MACSEC_RX_UNINIT_KEY_SLOT) ==
@@ -4399,8 +4406,7 @@ static void macsec_intr_config(struct osi_core_priv_data *const osi_core, nveu32
val |= (MACSEC_RX_UNINIT_KEY_SLOT_INT_EN |
MACSEC_RX_LKUP_MISS_INT_EN |
MACSEC_TX_UNINIT_KEY_SLOT_INT_EN |
MACSEC_TX_LKUP_MISS_INT_EN |
MACSEC_SECURE_REG_VIOL_INT_EN);
MACSEC_TX_LKUP_MISS_INT_EN);
osi_writela(osi_core, val, addr + MACSEC_COMMON_IMR);
LOG("Write MACSEC_COMMON_IMR: 0x%x\n", val);
} else {
@@ -4431,8 +4437,7 @@ static void macsec_intr_config(struct osi_core_priv_data *const osi_core, nveu32
val &= (~MACSEC_RX_UNINIT_KEY_SLOT_INT_EN &
~MACSEC_RX_LKUP_MISS_INT_EN &
~MACSEC_TX_UNINIT_KEY_SLOT_INT_EN &
~MACSEC_TX_LKUP_MISS_INT_EN &
~MACSEC_SECURE_REG_VIOL_INT_EN);
~MACSEC_TX_LKUP_MISS_INT_EN);
osi_writela(osi_core, val, addr + MACSEC_COMMON_IMR);
LOG("Write MACSEC_COMMON_IMR: 0x%x\n", val);
}
@@ -4561,6 +4566,9 @@ static nve32_t macsec_initialize(struct osi_core_priv_data *const osi_core, nveu
LOG("Write MACSEC_RX_IMR: 0x%x\n", val);
osi_writela(osi_core, val, addr + MACSEC_RX_IMR);
val = osi_readla(osi_core, addr + MACSEC_COMMON_IMR);
val |= MACSEC_SECURE_REG_VIOL_INT_EN;
osi_writela(osi_core, val, addr + MACSEC_COMMON_IMR);
/* Set AES mode
* Default power on reset is AES-GCM128, leave it.
*/

6
osi/core/macsec.h
View File

@@ -91,9 +91,7 @@
#define MACSEC_TX_SCI_LUT_VALID 0xD028
#define MACSEC_RX_BYP_LUT_VALID 0xD02C
#define MACSEC_RX_SCI_LUT_VALID 0xD030
#ifdef DEBUG_MACSEC
#define MACSEC_COMMON_IMR 0xD054
#endif /* DEBUG_MACSEC */
#define MACSEC_COMMON_ISR 0xD058
#define MACSEC_TX_SC_KEY_INVALID_STS0_0 0xD064
#define MACSEC_TX_SC_KEY_INVALID_STS1_0 0xD068
@@ -217,7 +215,6 @@
#define MACSEC_TX_AES_MODE_AES256 OSI_BIT(1)
/** @} */
#ifdef DEBUG_MACSEC
/**
* @addtogroup MACSEC_COMMON_IMR register
*
@@ -225,12 +222,13 @@
* @{
*/
#define MACSEC_SECURE_REG_VIOL_INT_EN OSI_BIT(31)
#ifdef DEBUG_MACSEC
#define MACSEC_RX_UNINIT_KEY_SLOT_INT_EN OSI_BIT(17)
#define MACSEC_RX_LKUP_MISS_INT_EN OSI_BIT(16)
#define MACSEC_TX_UNINIT_KEY_SLOT_INT_EN OSI_BIT(1)
#define MACSEC_TX_LKUP_MISS_INT_EN OSI_BIT(0)
/** @} */
#endif /* DEBUG_MACSEC */
/** @} */
/**
* @addtogroup MACSEC_TX_IMR register