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osi: core: fix misra 4.6 rule

Browse Source 
===== DIFF ======
Total misra violation count changed by -240
Rule: MISRA_C-2012_Directive_4.6 Diff: -240
Rule: Total Diff: -240

Bug 3695218

Change-Id: Ida2d3a775872637eda3058ea361a00346c86f7f7
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2767895
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Narayan Reddy
2022-08-27 21:55:06 +00:00
committed by Bhadram Varka
parent 53faa7fc0a
commit ef38debe2e
20 changed files with 792 additions and 793 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
include/ivc_core.h
View File

@@ -106,11 +106,11 @@ typedef struct macsec_config {
/** MACsec secure channel basic information */
struct osi_macsec_sc_info sc_info;
/** MACsec enable or disable */
unsigned int enable;
nveu32_t enable;
/** MACsec controller */
unsigned short ctlr;
nveu16_t ctlr;
/** MACsec KT index */
unsigned short kt_idx;
nveu16_t kt_idx;
/** MACsec KT index */
nveu32_t key_index;
/** MACsec SCI */

12
include/mmc.h
View File

@@ -530,25 +530,25 @@ struct osi_mmc_counters {
nveu64_t mmc_rx_icmp_err_octets_h;
/** This counter provides the number of additional mPackets
* transmitted due to preemption */
unsigned long mmc_tx_fpe_frag_cnt;
nveu64_t mmc_tx_fpe_frag_cnt;
/** This counter provides the count of number of times a hold
* request is given to MAC */
unsigned long mmc_tx_fpe_hold_req_cnt;
nveu64_t mmc_tx_fpe_hold_req_cnt;
/** This counter provides the number of MAC frames with reassembly
* errors on the Receiver, due to mismatch in the fragment
* count value */
unsigned long mmc_rx_packet_reass_err_cnt;
nveu64_t mmc_rx_packet_reass_err_cnt;
/** This counter the number of received MAC frames rejected
* due to unknown SMD value and MAC frame fragments rejected due
* to arriving with an SMD-C when there was no preceding preempted
* frame */
unsigned long mmc_rx_packet_smd_err_cnt;
nveu64_t mmc_rx_packet_smd_err_cnt;
/** This counter provides the number of MAC frames that were
* successfully reassembled and delivered to MAC */
unsigned long mmc_rx_packet_asm_ok_cnt;
nveu64_t mmc_rx_packet_asm_ok_cnt;
/** This counter provides the number of additional mPackets received
* due to preemption */
unsigned long mmc_rx_fpe_fragment_cnt;
nveu64_t mmc_rx_fpe_fragment_cnt;
};
/**

26
include/osi_common.h
View File

@@ -32,19 +32,19 @@
* the flow control is asserted or de-asserted
* @{
*/
#define FULL_MINUS_1_5K (unsigned int)1
#define FULL_MINUS_2_K (unsigned int)2
#define FULL_MINUS_2_5K (unsigned int)3
#define FULL_MINUS_3_K (unsigned int)4
#define FULL_MINUS_4_K (unsigned int)6
#define FULL_MINUS_6_K (unsigned int)10
#define FULL_MINUS_10_K (unsigned int)18
#define FULL_MINUS_16_K (unsigned int)30
#define FULL_MINUS_18_K (unsigned int)34
#define FULL_MINUS_21_K (unsigned int)40
#define FULL_MINUS_24_K (unsigned int)46
#define FULL_MINUS_29_K (unsigned int)56
#define FULL_MINUS_32_K (unsigned int)62
#define FULL_MINUS_1_5K ((nveu32_t)1)
#define FULL_MINUS_2_K ((nveu32_t)2)
#define FULL_MINUS_2_5K ((nveu32_t)3)
#define FULL_MINUS_3_K ((nveu32_t)4)
#define FULL_MINUS_4_K ((nveu32_t)6)
#define FULL_MINUS_6_K ((nveu32_t)10)
#define FULL_MINUS_10_K ((nveu32_t)18)
#define FULL_MINUS_16_K ((nveu32_t)30)
#define FULL_MINUS_18_K ((nveu32_t)34)
#define FULL_MINUS_21_K ((nveu32_t)40)
#define FULL_MINUS_24_K ((nveu32_t)46)
#define FULL_MINUS_29_K ((nveu32_t)56)
#define FULL_MINUS_32_K ((nveu32_t)62)
/** @} */
/**

128
include/osi_core.h
View File

@@ -460,11 +460,11 @@ struct osi_filter {
struct osi_rxq_route {
#define OSI_RXQ_ROUTE_PTP 0U
/** Indicates RX routing type OSI_RXQ_ROUTE_* */
unsigned int route_type;
nveu32_t route_type;
/** RXQ routing enable(1) disable (0) */
unsigned int enable;
nveu32_t enable;
/** RX queue index */
unsigned int idx;
nveu32_t idx;
};
#endif
/**
@@ -816,23 +816,23 @@ struct osi_vlan_filter {
*/
struct osi_core_frp_data {
/* Entry Match Data */
unsigned int match_data;
nveu32_t match_data;
/* Entry Match Enable mask */
unsigned int match_en;
nveu32_t match_en;
/* Entry Accept frame flag */
unsigned char accept_frame;
nveu8_t accept_frame;
/* Entry Reject Frame flag */
unsigned char reject_frame;
nveu8_t reject_frame;
/* Entry Inverse match flag */
unsigned char inverse_match;
nveu8_t inverse_match;
/* Entry Next Instruction Control match flag */
unsigned char next_ins_ctrl;
nveu8_t next_ins_ctrl;
/* Entry Frame offset in the packet data */
unsigned char frame_offset;
nveu8_t frame_offset;
/* Entry OK Index - Next Instruction */
unsigned char ok_index;
nveu8_t ok_index;
/* Entry DMA Channel selection (1-bit for each channel) */
unsigned int dma_chsel;
nveu32_t dma_chsel;
};
/**
@@ -840,23 +840,23 @@ struct osi_core_frp_data {
*/
struct osi_core_frp_cmd {
/* FRP Command type */
unsigned int cmd;
nveu32_t cmd;
/* OSD FRP ID */
int frp_id;
/* OSD match data type */
unsigned char match_type;
nveu8_t match_type;
/* OSD match data */
unsigned char match[OSI_FRP_MATCH_DATA_MAX];
nveu8_t match[OSI_FRP_MATCH_DATA_MAX];
/* OSD match data length */
unsigned char match_length;
nveu8_t match_length;
/* OSD Offset */
unsigned char offset;
nveu8_t offset;
/* OSD FRP filter mode flag */
unsigned char filter_mode;
nveu8_t filter_mode;
/* OSD FRP Link ID */
int next_frp_id;
/* OSD DMA Channel Selection */
unsigned int dma_sel;
nveu32_t dma_sel;
};
/**
@@ -910,7 +910,7 @@ struct osi_core_avb_algorithm {
* 10: enable */
nveu32_t oper_mode;
/** TC index */
unsigned int tcindex;
nveu32_t tcindex;
};
/**
@@ -918,20 +918,20 @@ struct osi_core_avb_algorithm {
*/
struct osi_pto_config {
/** enable(0) / disable(1) */
unsigned int en_dis;
nveu32_t en_dis;
/** Flag for Master mode.
* OSI_ENABLE for master OSI_DISABLE for slave */
unsigned int master;
nveu32_t master;
/** Flag to Select PTP packets for Taking Snapshots */
unsigned int snap_type;
nveu32_t snap_type;
/** ptp domain */
unsigned int domain_num;
nveu32_t domain_num;
/** The PTP Offload function qualifies received PTP
* packet with unicast Destination address
* 0 - only multicast, 1 - unicast and multicast */
unsigned int mc_uc;
nveu32_t mc_uc;
/** Port identification */
unsigned int portid;
nveu32_t portid;
};
/**
@@ -939,23 +939,23 @@ struct osi_pto_config {
*/
struct osi_est_config {
/** enable/disable */
unsigned int en_dis;
nveu32_t en_dis;
/** 64 bit base time register
* if both vlaues are 0, take ptp time to avoid BTRE
* index 0 for nsec, index 1 for sec
*/
unsigned int btr[2];
nveu32_t btr[2];
/** 64 bit base time offset index 0 for nsec, index 1 for sec */
unsigned int btr_offset[2];
nveu32_t btr_offset[2];
/** 40 bit cycle time register, index 0 for nsec, index 1 for sec */
unsigned int ctr[2];
nveu32_t ctr[2];
/** Configured Time Interval width + 7 bit extension register */
unsigned int ter;
nveu32_t ter;
/** size of the gate control list */
unsigned int llr;
nveu32_t llr;
/** data array 8 bit gate op + 24 execution time
* MGBE HW support GCL depth 256 */
unsigned int gcl[OSI_GCL_SIZE_256];
nveu32_t gcl[OSI_GCL_SIZE_256];
};
/**
@@ -963,11 +963,11 @@ struct osi_est_config {
*/
struct osi_fpe_config {
/** Queue Mask 1 preemption 0- express bit representation */
unsigned int tx_queue_preemption_enable;
nveu32_t tx_queue_preemption_enable;
/** RQ for all preemptable packets which are not filtered
* based on user priority or SA-DA
*/
unsigned int rq;
nveu32_t rq;
};
/**
@@ -975,19 +975,19 @@ struct osi_fpe_config {
*/
struct osi_tsn_stats {
/** Constant Gate Control Error */
unsigned long const_gate_ctr_err;
nveu64_t const_gate_ctr_err;
/** Head-Of-Line Blocking due to Scheduling */
unsigned long head_of_line_blk_sch;
nveu64_t head_of_line_blk_sch;
/** Per TC Schedule Error */
unsigned long hlbs_q[OSI_MAX_TC_NUM];
nveu64_t hlbs_q[OSI_MAX_TC_NUM];
/** Head-Of-Line Blocking due to Frame Size */
unsigned long head_of_line_blk_frm;
nveu64_t head_of_line_blk_frm;
/** Per TC Frame Size Error */
unsigned long hlbf_q[OSI_MAX_TC_NUM];
nveu64_t hlbf_q[OSI_MAX_TC_NUM];
/** BTR Error */
unsigned long base_time_reg_err;
nveu64_t base_time_reg_err;
/** Switch to Software Owned List Complete */
unsigned long sw_own_list_complete;
nveu64_t sw_own_list_complete;
};
/**
@@ -996,11 +996,11 @@ struct osi_tsn_stats {
*/
struct osi_core_rss {
/** Flag to represent to enable RSS or not */
unsigned int enable;
nveu32_t enable;
/** Array for storing RSS Hash key */
unsigned char key[OSI_RSS_HASH_KEY_SIZE];
nveu8_t key[OSI_RSS_HASH_KEY_SIZE];
/** Array for storing RSS Hash table */
unsigned int table[OSI_RSS_MAX_TABLE_SIZE];
nveu32_t table[OSI_RSS_MAX_TABLE_SIZE];
};
/**
@@ -1104,7 +1104,7 @@ struct osi_vm_irq_data {
*/
struct osd_core_ops {
/** padctrl rx pin disable/enable callback */
int (*padctrl_mii_rx_pins)(void *priv, nveu32_t enable);
nve32_t (*padctrl_mii_rx_pins)(void *priv, nveu32_t enable);
/** logging callback */
void (*ops_log)(void *priv, const nve8_t *func, nveu32_t line,
nveu32_t level, nveu32_t type, const nve8_t *err,
@@ -1120,7 +1120,7 @@ struct osd_core_ops {
nveu32_t len);
#ifdef MACSEC_SUPPORT
/** Program macsec key table through Trust Zone callback */
nve32_t (*macsec_tz_kt_config)(void *priv, unsigned char cmd,
nve32_t (*macsec_tz_kt_config)(void *priv, nveu8_t cmd,
void *const kt_config,
void *const genl_info);
#endif /* MACSEC_SUPPORT */
@@ -1131,7 +1131,7 @@ struct osd_core_ops {
const char *fmt, ...);
#endif
/** Lane bringup restart callback */
void (*restart_lane_bringup)(void *priv, unsigned int en_disable);
void (*restart_lane_bringup)(void *priv, nveu32_t en_disable);
};
#ifdef MACSEC_SUPPORT
@@ -1297,19 +1297,19 @@ struct core_padctrl {
/** Memory mapped base address of eqos padctrl registers */
void *padctrl_base;
/** EQOS_RD0_0 register offset */
unsigned int offset_rd0;
nveu32_t offset_rd0;
/** EQOS_RD1_0 register offset */
unsigned int offset_rd1;
nveu32_t offset_rd1;
/** EQOS_RD2_0 register offset */
unsigned int offset_rd2;
nveu32_t offset_rd2;
/** EQOS_RD3_0 register offset */
unsigned int offset_rd3;
nveu32_t offset_rd3;
/** RX_CTL_0 register offset */
unsigned int offset_rx_ctl;
nveu32_t offset_rx_ctl;
/** is pad calibration in progress */
unsigned int is_pad_cal_in_progress;
nveu32_t is_pad_cal_in_progress;
/** This flag set/reset using priv ioctl and DT entry */
unsigned int pad_calibration_enable;
nveu32_t pad_calibration_enable;
};
#ifndef OSI_STRIPPED_LIB
@@ -1405,7 +1405,7 @@ struct osi_core_priv_data {
/** FPE HW configuration initited to enable/disable
* 1- FPE HW configuration initiated to enable
* 0- FPE HW configuration initiated to disable */
unsigned int is_fpe_enabled;
nveu32_t is_fpe_enabled;
#endif /* MACSEC_SUPPORT */
/** Pointer to OSD private data structure */
void *osd;
@@ -1442,14 +1442,14 @@ struct osi_core_priv_data {
/** DMA channel selection enable (1) */
nveu32_t dcs_en;
/** TQ:TC mapping */
unsigned int tc[OSI_MGBE_MAX_NUM_CHANS];
nveu32_t tc[OSI_MGBE_MAX_NUM_CHANS];
#ifndef OSI_STRIPPED_LIB
/** xtra sw error counters */
struct osi_xtra_stat_counters xstats;
/** Memory mapped base address of HV window */
void *hv_base;
/** Residual queue valid with FPE support */
unsigned int residual_queue;
nveu32_t residual_queue;
/** Functional safety config to do periodic read-verify of
* certain safety critical registers */
void *safety_config;
@@ -1458,28 +1458,28 @@ struct osi_core_priv_data {
/** FRP Instruction Table */
struct osi_core_frp_entry frp_table[OSI_FRP_MAX_ENTRY];
/** Number of valid Entries in the FRP Instruction Table */
unsigned int frp_cnt;
nveu32_t frp_cnt;
/** RSS core structure */
struct osi_core_rss rss;
/* Switch to Software Owned List Complete.
* 1 - Successful and User configured GCL in placed
*/
unsigned int est_ready;
nveu32_t est_ready;
/* FPE enabled, verify and respose done with peer device
* 1- Successful and can be used between P2P device
*/
unsigned int fpe_ready;
nveu32_t fpe_ready;
/** TSN stats counters */
struct osi_tsn_stats tsn_stats;
/** csr clock is to program LPI 1 us tick timer register.
* Value stored in MHz
*/
nveu32_t csr_clk_speed;
unsigned long vf_bitmap;
nveu64_t vf_bitmap;
/** Array to maintaion VLAN filters */
unsigned short vid[VLAN_NUM_VID];
nveu16_t vid[VLAN_NUM_VID];
/** Count of number of VLAN filters in vid array */
unsigned short vlan_filter_cnt;
nveu16_t vlan_filter_cnt;
#endif
/** eqos pad control structure */
struct core_padctrl padctrl;

18
include/osi_dma.h
View File

@@ -288,13 +288,13 @@ struct osi_pkt_err_stats {
/** FRP Parsed count, includes accept
* routing-bypass, or result-bypass count.
*/
unsigned long frp_parsed;
nveu64_t frp_parsed;
/** FRP Dropped count */
unsigned long frp_dropped;
nveu64_t frp_dropped;
/** FRP Parsing Error count */
unsigned long frp_err;
nveu64_t frp_err;
/** FRP Incomplete Parsing */
unsigned long frp_incomplete;
nveu64_t frp_incomplete;
};
#endif /* !OSI_STRIPPED_LIB */
@@ -387,9 +387,9 @@ struct osi_tx_swcx {
* Bit 0 is_paged_buf - whether buffer pointed by buf_phy_addr
* is a paged buffer/linear buffer
* Bit 1 PTP hwtime form timestamp registers */
unsigned int flags;
nveu32_t flags;
/** Packet id of packet for which TX timestamp needed */
unsigned int pktid;
nveu32_t pktid;
/** dma channel number for osd use */
nveu32_t chan;
/** reserved field 1 for future use */
@@ -444,7 +444,7 @@ struct osi_txdone_pkt_cx {
* bit is set in fields */
nveul64_t ns;
/** Passing packet id to map TX time to packet */
unsigned int pktid;
nveu32_t pktid;
};
/**
@@ -608,7 +608,7 @@ struct osi_dma_priv_data {
* OSI_PTP_SYNC_ONESTEP - one-step mode
* OSI_PTP_SYNC_TWOSTEP - two step mode
*/
unsigned int ptp_flag;
nveu32_t ptp_flag;
#ifdef OSI_DEBUG
/** OSI DMA IOCTL data */
struct osi_dma_ioctl_data ioctl_data;
@@ -667,7 +667,7 @@ nveu32_t osi_get_global_dma_status(struct osi_dma_priv_data *osi_dma);
* @retval "Number of available free descriptors."
*/
nveu32_t osi_get_refill_rx_desc_cnt(struct osi_dma_priv_data *osi_dma,
unsigned int chan);
nveu32_t chan);
/**
* @brief osi_rx_dma_desc_init - DMA Rx descriptor init

26
osi/core/core_local.h
View File

@@ -212,7 +212,7 @@ struct core_ops {
const nveu32_t enable,
const nveu8_t *ip_addr);
/** Called to configure HW PTP offload feature */
int (*config_ptp_offload)(struct osi_core_priv_data *const osi_core,
nve32_t (*config_ptp_offload)(struct osi_core_priv_data *const osi_core,
struct osi_pto_config *const pto_config);
/** Called periodically to read and validate safety critical
* registers against last written value */
@@ -248,31 +248,31 @@ struct core_ops {
struct osi_core_priv_data *const osi_core,
const nveu32_t lb_mode);
/** Called to update GCL config */
int (*hw_config_est)(struct osi_core_priv_data *const osi_core,
nve32_t (*hw_config_est)(struct osi_core_priv_data *const osi_core,
struct osi_est_config *const est);
/** Called to update FPE config */
int (*hw_config_fpe)(struct osi_core_priv_data *const osi_core,
nve32_t (*hw_config_fpe)(struct osi_core_priv_data *const osi_core,
struct osi_fpe_config *const fpe);
/** Called to configure FRP engine */
int (*config_frp)(struct osi_core_priv_data *const osi_core,
const unsigned int enabled);
nve32_t (*config_frp)(struct osi_core_priv_data *const osi_core,
const nveu32_t enabled);
/** Called to update FRP Instruction Table entry */
int (*update_frp_entry)(struct osi_core_priv_data *const osi_core,
const unsigned int pos,
nve32_t (*update_frp_entry)(struct osi_core_priv_data *const osi_core,
const nveu32_t pos,
struct osi_core_frp_data *const data);
/** Called to update FRP NVE and */
int (*update_frp_nve)(struct osi_core_priv_data *const osi_core,
const unsigned int nve);
nve32_t (*update_frp_nve)(struct osi_core_priv_data *const osi_core,
const nveu32_t nve);
/** Called to configure RSS for MAC */
nve32_t (*config_rss)(struct osi_core_priv_data *osi_core);
/** Called to configure the PTP RX packets Queue */
nve32_t (*config_ptp_rxq)(struct osi_core_priv_data *const osi_core,
const unsigned int rxq_idx,
const unsigned int enable);
const nveu32_t rxq_idx,
const nveu32_t enable);
#endif /* !OSI_STRIPPED_LIB */
#ifdef HSI_SUPPORT
/** Interface function called to initialize HSI */
int (*core_hsi_configure)(struct osi_core_priv_data *const osi_core,
nve32_t (*core_hsi_configure)(struct osi_core_priv_data *const osi_core,
const nveu32_t enable);
#endif
};
@@ -458,7 +458,7 @@ struct core_local {
};
/**
* @brief update_counter_u - Increment unsigned int counter
* @brief update_counter_u - Increment nveu32_t counter
*
* @param[out] value: Pointer to value to be incremented.
* @param[in] incr: increment value

24
osi/core/debug.c
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2021, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2021-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -32,7 +32,7 @@
*
*/
static void core_dump_struct(struct osi_core_priv_data *osi_core,
unsigned char *ptr,
nveu8_t *ptr,
unsigned long size)
{
nveu32_t i = 0, rem, j;
@@ -72,40 +72,40 @@ void core_structs_dump(struct osi_core_priv_data *osi_core)
osi_core->osd_ops.printf(osi_core, OSI_DEBUG_TYPE_STRUCTS,
"CORE struct size = %lu",
sizeof(struct osi_core_priv_data));
core_dump_struct(osi_core, (unsigned char *)osi_core,
core_dump_struct(osi_core, (nveu8_t *)osi_core,
sizeof(struct osi_core_priv_data));
#ifdef MACSEC_SUPPORT
osi_core->osd_ops.printf(osi_core, OSI_DEBUG_TYPE_STRUCTS,
"MACSEC ops size = %lu",
sizeof(struct osi_macsec_core_ops));
core_dump_struct(osi_core, (unsigned char *)osi_core->macsec_ops,
core_dump_struct(osi_core, (nveu8_t *)osi_core->macsec_ops,
sizeof(struct osi_macsec_core_ops));
osi_core->osd_ops.printf(osi_core, OSI_DEBUG_TYPE_STRUCTS,
"MACSEC LUT status size = %lu",
sizeof(struct osi_macsec_lut_status));
core_dump_struct(osi_core, (unsigned char *)osi_core->macsec_ops,
core_dump_struct(osi_core, (nveu8_t *)osi_core->macsec_ops,
sizeof(struct osi_macsec_lut_status));
#endif
osi_core->osd_ops.printf(osi_core, OSI_DEBUG_TYPE_STRUCTS,
"HW features size = %lu",
sizeof(struct osi_hw_features));
core_dump_struct(osi_core, (unsigned char *)osi_core->hw_feature,
core_dump_struct(osi_core, (nveu8_t *)osi_core->hw_feature,
sizeof(struct osi_hw_features));
osi_core->osd_ops.printf(osi_core, OSI_DEBUG_TYPE_STRUCTS,
"core local size = %lu",
sizeof(struct core_local));
core_dump_struct(osi_core, (unsigned char *)l_core,
core_dump_struct(osi_core, (nveu8_t *)l_core,
sizeof(struct core_local));
osi_core->osd_ops.printf(osi_core, OSI_DEBUG_TYPE_STRUCTS,
"core ops size = %lu",
sizeof(struct core_ops));
core_dump_struct(osi_core, (unsigned char *)l_core->ops_p,
core_dump_struct(osi_core, (nveu8_t *)l_core->ops_p,
sizeof(struct core_ops));
osi_core->osd_ops.printf(osi_core, OSI_DEBUG_TYPE_STRUCTS,
"if_ops_p struct size = %lu",
sizeof(struct if_core_ops));
core_dump_struct(osi_core, (unsigned char *)l_core->if_ops_p,
core_dump_struct(osi_core, (nveu8_t *)l_core->if_ops_p,
sizeof(struct if_core_ops));
}
@@ -116,9 +116,9 @@ void core_structs_dump(struct osi_core_priv_data *osi_core)
*/
void core_reg_dump(struct osi_core_priv_data *osi_core)
{
unsigned int max_addr;
unsigned int addr = 0x0;
unsigned int reg_val;
nveu32_t max_addr;
nveu32_t addr = 0x0;
nveu32_t reg_val;
switch (osi_core->mac_ver) {
case OSI_EQOS_MAC_5_00:

194
osi/core/eqos_core.c
View File

@@ -934,12 +934,12 @@ static nve32_t eqos_configure_mtl_queue(nveu32_t qinx,
* @retval 0 on success
* @retval -1 on failure.
*/
static int eqos_config_frp(struct osi_core_priv_data *const osi_core,
const unsigned int enabled)
static nve32_t eqos_config_frp(struct osi_core_priv_data *const osi_core,
const nveu32_t enabled)
{
unsigned char *base = osi_core->base;
unsigned int op_mode = 0U, val = 0U;
int ret = 0;
nveu8_t *base = osi_core->base;
nveu32_t op_mode = 0U, val = 0U;
nve32_t ret = 0;
if ((enabled != OSI_ENABLE) && (enabled != OSI_DISABLE)) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID,
@@ -1016,11 +1016,11 @@ frp_enable_re:
* @retval 0 on success
* @retval -1 on failure.
*/
static int eqos_update_frp_nve(struct osi_core_priv_data *const osi_core,
const unsigned int nve)
static nve32_t eqos_update_frp_nve(struct osi_core_priv_data *const osi_core,
const nveu32_t nve)
{
unsigned int val;
unsigned char *base = osi_core->base;
nveu32_t val;
nveu8_t *base = osi_core->base;
/* Validate the NVE value */
if (nve >= OSI_FRP_MAX_ENTRY) {
@@ -1056,13 +1056,13 @@ static int eqos_update_frp_nve(struct osi_core_priv_data *const osi_core,
* @retval 0 on success
* @retval -1 on failure.
*/
static int eqos_frp_write(struct osi_core_priv_data *osi_core,
unsigned int addr,
unsigned int data)
static nve32_t eqos_frp_write(struct osi_core_priv_data *osi_core,
nveu32_t addr,
nveu32_t data)
{
int ret = 0;
unsigned char *base = osi_core->base;
unsigned int val = 0U;
nve32_t ret = 0;
nveu8_t *base = osi_core->base;
nveu32_t val = 0U;
/* Wait for ready */
ret = osi_readl_poll_timeout((base + EQOS_MTL_RXP_IND_CS),
@@ -1125,12 +1125,12 @@ static int eqos_frp_write(struct osi_core_priv_data *osi_core,
* @retval 0 on success
* @retval -1 on failure.
*/
static int eqos_update_frp_entry(struct osi_core_priv_data *const osi_core,
const unsigned int pos,
static nve32_t eqos_update_frp_entry(struct osi_core_priv_data *const osi_core,
const nveu32_t pos,
struct osi_core_frp_data *const data)
{
unsigned int val = 0U, tmp = 0U;
int ret = -1;
nveu32_t val = 0U, tmp = 0U;
nve32_t ret = -1;
/* Validate pos value */
if (pos >= OSI_FRP_MAX_ENTRY) {
@@ -1283,7 +1283,7 @@ static void eqos_configure_rxq_priority(
* @retval 0 on success
* @retval -1 on failure
*/
static int eqos_hsi_configure(struct osi_core_priv_data *const osi_core,
static nve32_t eqos_hsi_configure(struct osi_core_priv_data *const osi_core,
const nveu32_t enable)
{
nveu32_t value;
@@ -1638,10 +1638,10 @@ static void eqos_configure_dma(struct osi_core_priv_data *const osi_core)
static inline void eqos_enable_mtl_interrupts(
struct osi_core_priv_data *const osi_core)
{
unsigned int mtl_est_ir = OSI_DISABLE;
nveu32_t mtl_est_ir = OSI_DISABLE;
void *addr = osi_core->base;
mtl_est_ir = osi_readla(osi_core, (unsigned char *)
mtl_est_ir = osi_readla(osi_core, (nveu8_t *)
addr + EQOS_MTL_EST_ITRE);
/* enable only MTL interrupt realted to
* Constant Gate Control Error
@@ -1654,7 +1654,7 @@ static inline void eqos_enable_mtl_interrupts(
EQOS_MTL_EST_ITRE_IEHF | EQOS_MTL_EST_ITRE_IEBE |
EQOS_MTL_EST_ITRE_IECC);
osi_writela(osi_core, mtl_est_ir,
(unsigned char *)addr + EQOS_MTL_EST_ITRE);
(nveu8_t *)addr + EQOS_MTL_EST_ITRE);
}
/**
@@ -1669,14 +1669,14 @@ static inline void eqos_enable_mtl_interrupts(
static inline void eqos_enable_fpe_interrupts(
struct osi_core_priv_data *const osi_core)
{
unsigned int value = OSI_DISABLE;
nveu32_t value = OSI_DISABLE;
void *addr = osi_core->base;
/* Read MAC IER Register and enable Frame Preemption Interrupt
* Enable */
value = osi_readla(osi_core, (unsigned char *)addr + EQOS_MAC_IMR);
value = osi_readla(osi_core, (nveu8_t *)addr + EQOS_MAC_IMR);
value |= EQOS_IMR_FPEIE;
osi_writela(osi_core, value, (unsigned char *)addr + EQOS_MAC_IMR);
osi_writela(osi_core, value, (nveu8_t *)addr + EQOS_MAC_IMR);
}
/**
@@ -1689,11 +1689,11 @@ static inline void eqos_enable_fpe_interrupts(
static inline void eqos_save_gcl_params(struct osi_core_priv_data *osi_core)
{
struct core_local *l_core = (struct core_local *)osi_core;
unsigned int gcl_widhth[4] = {0, OSI_MAX_24BITS, OSI_MAX_28BITS,
nveu32_t gcl_widhth[4] = {0, OSI_MAX_24BITS, OSI_MAX_28BITS,
OSI_MAX_32BITS};
nveu32_t gcl_ti_mask[4] = {0, OSI_MASK_16BITS, OSI_MASK_20BITS,
OSI_MASK_24BITS};
unsigned int gcl_depthth[6] = {0, OSI_GCL_SIZE_64, OSI_GCL_SIZE_128,
nveu32_t gcl_depthth[6] = {0, OSI_GCL_SIZE_64, OSI_GCL_SIZE_128,
OSI_GCL_SIZE_256, OSI_GCL_SIZE_512,
OSI_GCL_SIZE_1024};
@@ -1701,7 +1701,7 @@ static inline void eqos_save_gcl_params(struct osi_core_priv_data *osi_core)
(osi_core->hw_feature->gcl_width > 3U)) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID,
"Wrong HW feature GCL width\n",
(unsigned long long)osi_core->hw_feature->gcl_width);
(nveul64_t)osi_core->hw_feature->gcl_width);
} else {
l_core->gcl_width_val =
gcl_widhth[osi_core->hw_feature->gcl_width];
@@ -1713,7 +1713,7 @@ static inline void eqos_save_gcl_params(struct osi_core_priv_data *osi_core)
/* Do Nothing */
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID,
"Wrong HW feature GCL depth\n",
(unsigned long long)osi_core->hw_feature->gcl_depth);
(nveul64_t)osi_core->hw_feature->gcl_depth);
} else {
l_core->gcl_dep = gcl_depthth[osi_core->hw_feature->gcl_depth];
}
@@ -1737,14 +1737,14 @@ static inline void eqos_save_gcl_params(struct osi_core_priv_data *osi_core)
* @note MAC should be init and started. see osi_start_mac()
*/
static void eqos_tsn_init(struct osi_core_priv_data *osi_core,
unsigned int est_sel, unsigned int fpe_sel)
nveu32_t est_sel, nveu32_t fpe_sel)
{
unsigned int val = 0x0;
unsigned int temp = 0U;
nveu32_t val = 0x0;
nveu32_t temp = 0U;
if (est_sel == OSI_ENABLE) {
eqos_save_gcl_params(osi_core);
val = osi_readla(osi_core, (unsigned char *)osi_core->base +
val = osi_readla(osi_core, (nveu8_t *)osi_core->base +
EQOS_MTL_EST_CONTROL);
/*
@@ -1789,14 +1789,14 @@ static void eqos_tsn_init(struct osi_core_priv_data *osi_core,
}
if (fpe_sel == OSI_ENABLE) {
val = osi_readla(osi_core, (unsigned char *)osi_core->base +
val = osi_readla(osi_core, (nveu8_t *)osi_core->base +
EQOS_MAC_RQC1R);
val &= ~EQOS_MAC_RQC1R_FPRQ;
temp = osi_core->residual_queue;
temp = temp << EQOS_MAC_RQC1R_FPRQ_SHIFT;
temp = (temp & EQOS_MAC_RQC1R_FPRQ);
val |= temp;
osi_writela(osi_core, val, (unsigned char *)osi_core->base +
osi_writela(osi_core, val, (nveu8_t *)osi_core->base +
EQOS_MAC_RQC1R);
eqos_enable_fpe_interrupts(osi_core);
@@ -2019,11 +2019,11 @@ static nve32_t eqos_core_init(struct osi_core_priv_data *const osi_core,
*/
static void eqos_handle_mac_fpe_intrs(struct osi_core_priv_data *osi_core)
{
unsigned int val = 0;
nveu32_t val = 0;
/* interrupt bit clear on read as CSR_SW is reset */
val = osi_readla(osi_core,
(unsigned char *)osi_core->base + EQOS_MAC_FPE_CTS);
(nveu8_t *)osi_core->base + EQOS_MAC_FPE_CTS);
if ((val & EQOS_MAC_FPE_CTS_RVER) == EQOS_MAC_FPE_CTS_RVER) {
val &= ~EQOS_MAC_FPE_CTS_RVER;
@@ -2057,7 +2057,7 @@ static void eqos_handle_mac_fpe_intrs(struct osi_core_priv_data *osi_core)
}
osi_writela(osi_core, val,
(unsigned char *)osi_core->base + EQOS_MAC_FPE_CTS);
(nveu8_t *)osi_core->base + EQOS_MAC_FPE_CTS);
}
#endif /* !OSI_STRIPPED_LIB */
@@ -2258,16 +2258,16 @@ static inline void update_dma_sr_stats(
*/
static void eqos_handle_mtl_intrs(struct osi_core_priv_data *osi_core)
{
unsigned int val = 0U;
unsigned int sch_err = 0U;
unsigned int frm_err = 0U;
unsigned int temp = 0U;
unsigned int i = 0;
unsigned long stat_val = 0U;
unsigned int value = 0U;
nveu32_t val = 0U;
nveu32_t sch_err = 0U;
nveu32_t frm_err = 0U;
nveu32_t temp = 0U;
nveu32_t i = 0;
nveu64_t stat_val = 0U;
nveu32_t value = 0U;
val = osi_readla(osi_core,
(unsigned char *)osi_core->base + EQOS_MTL_EST_STATUS);
(nveu8_t *)osi_core->base + EQOS_MTL_EST_STATUS);
val &= (EQOS_MTL_EST_STATUS_CGCE | EQOS_MTL_EST_STATUS_HLBS |
EQOS_MTL_EST_STATUS_HLBF | EQOS_MTL_EST_STATUS_BTRE |
EQOS_MTL_EST_STATUS_SWLC);
@@ -2550,24 +2550,24 @@ static void eqos_handle_common_intr(struct osi_core_priv_data *const osi_core)
#ifndef OSI_STRIPPED_LIB
/* Handle MTL inerrupts */
mtl_isr = osi_readla(osi_core,
(unsigned char *)base + EQOS_MTL_INTR_STATUS);
(nveu8_t *)base + EQOS_MTL_INTR_STATUS);
if (((mtl_isr & EQOS_MTL_IS_ESTIS) == EQOS_MTL_IS_ESTIS) &&
((dma_isr & EQOS_DMA_ISR_MTLIS) == EQOS_DMA_ISR_MTLIS)) {
eqos_handle_mtl_intrs(osi_core);
mtl_isr &= ~EQOS_MTL_IS_ESTIS;
osi_writela(osi_core, mtl_isr, (unsigned char *)base +
osi_writela(osi_core, mtl_isr, (nveu8_t *)base +
EQOS_MTL_INTR_STATUS);
}
/* Clear FRP Interrupt MTL_RXP_Interrupt_Control_Status */
frp_isr = osi_readla(osi_core,
(unsigned char *)base + EQOS_MTL_RXP_INTR_CS);
(nveu8_t *)base + EQOS_MTL_RXP_INTR_CS);
frp_isr |= (EQOS_MTL_RXP_INTR_CS_NVEOVIS |
EQOS_MTL_RXP_INTR_CS_NPEOVIS |
EQOS_MTL_RXP_INTR_CS_FOOVIS |
EQOS_MTL_RXP_INTR_CS_PDRFIS);
osi_writela(osi_core, frp_isr,
(unsigned char *)base + EQOS_MTL_RXP_INTR_CS);
(nveu8_t *)base + EQOS_MTL_RXP_INTR_CS);
#endif /* !OSI_STRIPPED_LIB */
}
@@ -3100,14 +3100,14 @@ static nve32_t eqos_update_ip4_addr(struct osi_core_priv_data *const osi_core,
* @retval 0 on success
* @retval -1 on failure.
*/
static int eqos_config_ptp_offload(struct osi_core_priv_data *const osi_core,
static nve32_t eqos_config_ptp_offload(struct osi_core_priv_data *const osi_core,
struct osi_pto_config *const pto_config)
{
unsigned char *addr = (unsigned char *)osi_core->base;
int ret = 0;
unsigned int value = 0x0U;
unsigned int ptc_value = 0x0U;
unsigned int port_id = 0x0U;
nveu8_t *addr = (nveu8_t *)osi_core->base;
nve32_t ret = 0;
nveu32_t value = 0x0U;
nveu32_t ptc_value = 0x0U;
nveu32_t port_id = 0x0U;
/* Read MAC TCR */
value = osi_readla(osi_core, (nveu8_t *)addr + EQOS_MAC_TCR);
@@ -3903,12 +3903,12 @@ static nve32_t eqos_adjust_mactime(struct osi_core_priv_data *const osi_core,
* @retval -1 on failure.
*/
static nve32_t eqos_config_ptp_rxq(struct osi_core_priv_data *const osi_core,
const unsigned int rxq_idx,
const unsigned int enable)
const nveu32_t rxq_idx,
const nveu32_t enable)
{
unsigned char *base = osi_core->base;
unsigned int value = OSI_NONE;
unsigned int i = 0U;
nveu8_t *base = osi_core->base;
nveu32_t value = OSI_NONE;
nveu32_t i = 0U;
/* Validate the RX queue index argment */
if (rxq_idx >= OSI_EQOS_MAX_NUM_QUEUES) {
@@ -4018,26 +4018,26 @@ static void eqos_core_deinit(struct osi_core_priv_data *const osi_core)
* @retval 0 on success
* @retval -1 on failure.
*/
static int eqos_hw_est_write(struct osi_core_priv_data *osi_core,
unsigned int addr_val,
unsigned int data, unsigned int gcla)
static nve32_t eqos_hw_est_write(struct osi_core_priv_data *osi_core,
nveu32_t addr_val,
nveu32_t data, nveu32_t gcla)
{
void *base = osi_core->base;
int retry = 1000;
unsigned int val = 0x0;
nve32_t retry = 1000;
nveu32_t val = 0x0;
osi_writela(osi_core, data, (unsigned char *)base + EQOS_MTL_EST_DATA);
osi_writela(osi_core, data, (nveu8_t *)base + EQOS_MTL_EST_DATA);
val &= ~EQOS_MTL_EST_ADDR_MASK;
val |= (gcla == 1U) ? 0x0U : EQOS_MTL_EST_GCRR;
val |= EQOS_MTL_EST_SRWO;
val |= addr_val;
osi_writela(osi_core, val,
(unsigned char *)base + EQOS_MTL_EST_GCL_CONTROL);
(nveu8_t *)base + EQOS_MTL_EST_GCL_CONTROL);
while (--retry > 0) {
osi_core->osd_ops.udelay(OSI_DELAY_1US);
val = osi_readla(osi_core, (unsigned char *)base +
val = osi_readla(osi_core, (nveu8_t *)base +
EQOS_MTL_EST_GCL_CONTROL);
if ((val & EQOS_MTL_EST_SRWO) == EQOS_MTL_EST_SRWO) {
continue;
@@ -4077,15 +4077,15 @@ static int eqos_hw_est_write(struct osi_core_priv_data *osi_core,
* @retval 0 on success
* @retval -1 on failure.
*/
static int eqos_hw_config_est(struct osi_core_priv_data *const osi_core,
static nve32_t eqos_hw_config_est(struct osi_core_priv_data *const osi_core,
struct osi_est_config *const est)
{
void *base = osi_core->base;
unsigned int btr[2] = {0};
unsigned int val = 0x0;
unsigned int addr = 0x0;
unsigned int i;
int ret = 0;
nveu32_t btr[2] = {0};
nveu32_t val = 0x0;
nveu32_t addr = 0x0;
nveu32_t i;
nve32_t ret = 0;
if ((osi_core->hw_feature != OSI_NULL) &&
(osi_core->hw_feature->est_sel == OSI_DISABLE)) {
@@ -4161,7 +4161,7 @@ static int eqos_hw_config_est(struct osi_core_priv_data *const osi_core,
if (ret < 0) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID,
"GCL enties write failed\n",
(unsigned long long)i);
(nveul64_t)i);
return ret;
}
}
@@ -4172,7 +4172,7 @@ static int eqos_hw_config_est(struct osi_core_priv_data *const osi_core,
if (ret < 0) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID,
"GCL BTR[0] failed\n",
(unsigned long long)(btr[0] +
(nveul64_t)(btr[0] +
est->btr_offset[0]));
return ret;
}
@@ -4182,12 +4182,12 @@ static int eqos_hw_config_est(struct osi_core_priv_data *const osi_core,
if (ret < 0) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_INVALID,
"GCL BTR[1] failed\n",
(unsigned long long)(btr[1] +
(nveul64_t)(btr[1] +
est->btr_offset[1]));
return ret;
}
val = osi_readla(osi_core, (unsigned char *)
val = osi_readla(osi_core, (nveu8_t *)
base + EQOS_MTL_EST_CONTROL);
/* Store table */
val |= EQOS_MTL_EST_CONTROL_SSWL;
@@ -4214,13 +4214,13 @@ static int eqos_hw_config_est(struct osi_core_priv_data *const osi_core,
* @retval 0 on success
* @retval -1 on failure.
*/
static int eqos_hw_config_fpe(struct osi_core_priv_data *const osi_core,
static nve32_t eqos_hw_config_fpe(struct osi_core_priv_data *const osi_core,
struct osi_fpe_config *const fpe)
{
unsigned int i = 0U;
unsigned int val = 0U;
unsigned int temp = 0U, temp1 = 0U;
unsigned int temp_shift = 0U;
nveu32_t i = 0U;
nveu32_t val = 0U;
nveu32_t temp = 0U, temp1 = 0U;
nveu32_t temp_shift = 0U;
if ((osi_core->hw_feature != OSI_NULL) &&
(osi_core->hw_feature->fpe_sel == OSI_DISABLE)) {
@@ -4280,7 +4280,7 @@ static int eqos_hw_config_fpe(struct osi_core_priv_data *const osi_core,
}
val = osi_readla(osi_core,
(unsigned char *)osi_core->base + EQOS_MAC_RQC1R);
(nveu8_t *)osi_core->base + EQOS_MAC_RQC1R);
val &= ~EQOS_MAC_RQC1R_FPRQ;
temp = fpe->rq;
temp = temp << EQOS_MAC_RQC1R_FPRQ_SHIFT;
@@ -4289,22 +4289,22 @@ static int eqos_hw_config_fpe(struct osi_core_priv_data *const osi_core,
/* update RQ in OSI CORE struct */
osi_core->residual_queue = fpe->rq;
osi_writela(osi_core, val,
(unsigned char *)osi_core->base + EQOS_MAC_RQC1R);
(nveu8_t *)osi_core->base + EQOS_MAC_RQC1R);
/* initiate SVER for SMD-V and SMD-R */
val = osi_readla(osi_core,
(unsigned char *)osi_core->base + EQOS_MTL_FPE_CTS);
(nveu8_t *)osi_core->base + EQOS_MTL_FPE_CTS);
val |= EQOS_MAC_FPE_CTS_SVER;
osi_writela(osi_core, val,
(unsigned char *)osi_core->base + EQOS_MAC_FPE_CTS);
(nveu8_t *)osi_core->base + EQOS_MAC_FPE_CTS);
val = osi_readla(osi_core,
(unsigned char *)osi_core->base + EQOS_MTL_FPE_ADV);
(nveu8_t *)osi_core->base + EQOS_MTL_FPE_ADV);
val &= ~EQOS_MTL_FPE_ADV_HADV_MASK;
/* (minimum_fragment_size +IPG/EIPG + Preamble) *.8 ~98ns for10G */
val |= EQOS_MTL_FPE_ADV_HADV_VAL;
osi_writela(osi_core, val,
(unsigned char *)osi_core->base + EQOS_MTL_FPE_ADV);
(nveu8_t *)osi_core->base + EQOS_MTL_FPE_ADV);
return 0;
}
@@ -5636,8 +5636,8 @@ static nve32_t eqos_get_hw_features(struct osi_core_priv_data *const osi_core,
* @retval 0 on success
* @retval -1 on failure.
*/
static int eqos_padctl_rx_pins(struct osi_core_priv_data *const osi_core,
unsigned int enable)
static nve32_t eqos_padctl_rx_pins(struct osi_core_priv_data *const osi_core,
nveu32_t enable)
{
nveu32_t value;
void *pad_addr = osi_core->padctrl.padctrl_base;
@@ -5672,7 +5672,7 @@ static int eqos_padctl_rx_pins(struct osi_core_priv_data *const osi_core,
osi_writela(osi_core, value, (nveu8_t *)pad_addr +
osi_core->padctrl.offset_rd3);
} else {
value = osi_readla(osi_core, (unsigned char *)pad_addr +
value = osi_readla(osi_core, (nveu8_t *)pad_addr +
osi_core->padctrl.offset_rx_ctl);
value &= ~EQOS_PADCTL_EQOS_E_INPUT;
osi_writela(osi_core, value, (nveu8_t *)pad_addr +
@@ -5714,7 +5714,7 @@ static int eqos_padctl_rx_pins(struct osi_core_priv_data *const osi_core,
* @retval 0 on success
* @retval -1 on failure.
*/
static inline int poll_for_mac_tx_rx_idle(struct osi_core_priv_data *osi_core)
static inline nve32_t poll_for_mac_tx_rx_idle(struct osi_core_priv_data *osi_core)
{
nveu32_t retry = 0;
nveu32_t mac_debug;
@@ -5761,7 +5761,7 @@ static inline int poll_for_mac_tx_rx_idle(struct osi_core_priv_data *osi_core)
* @retval negative value on failure.
*/
static int eqos_pre_pad_calibrate(struct osi_core_priv_data *const osi_core)
static nve32_t eqos_pre_pad_calibrate(struct osi_core_priv_data *const osi_core)
{
nve32_t ret = 0;
nveu32_t value;
@@ -5806,7 +5806,7 @@ error:
/* Enable MAC RGSMIIIE - RGMII/SMII interrupts */
/* Read MAC IMR Register */
value = osi_readl((unsigned char *)osi_core->base + EQOS_MAC_IMR);
value = osi_readl((nveu8_t *)osi_core->base + EQOS_MAC_IMR);
value |= EQOS_IMR_RGSMIIIE;
eqos_core_safety_writel(osi_core, value, (nveu8_t *)osi_core->base +
EQOS_MAC_IMR, EQOS_MAC_IMR_IDX);

12
osi/core/eqos_core.h
View File

@@ -543,18 +543,18 @@
#define EQOS_MTL_EST_GCRR OSI_BIT(2)
#define EQOS_MTL_EST_ERR0 OSI_BIT(20)
/* EST GCRA addresses */
#define EQOS_MTL_EST_BTR_LOW ((unsigned int)0x0 << \
#define EQOS_MTL_EST_BTR_LOW ((nveu32_t)0x0 << \
EQOS_MTL_EST_ADDR_SHIFT)
#define EQOS_MTL_EST_BTR_HIGH ((unsigned int)0x1 << \
#define EQOS_MTL_EST_BTR_HIGH ((nveu32_t)0x1 << \
EQOS_MTL_EST_ADDR_SHIFT)
#define EQOS_MTL_EST_CTR_LOW ((unsigned int)0x2 << \
#define EQOS_MTL_EST_CTR_LOW ((nveu32_t)0x2 << \
EQOS_MTL_EST_ADDR_SHIFT)
#define EQOS_MTL_EST_CTR_HIGH ((unsigned int)0x3 << \
#define EQOS_MTL_EST_CTR_HIGH ((nveu32_t)0x3 << \
EQOS_MTL_EST_ADDR_SHIFT)
#define EQOS_MTL_EST_CTR_HIGH_MAX 0xFFU
#define EQOS_MTL_EST_TER ((unsigned int)0x4 << \
#define EQOS_MTL_EST_TER ((nveu32_t)0x4 << \
EQOS_MTL_EST_ADDR_SHIFT)
#define EQOS_MTL_EST_LLR ((unsigned int)0x5 << \
#define EQOS_MTL_EST_LLR ((nveu32_t)0x5 << \
EQOS_MTL_EST_ADDR_SHIFT)
/*EST MTL interrupt STATUS and ERR*/
#define EQOS_MTL_IS_ESTIS OSI_BIT(18)

134
osi/core/frp.c
View File

@@ -62,12 +62,12 @@ static void frp_entry_copy(struct osi_core_frp_entry *dst,
* @retval 0 on success.
* @retval -1 on failure.
*/
static int frp_entry_find(struct osi_core_priv_data *const osi_core,
int frp_id,
unsigned char *start,
unsigned char *no_entries)
static nve32_t frp_entry_find(struct osi_core_priv_data *const osi_core,
nve32_t frp_id,
nveu8_t *start,
nveu8_t *no_entries)
{
unsigned char count = OSI_NONE, found = OSI_NONE;
nveu8_t count = OSI_NONE, found = OSI_NONE;
struct osi_core_frp_entry *entry = OSI_NULL;
/* Parse the FRP table for give frp_id */
@@ -81,7 +81,7 @@ static int frp_entry_find(struct osi_core_priv_data *const osi_core,
found = OSI_ENABLE;
} else {
/* Increment entries */
*no_entries = (unsigned char) (*no_entries + 1U);
*no_entries = (nveu8_t) (*no_entries + 1U);
}
}
}
@@ -105,10 +105,10 @@ static int frp_entry_find(struct osi_core_priv_data *const osi_core,
*
* @retval No of FRP entries required.
*/
static unsigned char frp_req_entries(unsigned char offset,
unsigned char match_length)
static nveu8_t frp_req_entries(nveu8_t offset,
nveu8_t match_length)
{
unsigned char req = 0U;
nveu8_t req = 0U;
/* Validate for match_length */
if ((match_length == OSI_NONE) ||
@@ -118,18 +118,18 @@ static unsigned char frp_req_entries(unsigned char offset,
}
/* Check does the given length can fit in fist entry */
if (match_length <= (unsigned char) FRP_OFFSET_BYTES(offset)) {
if (match_length <= (nveu8_t) FRP_OFFSET_BYTES(offset)) {
/* Require one entry */
return 1U;
}
/* Initialize req as 1U and decrement length by FRP_OFFSET_BYTES */
req = 1U;
match_length = (unsigned char) (match_length - (unsigned char) FRP_OFFSET_BYTES(offset));
match_length = (nveu8_t) (match_length - (nveu8_t) FRP_OFFSET_BYTES(offset));
if ((match_length / FRP_MD_SIZE) < OSI_FRP_MATCH_DATA_MAX) {
req = (unsigned char) (req + (match_length / FRP_MD_SIZE));
req = (nveu8_t) (req + (match_length / FRP_MD_SIZE));
if ((match_length % FRP_MD_SIZE) != OSI_NONE) {
/* Need one more entry */
req = (unsigned char) (req + 1U);
req = (nveu8_t) (req + 1U);
}
}
@@ -145,7 +145,7 @@ static unsigned char frp_req_entries(unsigned char offset,
* @param[in] data: FRP entry data pointer.
*
*/
static void frp_entry_mode_parse(unsigned char filter_mode,
static void frp_entry_mode_parse(nveu8_t filter_mode,
struct osi_core_frp_data *data)
{
switch (filter_mode) {
@@ -216,23 +216,23 @@ static void frp_entry_mode_parse(unsigned char filter_mode,
* @retval 0 on success.
* @retval -1 on failure.
*/
static int frp_entry_add(struct osi_core_priv_data *const osi_core,
int frp_id,
unsigned char pos,
unsigned char *const match,
unsigned char length,
unsigned char offset,
unsigned char filter_mode,
int next_frp_id,
unsigned int dma_sel)
static nve32_t frp_entry_add(struct osi_core_priv_data *const osi_core,
nve32_t frp_id,
nveu8_t pos,
nveu8_t *const match,
nveu8_t length,
nveu8_t offset,
nveu8_t filter_mode,
nve32_t next_frp_id,
nveu32_t dma_sel)
{
struct osi_core_frp_entry *entry = OSI_NULL;
struct osi_core_frp_data *data = OSI_NULL;
unsigned int req_entries = 0U;
unsigned char ok_index = 0U;
unsigned char fo_t = 0U;
unsigned char fp_t = 0U;
unsigned char i = 0U, j = 0U, md_pos = 0U;
nveu32_t req_entries = 0U;
nveu8_t ok_index = 0U;
nveu8_t fo_t = 0U;
nveu8_t fp_t = 0U;
nveu8_t i = 0U, j = 0U, md_pos = 0U;
/* Validate length */
if (length > OSI_FRP_MATCH_DATA_MAX) {
@@ -275,7 +275,7 @@ static int frp_entry_add(struct osi_core_priv_data *const osi_core,
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
"No Link FRP ID index found\n",
OSI_NONE);
i = (unsigned char) next_frp_id;
i = (nveu8_t) next_frp_id;
}
ok_index = i;
}
@@ -296,9 +296,9 @@ static int frp_entry_add(struct osi_core_priv_data *const osi_core,
data->match_data = OSI_NONE;
data->match_en = OSI_NONE;
for (j = fp_t; j < FRP_MD_SIZE; j++) {
data->match_data |= ((unsigned int)match[md_pos])
data->match_data |= ((nveu32_t)match[md_pos])
<< (j * FRP_ME_BYTE_SHIFT);
data->match_en |= ((unsigned int)FRP_ME_BYTE <<
data->match_en |= ((nveu32_t)FRP_ME_BYTE <<
(j * FRP_ME_BYTE_SHIFT));
md_pos++;
if (md_pos >= length) {
@@ -355,12 +355,12 @@ static int frp_entry_add(struct osi_core_priv_data *const osi_core,
* @retval 0 on success.
* @retval -1 on failure.
*/
static int frp_hw_write(struct osi_core_priv_data *const osi_core,
static nve32_t frp_hw_write(struct osi_core_priv_data *const osi_core,
struct core_ops *ops_p)
{
int ret = -1, tmp = -1;
nve32_t ret = -1, tmp = -1;
struct osi_core_frp_entry *entry;
unsigned int frp_cnt = osi_core->frp_cnt, i = OSI_NONE;
nveu32_t frp_cnt = osi_core->frp_cnt, i = OSI_NONE;
/* Disable the FRP in HW */
ret = ops_p->config_frp(osi_core, OSI_DISABLE);
@@ -410,17 +410,17 @@ hw_write_enable_frp:
* @retval 0 on success.
* @retval -1 on failure.
*/
static int frp_add_proto(struct osi_core_priv_data *const osi_core,
static nve32_t frp_add_proto(struct osi_core_priv_data *const osi_core,
struct osi_core_frp_cmd *const cmd,
unsigned char *pos)
nveu8_t *pos)
{
int ret = -1, proto_oki = -1;
unsigned char proto_entry = OSI_DISABLE;
unsigned char req = 0U;
unsigned char proto_match[FRP_PROTO_LENGTH];
unsigned char proto_lendth;
unsigned char proto_offset;
unsigned char match_type = cmd->match_type;
nve32_t ret = -1, proto_oki = -1;
nveu8_t proto_entry = OSI_DISABLE;
nveu8_t req = 0U;
nveu8_t proto_match[FRP_PROTO_LENGTH];
nveu8_t proto_lendth;
nveu8_t proto_offset;
nveu8_t match_type = cmd->match_type;
switch (match_type) {
case OSI_FRP_MATCH_L4_S_UPORT:
@@ -463,7 +463,7 @@ static int frp_add_proto(struct osi_core_priv_data *const osi_core,
/* Check and Add protocol FRP entire */
if (proto_entry == OSI_ENABLE) {
/* Check for space */
req = (unsigned char) (frp_req_entries(cmd->offset, cmd->match_length) + 1U);
req = (nveu8_t) (frp_req_entries(cmd->offset, cmd->match_length) + 1U);
if (*pos > (OSI_FRP_MAX_ENTRY - req)) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
"Fail add FRP protocol entry\n",
@@ -485,7 +485,7 @@ static int frp_add_proto(struct osi_core_priv_data *const osi_core,
}
/* Increment pos value */
*pos = (unsigned char) (*pos + 1U);
*pos = (nveu8_t) (*pos + 1U);
}
return 0;
@@ -503,8 +503,8 @@ static int frp_add_proto(struct osi_core_priv_data *const osi_core,
static void frp_parse_mtype(OSI_UNUSED struct osi_core_priv_data *const osi_core,
struct osi_core_frp_cmd *const cmd)
{
unsigned char offset;
unsigned char match_type = cmd->match_type;
nveu8_t offset;
nveu8_t match_type = cmd->match_type;
switch (match_type) {
case OSI_FRP_MATCH_L2_DA:
@@ -555,14 +555,14 @@ static void frp_parse_mtype(OSI_UNUSED struct osi_core_priv_data *const osi_core
* @retval 0 on success.
* @retval -1 on failure.
*/
static int frp_delete(struct osi_core_priv_data *const osi_core,
static nve32_t frp_delete(struct osi_core_priv_data *const osi_core,
struct core_ops *ops_p,
struct osi_core_frp_cmd *const cmd)
{
int ret = -1;
unsigned char i = 0U, pos = 0U, count = 0U;
int frp_id = cmd->frp_id;
unsigned int frp_cnt = osi_core->frp_cnt;
nve32_t ret = -1;
nveu8_t i = 0U, pos = 0U, count = 0U;
nve32_t frp_id = cmd->frp_id;
nveu32_t frp_cnt = osi_core->frp_cnt;
/* Check for FRP entries */
if (frp_cnt == 0U) {
@@ -581,7 +581,7 @@ static int frp_delete(struct osi_core_priv_data *const osi_core,
}
/* Validate pos and count */
if (((unsigned int)pos + count) > frp_cnt) {
if (((nveu32_t)pos + count) > frp_cnt) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
"Invalid FRP entry index\n",
OSI_NONE);
@@ -593,7 +593,7 @@ static int frp_delete(struct osi_core_priv_data *const osi_core,
(sizeof(struct osi_core_frp_entry) * count));
/* Move in FRP table entries by count */
for (i = (unsigned char) (pos + count); i <= frp_cnt; i++) {
for (i = (nveu8_t) (pos + count); i <= frp_cnt; i++) {
frp_entry_copy(&osi_core->frp_table[pos],
&osi_core->frp_table[i]);
pos++;
@@ -624,13 +624,13 @@ static int frp_delete(struct osi_core_priv_data *const osi_core,
* @retval 0 on success.
* @retval -1 on failure.
*/
static int frp_update(struct osi_core_priv_data *const osi_core,
static nve32_t frp_update(struct osi_core_priv_data *const osi_core,
struct core_ops *ops_p,
struct osi_core_frp_cmd *const cmd)
{
int ret = -1;
unsigned char pos = 0U, count = 0U, req = 0U;
int frp_id = cmd->frp_id;
nve32_t ret = -1;
nveu8_t pos = 0U, count = 0U, req = 0U;
nve32_t frp_id = cmd->frp_id;
/* Validate given frp_id */
if (frp_entry_find(osi_core, frp_id, &pos, &count) < 0) {
@@ -709,14 +709,14 @@ static int frp_update(struct osi_core_priv_data *const osi_core,
* @retval 0 on success.
* @retval -1 on failure.
*/
static int frp_add(struct osi_core_priv_data *const osi_core,
static nve32_t frp_add(struct osi_core_priv_data *const osi_core,
struct core_ops *ops_p,
struct osi_core_frp_cmd *const cmd)
{
int ret = -1;
unsigned char pos = 0U, count = 0U;
int frp_id = cmd->frp_id;
unsigned int nve = osi_core->frp_cnt;
nve32_t ret = -1;
nveu8_t pos = 0U, count = 0U;
nve32_t frp_id = cmd->frp_id;
nveu32_t nve = osi_core->frp_cnt;
/* Check for MAX FRP entries */
if (nve >= OSI_FRP_MAX_ENTRY) {
@@ -739,7 +739,7 @@ static int frp_add(struct osi_core_priv_data *const osi_core,
frp_parse_mtype(osi_core, cmd);
/* Process and add FRP Command Protocal Entry */
ret = frp_add_proto(osi_core, cmd, (unsigned char *)&nve);
ret = frp_add_proto(osi_core, cmd, (nveu8_t *)&nve);
if (ret < 0) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
"Fail to parse match type\n",
@@ -748,7 +748,7 @@ static int frp_add(struct osi_core_priv_data *const osi_core,
}
/* Add Match data FRP Entry */
ret = frp_entry_add(osi_core, frp_id, (unsigned char)nve,
ret = frp_entry_add(osi_core, frp_id, (nveu8_t)nve,
cmd->match, cmd->match_length,
cmd->offset, cmd->filter_mode,
cmd->next_frp_id, cmd->dma_sel);
@@ -783,11 +783,11 @@ static int frp_add(struct osi_core_priv_data *const osi_core,
* @retval 0 on success.
* @retval -1 on failure.
*/
int setup_frp(struct osi_core_priv_data *const osi_core,
nve32_t setup_frp(struct osi_core_priv_data *const osi_core,
struct core_ops *ops_p,
struct osi_core_frp_cmd *const cmd)
{
int ret = -1;
nve32_t ret = -1;
switch (cmd->cmd) {
case OSI_FRP_CMD_ADD:

4
osi/core/frp.h
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2020, NVIDIA CORPORATION. All rights reserved.
* Copyright (c) 2020-2022, NVIDIA CORPORATION. All rights reserved.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
@@ -65,7 +65,7 @@
* @retval 0 on success.
* @retval -1 on failure.
*/
int setup_frp(struct osi_core_priv_data *const osi_core,
nve32_t setup_frp(struct osi_core_priv_data *const osi_core,
struct core_ops *ops_p,
struct osi_core_frp_cmd *const cmd);

28
osi/core/ivc_core.c
View File

@@ -200,7 +200,7 @@ static nve32_t ivc_read_phy_reg(struct osi_core_priv_data *const osi_core,
* @retval 0 on success
* @retval -1 on failure.
*/
static int ivc_macsec_dbg_events_config(
static nve32_t ivc_macsec_dbg_events_config(
struct osi_core_priv_data *const osi_core,
struct osi_macsec_dbg_buf_config *const dbg_buf_config)
{
@@ -236,7 +236,7 @@ exit:
* @retval 0 on Success
* @retval -1 on Failure
*/
static int ivc_macsec_dbg_buf_config(
static nve32_t ivc_macsec_dbg_buf_config(
struct osi_core_priv_data *const osi_core,
struct osi_macsec_dbg_buf_config *const dbg_buf_config)
{
@@ -306,7 +306,7 @@ static void ivc_macsec_read_mmc(struct osi_core_priv_data *const osi_core)
* @retval 0 on Success
* @retval -1 on Failure
*/
static int ivc_get_sc_lut_key_index(struct osi_core_priv_data *const osi_core,
static nve32_t ivc_get_sc_lut_key_index(struct osi_core_priv_data *const osi_core,
nveu8_t *sci, nveu32_t *key_index,
nveu16_t ctlr)
{
@@ -342,10 +342,10 @@ static int ivc_get_sc_lut_key_index(struct osi_core_priv_data *const osi_core,
* @retval 0 on Success
* @retval -1 on Failure
*/
static int ivc_macsec_config(struct osi_core_priv_data *const osi_core,
static nve32_t ivc_macsec_config(struct osi_core_priv_data *const osi_core,
struct osi_macsec_sc_info *const sc,
unsigned int enable, unsigned short ctlr,
unsigned short *kt_idx)
nveu32_t enable, nveu16_t ctlr,
nveu16_t *kt_idx)
{
ivc_msg_common_t msg;
nve32_t ret = 0;
@@ -379,8 +379,8 @@ exit:
* @retval 0 on Success
* @retval -1 on Failure
*/
static int ivc_macsec_enable(struct osi_core_priv_data *const osi_core,
unsigned int enable)
static nve32_t ivc_macsec_enable(struct osi_core_priv_data *const osi_core,
nveu32_t enable)
{
ivc_msg_common_t msg;
nveu32_t index = 0;
@@ -405,8 +405,8 @@ static int ivc_macsec_enable(struct osi_core_priv_data *const osi_core,
* @retval 0 on Success
* @retval -1 on Failure
*/
static int ivc_macsec_loopback_config(struct osi_core_priv_data *const osi_core,
unsigned int enable)
static nve32_t ivc_macsec_loopback_config(struct osi_core_priv_data *const osi_core,
nveu32_t enable)
{
ivc_msg_common_t msg;
nveu32_t index = 0;
@@ -466,8 +466,8 @@ static nve32_t ivc_macsec_kt_config(struct osi_core_priv_data *const osi_core,
* @retval 0 on Success
* @retval -1 on Failure
*/
static int ivc_macsec_cipher_config(struct osi_core_priv_data *const osi_core,
unsigned int cipher)
static nve32_t ivc_macsec_cipher_config(struct osi_core_priv_data *const osi_core,
nveu32_t cipher)
{
ivc_msg_common_t msg;
nveu32_t index = 0;
@@ -537,7 +537,7 @@ static void ivc_macsec_handle_irq(OSI_UNUSED
* @retval -1 on Failure
*/
static int ivc_macsec_deinit(struct osi_core_priv_data *const osi_core)
static nve32_t ivc_macsec_deinit(struct osi_core_priv_data *const osi_core)
{
ivc_msg_common_t msg;
@@ -557,7 +557,7 @@ static int ivc_macsec_deinit(struct osi_core_priv_data *const osi_core)
* @retval 0 on Success
* @retval -1 on Failure
*/
static int ivc_macsec_init(struct osi_core_priv_data *const osi_core,
static nve32_t ivc_macsec_init(struct osi_core_priv_data *const osi_core,
nveu32_t mtu)
{
ivc_msg_common_t msg;

716
osi/core/mgbe_core.c
View File

File diff suppressed because it is too large Load Diff

16
osi/core/mgbe_core.h
View File

@@ -33,7 +33,7 @@
* PHY should be up before the LPI pattern can be transmitted to the PHY.
* Default 1sec.
*/
#define MGBE_DEFAULT_LPI_LS_TIMER (unsigned int)1000
#define MGBE_DEFAULT_LPI_LS_TIMER ((nveu32_t)1000)
#define MGBE_LPI_LS_TIMER_MASK 0x3FFU
#define MGBE_LPI_LS_TIMER_SHIFT 16U
/* LPI TW timer - minimum time (in microseconds) for which MAC wait after it
@@ -491,7 +491,7 @@
#define MGBE_MAC_VLAN_TR_VTIM OSI_BIT(17)
#define MGBE_MAC_VLAN_TR_VTIM_SHIFT 17
#define MGBE_MAC_VLAN_TR_VTHM OSI_BIT(25)
#define MGBE_MAC_VLANTR_EVLS_ALWAYS_STRIP ((unsigned int)0x3 << 21U)
#define MGBE_MAC_VLANTR_EVLS_ALWAYS_STRIP ((nveu32_t)0x3 << 21U)
#define MGBE_MAC_VLANTR_EVLRXS OSI_BIT(24)
#define MGBE_MAC_VLANTR_DOVLTC OSI_BIT(20)
#define MGBE_MAC_VLANTIR_VLTI OSI_BIT(20)
@@ -627,18 +627,18 @@
#define MGBE_MTL_EST_GCRR OSI_BIT(2)
#define MGBE_MTL_EST_ERR0 OSI_BIT(20)
/* EST GCRA addresses */
#define MGBE_MTL_EST_BTR_LOW ((unsigned int)0x0 << \
#define MGBE_MTL_EST_BTR_LOW ((nveu32_t)0x0 << \
MGBE_MTL_EST_ADDR_SHIFT)
#define MGBE_MTL_EST_BTR_HIGH ((unsigned int)0x1 << \
#define MGBE_MTL_EST_BTR_HIGH ((nveu32_t)0x1 << \
MGBE_MTL_EST_ADDR_SHIFT)
#define MGBE_MTL_EST_CTR_LOW ((unsigned int)0x2 << \
#define MGBE_MTL_EST_CTR_LOW ((nveu32_t)0x2 << \
MGBE_MTL_EST_ADDR_SHIFT)
#define MGBE_MTL_EST_CTR_HIGH ((unsigned int)0x3 << \
#define MGBE_MTL_EST_CTR_HIGH ((nveu32_t)0x3 << \
MGBE_MTL_EST_ADDR_SHIFT)
#define MGBE_MTL_EST_CTR_HIGH_MAX 0xFFU
#define MGBE_MTL_EST_TER ((unsigned int)0x4 << \
#define MGBE_MTL_EST_TER ((nveu32_t)0x4 << \
MGBE_MTL_EST_ADDR_SHIFT)
#define MGBE_MTL_EST_LLR ((unsigned int)0x5 << \
#define MGBE_MTL_EST_LLR ((nveu32_t)0x5 << \
MGBE_MTL_EST_ADDR_SHIFT)
/*EST MTL interrupt STATUS and ERR*/
#define MGBE_MTL_IS_ESTIS OSI_BIT(18)

18
osi/core/mgbe_mmc.c
View File

@@ -43,12 +43,12 @@
* @retval 0 on MMC counters overflow
* @retval value on current MMC counter value.
*/
static inline unsigned long update_mmc_val(struct osi_core_priv_data *osi_core,
unsigned long last_value,
unsigned long offset)
static inline nveu64_t update_mmc_val(struct osi_core_priv_data *osi_core,
nveu64_t last_value,
nveu64_t offset)
{
unsigned long temp;
unsigned int value = osi_readl((unsigned char *)osi_core->base +
nveu64_t temp;
nveu32_t value = osi_readl((nveu8_t *)osi_core->base +
offset);
temp = last_value + value;
@@ -56,7 +56,7 @@ static inline unsigned long update_mmc_val(struct osi_core_priv_data *osi_core,
OSI_CORE_ERR(osi_core->osd,
OSI_LOG_ARG_OUTOFBOUND,
"Value overflow resetting all counters\n",
(unsigned long long)offset);
(nveul64_t)offset);
mgbe_reset_mmc(osi_core);
} else {
return temp;
@@ -77,12 +77,12 @@ static inline unsigned long update_mmc_val(struct osi_core_priv_data *osi_core,
*/
void mgbe_reset_mmc(struct osi_core_priv_data *const osi_core)
{
unsigned int value;
nveu32_t value;
value = osi_readl((unsigned char *)osi_core->base + MGBE_MMC_CNTRL);
value = osi_readl((nveu8_t *)osi_core->base + MGBE_MMC_CNTRL);
/* self-clear bit in one clock cycle */
value |= MGBE_MMC_CNTRL_CNTRST;
osi_writel(value, (unsigned char *)osi_core->base + MGBE_MMC_CNTRL);
osi_writel(value, (nveu8_t *)osi_core->base + MGBE_MMC_CNTRL);
osi_memset(&osi_core->mmc, 0U, sizeof(struct osi_mmc_counters));
}

10
osi/core/osi_hal.c
View File

@@ -214,7 +214,7 @@ static nve32_t osi_hal_init_core_ops(struct osi_core_priv_data *const osi_core)
*/
static inline void init_vlan_filters(struct osi_core_priv_data *const osi_core)
{
unsigned int i = 0U;
nveu32_t i = 0U;
for (i = 0; i < VLAN_NUM_VID; i++) {
osi_core->vid[i] = VLAN_ID_INVALID;
@@ -294,7 +294,7 @@ static nve32_t conf_ptp_offload(struct osi_core_priv_data *const osi_core,
struct osi_pto_config *const pto_config)
{
struct core_local *l_core = (struct core_local *)(void *)osi_core;
int ret = -1;
nve32_t ret = -1;
/* Validate input arguments */
if (pto_config == OSI_NULL) {
@@ -964,8 +964,8 @@ static nve32_t vlan_id_update(struct osi_core_priv_data *const osi_core,
const nveu32_t vid)
{
struct core_local *const l_core = (struct core_local *)(void *)osi_core;
unsigned int action = vid & VLAN_ACTION_MASK;
unsigned short vlan_id = (unsigned short)(vid & VLAN_VID_MASK);
nveu32_t action = vid & VLAN_ACTION_MASK;
nveu16_t vlan_id = (nveu16_t)(vid & VLAN_VID_MASK);
if ((osi_core->mac_ver == OSI_EQOS_MAC_4_10) ||
(osi_core->mac_ver == OSI_EQOS_MAC_5_00)) {
@@ -1067,7 +1067,7 @@ static nve32_t conf_eee(struct osi_core_priv_data *const osi_core,
* @retval 0 on success
* @retval -1 on failure.
*/
static int configure_frp(struct osi_core_priv_data *const osi_core,
static nve32_t configure_frp(struct osi_core_priv_data *const osi_core,
struct osi_core_frp_cmd *const cmd)
{
struct core_local *l_core = (struct core_local *)(void *)osi_core;

116
osi/core/vlan_filter.c
View File

@@ -36,11 +36,11 @@
* @return Index from VID array if match found.
* @return Return VLAN_HW_FILTER_FULL_IDX if not found.
*/
static inline unsigned int get_vlan_filter_idx(
static inline nveu32_t get_vlan_filter_idx(
struct osi_core_priv_data *osi_core,
unsigned short vlan_id)
nveu16_t vlan_id)
{
unsigned int vid_idx = VLAN_HW_FILTER_FULL_IDX;
nveu32_t vid_idx = VLAN_HW_FILTER_FULL_IDX;
unsigned long bitmap = osi_core->vf_bitmap;
unsigned long temp = 0U;
@@ -49,7 +49,7 @@ static inline unsigned int get_vlan_filter_idx(
if (osi_core->vid[temp] == vlan_id) {
/* vlan ID match found */
vid_idx = (unsigned int)temp;
vid_idx = (nveu32_t)temp;
break;
}
@@ -71,11 +71,11 @@ static inline unsigned int get_vlan_filter_idx(
*
* @return 0 on success
*/
static inline int allow_all_vid_tags(unsigned char *base,
unsigned int pass_all_vids)
static inline nve32_t allow_all_vid_tags(nveu8_t *base,
nveu32_t pass_all_vids)
{
unsigned int vlan_tag_reg = 0;
unsigned int hash_filter_reg = 0;
nveu32_t vlan_tag_reg = 0;
nveu32_t hash_filter_reg = 0;
vlan_tag_reg = osi_readl(base + MAC_VLAN_TAG_CTRL);
hash_filter_reg = osi_readl(base + MAC_VLAN_HASH_FILTER);
@@ -85,7 +85,7 @@ static inline int allow_all_vid_tags(unsigned char *base,
hash_filter_reg |= VLAN_HASH_ALLOW_ALL;
} else {
vlan_tag_reg &= ~MAC_VLAN_TAG_CTRL_VHTM;
hash_filter_reg &= (unsigned int) ~VLAN_HASH_ALLOW_ALL;
hash_filter_reg &= (nveu32_t) ~VLAN_HASH_ALLOW_ALL;
}
osi_writel(vlan_tag_reg, base + MAC_VLAN_TAG_CTRL);
@@ -108,11 +108,11 @@ static inline int allow_all_vid_tags(unsigned char *base,
* @return 0 on Success.
* @return negative value on failure
*/
static inline int is_vlan_id_enqueued(struct osi_core_priv_data *osi_core,
unsigned short vlan_id,
unsigned int *idx)
static inline nve32_t is_vlan_id_enqueued(struct osi_core_priv_data *osi_core,
nveu16_t vlan_id,
nveu32_t *idx)
{
unsigned int i = 0;
nveu32_t i = 0;
if (osi_core->vlan_filter_cnt == VLAN_HW_FILTER_FULL_IDX) {
/* No elements in SW queue to search */
@@ -141,11 +141,11 @@ static inline int is_vlan_id_enqueued(struct osi_core_priv_data *osi_core,
* @return 0 on success.
* @return negative value on failure.
*/
static inline int enqueue_vlan_id(struct osi_core_priv_data *osi_core,
unsigned short vlan_id)
static inline nve32_t enqueue_vlan_id(struct osi_core_priv_data *osi_core,
nveu16_t vlan_id)
{
int ret = 0;
unsigned int idx;
nve32_t ret = 0;
nveu32_t idx;
if (osi_core->vlan_filter_cnt == VLAN_NUM_VID) {
/* Entire SW queue full */
@@ -178,13 +178,13 @@ static inline int enqueue_vlan_id(struct osi_core_priv_data *osi_core,
* @return 0 on success.
* @return -1 on failure.
*/
static inline int poll_for_vlan_filter_reg_rw(
static inline nve32_t poll_for_vlan_filter_reg_rw(
struct osi_core_priv_data *osi_core)
{
unsigned int retry = 10;
unsigned int count;
unsigned int val = 0;
int cond = 1;
nveu32_t retry = 10;
nveu32_t count;
nveu32_t val = 0;
nve32_t cond = 1;
count = 0;
while (cond == 1) {
@@ -196,7 +196,7 @@ static inline int poll_for_vlan_filter_reg_rw(
count++;
val = osi_readl((unsigned char *)osi_core->base +
val = osi_readl((nveu8_t *)osi_core->base +
MAC_VLAN_TAG_CTRL);
if ((val & MAC_VLAN_TAG_CTRL_OB) == OSI_NONE) {
/* Set cond to 0 to exit loop */
@@ -223,17 +223,17 @@ static inline int poll_for_vlan_filter_reg_rw(
* @return 0 on success
* @return -1 on failure.
*/
static inline int update_vlan_filters(struct osi_core_priv_data *osi_core,
unsigned int vid_idx,
unsigned int val)
static inline nve32_t update_vlan_filters(struct osi_core_priv_data *osi_core,
nveu32_t vid_idx,
nveu32_t val)
{
unsigned char *base = (unsigned char *)osi_core->base;
int ret = 0;
nveu8_t *base = (nveu8_t *)osi_core->base;
nve32_t ret = 0;
osi_writel(val, base + MAC_VLAN_TAG_DATA);
val = osi_readl(base + MAC_VLAN_TAG_CTRL);
val &= (unsigned int) ~MAC_VLAN_TAG_CTRL_OFS_MASK;
val &= (nveu32_t) ~MAC_VLAN_TAG_CTRL_OFS_MASK;
val |= vid_idx << MAC_VLAN_TAG_CTRL_OFS_SHIFT;
val &= ~MAC_VLAN_TAG_CTRL_CT;
val |= MAC_VLAN_TAG_CTRL_OB;
@@ -260,13 +260,13 @@ static inline int update_vlan_filters(struct osi_core_priv_data *osi_core,
* @return 0 on success
* @return -1 on failure.
*/
static inline int add_vlan_id(struct osi_core_priv_data *osi_core,
static inline nve32_t add_vlan_id(struct osi_core_priv_data *osi_core,
struct core_ops *ops_p,
unsigned short vlan_id)
nveu16_t vlan_id)
{
unsigned int vid_idx = 0;
unsigned int val = 0;
int ret = 0;
nveu32_t vid_idx = 0;
nveu32_t val = 0;
nve32_t ret = 0;
/* Check if VLAN ID already programmed */
vid_idx = get_vlan_filter_idx(osi_core, vlan_id);
@@ -278,7 +278,7 @@ static inline int add_vlan_id(struct osi_core_priv_data *osi_core,
}
/* Get free index to add the VID */
vid_idx = (unsigned int) __builtin_ctzl(~osi_core->vf_bitmap);
vid_idx = (nveu32_t) __builtin_ctzl(~osi_core->vf_bitmap);
/* If there is no free filter index add into SW VLAN filter queue to store */
if (vid_idx == VLAN_HW_FILTER_FULL_IDX) {
/* Add VLAN ID to SW queue */
@@ -306,8 +306,8 @@ static inline int add_vlan_id(struct osi_core_priv_data *osi_core,
}
}
val = osi_readl((unsigned char *)osi_core->base + MAC_VLAN_TAG_DATA);
val &= (unsigned int) ~VLAN_VID_MASK;
val = osi_readl((nveu8_t *)osi_core->base + MAC_VLAN_TAG_DATA);
val &= (nveu32_t) ~VLAN_VID_MASK;
val |= (vlan_id | MAC_VLAN_TAG_DATA_ETV | MAC_VLAN_TAG_DATA_VEN);
return update_vlan_filters(osi_core, vid_idx, val);
@@ -326,10 +326,10 @@ static inline int add_vlan_id(struct osi_core_priv_data *osi_core,
* @return 0 on success
* @return -1 on failure.
*/
static inline int dequeue_vlan_id(struct osi_core_priv_data *osi_core,
unsigned int idx)
static inline nve32_t dequeue_vlan_id(struct osi_core_priv_data *osi_core,
nveu32_t idx)
{
unsigned int i;
nveu32_t i;
if (osi_core->vlan_filter_cnt == VLAN_HW_MAX_NRVF) {
return -1;
@@ -364,14 +364,14 @@ static inline int dequeue_vlan_id(struct osi_core_priv_data *osi_core,
* @return 0 on success
* @return -1 on failure.
*/
static inline int dequeue_vid_to_add_filter_reg(
static inline nve32_t dequeue_vid_to_add_filter_reg(
struct osi_core_priv_data *osi_core,
unsigned int vid_idx)
nveu32_t vid_idx)
{
unsigned int val = 0;
unsigned short vlan_id = 0;
unsigned int i = 0;
int ret = 0;
nveu32_t val = 0;
nveu16_t vlan_id = 0;
nveu32_t i = 0;
nve32_t ret = 0;
vlan_id = osi_core->vid[VLAN_HW_FILTER_FULL_IDX];
if (vlan_id == VLAN_ID_INVALID) {
@@ -381,8 +381,8 @@ static inline int dequeue_vid_to_add_filter_reg(
osi_core->vf_bitmap |= OSI_BIT(vid_idx);
osi_core->vid[vid_idx] = vlan_id;
val = osi_readl((unsigned char *)osi_core->base + MAC_VLAN_TAG_DATA);
val &= (unsigned int) ~VLAN_VID_MASK;
val = osi_readl((nveu8_t *)osi_core->base + MAC_VLAN_TAG_DATA);
val &= (nveu32_t) ~VLAN_VID_MASK;
val |= (vlan_id | MAC_VLAN_TAG_DATA_ETV | MAC_VLAN_TAG_DATA_VEN);
ret = update_vlan_filters(osi_core, vid_idx, val);
@@ -410,14 +410,14 @@ static inline int dequeue_vid_to_add_filter_reg(
* @return 0 on success
* @return -1 on failure.
*/
static inline int del_vlan_id(struct osi_core_priv_data *osi_core,
static inline nve32_t del_vlan_id(struct osi_core_priv_data *osi_core,
struct core_ops *ops_p,
unsigned short vlan_id)
nveu16_t vlan_id)
{
unsigned int vid_idx = 0;
unsigned int val = 0;
unsigned int idx;
int ret = 0;
nveu32_t vid_idx = 0;
nveu32_t val = 0;
nveu32_t idx;
nve32_t ret = 0;
/* Search for vlan filter index to be deleted */
vid_idx = get_vlan_filter_idx(osi_core, vlan_id);
@@ -463,12 +463,12 @@ static inline int del_vlan_id(struct osi_core_priv_data *osi_core,
return dequeue_vid_to_add_filter_reg(osi_core, vid_idx);
}
int update_vlan_id(struct osi_core_priv_data *osi_core,
nve32_t update_vlan_id(struct osi_core_priv_data *osi_core,
struct core_ops *ops_p,
unsigned int vid)
nveu32_t vid)
{
unsigned int action = vid & VLAN_ACTION_MASK;
unsigned short vlan_id = (unsigned short)(vid & VLAN_VID_MASK);
nveu32_t action = vid & VLAN_ACTION_MASK;
nveu16_t vlan_id = (nveu16_t)(vid & VLAN_VID_MASK);
if (action == OSI_VLAN_ACTION_ADD) {
return add_vlan_id(osi_core, ops_p, vlan_id);

5
osi/core/vlan_filter.h
View File

@@ -70,7 +70,6 @@
* @return 0 on success
* @return -1 on failure.
*/
int update_vlan_id(struct osi_core_priv_data *osi_core,
struct core_ops *ops_p,
unsigned int vid);
nve32_t update_vlan_id(struct osi_core_priv_data *osi_core,
struct core_ops *ops_p, nveu32_t vid);
#endif /* VLAN_FILTER_H */

62
osi/core/xpcs.c
View File

@@ -35,15 +35,15 @@
* @retval 0 on success
* @retval -1 on failure.
*/
static inline int xpcs_poll_for_an_complete(struct osi_core_priv_data *osi_core,
unsigned int *an_status)
static inline nve32_t xpcs_poll_for_an_complete(struct osi_core_priv_data *osi_core,
nveu32_t *an_status)
{
void *xpcs_base = osi_core->xpcs_base;
unsigned int status = 0;
unsigned int retry = 1000;
unsigned int count;
int cond = 1;
int ret = 0;
nveu32_t status = 0;
nveu32_t retry = 1000;
nveu32_t count;
nve32_t cond = 1;
nve32_t ret = 0;
/* 14. Poll for AN complete */
cond = 1;
@@ -101,11 +101,11 @@ static inline int xpcs_poll_for_an_complete(struct osi_core_priv_data *osi_core,
* @retval 0 on success
* @retval -1 on failure
*/
static inline int xpcs_set_speed(struct osi_core_priv_data *osi_core,
unsigned int status)
static inline nve32_t xpcs_set_speed(struct osi_core_priv_data *osi_core,
nveu32_t status)
{
unsigned int speed = status & XPCS_USXG_AN_STS_SPEED_MASK;
unsigned int ctrl = 0;
nveu32_t speed = status & XPCS_USXG_AN_STS_SPEED_MASK;
nveu32_t ctrl = 0;
void *xpcs_base = osi_core->xpcs_base;
ctrl = xpcs_read(xpcs_base, XPCS_SR_MII_CTRL);
@@ -142,15 +142,15 @@ static inline int xpcs_set_speed(struct osi_core_priv_data *osi_core,
* @retval 0 on success
* @retval -1 on failure.
*/
int xpcs_start(struct osi_core_priv_data *osi_core)
nve32_t xpcs_start(struct osi_core_priv_data *osi_core)
{
void *xpcs_base = osi_core->xpcs_base;
unsigned int an_status = 0;
unsigned int retry = RETRY_COUNT;
unsigned int count = 0;
unsigned int ctrl = 0;
int ret = 0;
int cond = COND_NOT_MET;
nveu32_t an_status = 0;
nveu32_t retry = RETRY_COUNT;
nveu32_t count = 0;
nveu32_t ctrl = 0;
nve32_t ret = 0;
nve32_t cond = COND_NOT_MET;
if (osi_core->xpcs_base == OSI_NULL) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
@@ -231,7 +231,7 @@ int xpcs_start(struct osi_core_priv_data *osi_core)
* @retval -1 on failure.
*/
static nve32_t xpcs_uphy_lane_bring_up(struct osi_core_priv_data *osi_core,
unsigned int lane_init_en)
nveu32_t lane_init_en)
{
void *xpcs_base = osi_core->xpcs_base;
nveu32_t retry = XPCS_RETRY_COUNT;
@@ -329,10 +329,10 @@ static nve32_t xpcs_check_pcs_lock_status(struct osi_core_priv_data *osi_core)
static nve32_t xpcs_lane_bring_up(struct osi_core_priv_data *osi_core)
{
struct core_local *l_core = (struct core_local *)(void *)osi_core;
unsigned int retry = 1000;
unsigned int count;
nveu32_t retry = 1000;
nveu32_t count;
nveu32_t val = 0;
int cond;
nve32_t cond;
if (xpcs_uphy_lane_bring_up(osi_core,
XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN) < 0) {
@@ -460,14 +460,14 @@ static nve32_t xpcs_lane_bring_up(struct osi_core_priv_data *osi_core)
* @retval 0 on success
* @retval -1 on failure.
*/
int xpcs_init(struct osi_core_priv_data *osi_core)
nve32_t xpcs_init(struct osi_core_priv_data *osi_core)
{
void *xpcs_base = osi_core->xpcs_base;
unsigned int retry = 1000;
unsigned int count;
unsigned int ctrl = 0;
int cond = 1;
int ret = 0;
nveu32_t retry = 1000;
nveu32_t count;
nveu32_t ctrl = 0;
nve32_t cond = 1;
nve32_t ret = 0;
if (osi_core->xpcs_base == OSI_NULL) {
OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
@@ -590,11 +590,11 @@ int xpcs_init(struct osi_core_priv_data *osi_core)
* @retval 0 on success
* @retval -1 on failure.
*/
int xpcs_eee(struct osi_core_priv_data *osi_core, unsigned int en_dis)
nve32_t xpcs_eee(struct osi_core_priv_data *osi_core, nveu32_t en_dis)
{
void *xpcs_base = osi_core->xpcs_base;
unsigned int val = 0x0U;
int ret = 0;
nveu32_t val = 0x0U;
nve32_t ret = 0;
if ((en_dis != OSI_ENABLE) && (en_dis != OSI_DISABLE)) {
return -1;

30
osi/core/xpcs.h
View File

@@ -120,9 +120,9 @@
#endif
/** @} */
int xpcs_init(struct osi_core_priv_data *osi_core);
int xpcs_start(struct osi_core_priv_data *osi_core);
int xpcs_eee(struct osi_core_priv_data *osi_core, unsigned int en_dis);
nve32_t xpcs_init(struct osi_core_priv_data *osi_core);
nve32_t xpcs_start(struct osi_core_priv_data *osi_core);
nve32_t xpcs_eee(struct osi_core_priv_data *osi_core, nveu32_t en_dis);
/**
* @brief xpcs_read - read from xpcs.
@@ -134,11 +134,11 @@ int xpcs_eee(struct osi_core_priv_data *osi_core, unsigned int en_dis);
*
* @retval value read from xpcs register.
*/
static inline unsigned int xpcs_read(void *xpcs_base, unsigned int reg_addr)
static inline nveu32_t xpcs_read(void *xpcs_base, nveu32_t reg_addr)
{
osi_writel(((reg_addr >> XPCS_REG_ADDR_SHIFT) & XPCS_REG_ADDR_MASK),
((unsigned char *)xpcs_base + XPCS_ADDRESS));
return osi_readl((unsigned char *)xpcs_base +
((nveu8_t *)xpcs_base + XPCS_ADDRESS));
return osi_readl((nveu8_t *)xpcs_base +
((reg_addr) & XPCS_REG_VALUE_MASK));
}
@@ -151,12 +151,12 @@ static inline unsigned int xpcs_read(void *xpcs_base, unsigned int reg_addr)
* @param[in] reg_addr: register address for writing
* @param[in] val: write value to register address
*/
static inline void xpcs_write(void *xpcs_base, unsigned int reg_addr,
unsigned int val)
static inline void xpcs_write(void *xpcs_base, nveu32_t reg_addr,
nveu32_t val)
{
osi_writel(((reg_addr >> XPCS_REG_ADDR_SHIFT) & XPCS_REG_ADDR_MASK),
((unsigned char *)xpcs_base + XPCS_ADDRESS));
osi_writel(val, (unsigned char *)xpcs_base +
((nveu8_t *)xpcs_base + XPCS_ADDRESS));
osi_writel(val, (nveu8_t *)xpcs_base +
(((reg_addr) & XPCS_REG_VALUE_MASK)));
}
@@ -174,13 +174,13 @@ static inline void xpcs_write(void *xpcs_base, unsigned int reg_addr,
* @retval -1 on failure.
*
*/
static inline int xpcs_write_safety(struct osi_core_priv_data *osi_core,
unsigned int reg_addr,
unsigned int val)
static inline nve32_t xpcs_write_safety(struct osi_core_priv_data *osi_core,
nveu32_t reg_addr,
nveu32_t val)
{
void *xpcs_base = osi_core->xpcs_base;
unsigned int read_val;
int retry = 10;
nveu32_t read_val;
nve32_t retry = 10;
while (--retry > 0) {
xpcs_write(xpcs_base, reg_addr, val);