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Author SHA1 Message Date
Om Prakash Singh
f661fdd189 core: add pcs register readback after write support 
As per T23X-MGBE_HSIv2-14 requirement for PCS register
we need to perform readback for each write operation
to verify write operation was successful

Bug 3606649
Change-Id: I7cca6baa43feaa4207b6158f0abc796e656338dd
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2700845
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
jetson_35.1 		2022-05-04 23:24:27 -07:00
Hareesh Kesireddy
ede22ef36d osi: remove extra args for tx complete callback 
Dma phy address, virtual address and packet length can be
obtained from tx swcx structure. Hence passing
pointer to tx swcx is sufficient. In future, if more information
from osi is needed, it can be embedded into tx swcx itself rather than
adding more arguments to osd tx complete call back.

Bug 3576506

Change-Id: I061ea27cd1b4d68c19f3e9d95a247505c511ce0c
Signed-off-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2700341
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-04-30 06:15:57 -07:00
Bhadram Varka
1ce3d01e1a osi: core: program 0xF's while deleting MAC address 
Issue: After deleting the MAC address its observed that
old MAC address values are there in low/high registers
which creates confusion while checking the register dump/

Fix: Program 0xF's in low/high registers while deleting
the MAC address.

Bug 3609583

Change-Id: I1d93d6bc31eb1c49e7641ff97f73d0ed4bb0345f
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2702855
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-29 13:27:00 -07:00
Sanath Kumar Gampa
62917832dc osi:macsec reduce complexity of MACSEC APIs 
Issue: Complexity of OSI APIs cannot be greater than 10

Fix: Split the functionality of complex APIs to multiple APIs.
Added De-oxygen comments as well for macsec osi APIs

Bug 3460422

Change-Id: I2383904d8581efa54a8d2ec2f85a50cb12b22e89
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2688990
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-04-27 20:18:14 -07:00
Sanath Kumar Gampa
437680030d osi:macsec: Fix MISRA defects in QNX OSD 
Dependent change made in osi to fix a misra defect in QNX OSD

Bug 3598679

Change-Id: Ie6b48a6d1cb8d34b00c437cc3b57971ad447fa3b
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2695627
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-26 04:07:19 -07:00
Om Prakash Singh
de75b86ee1 osi: core: fix XPCS_REG_VALUE_MASK 
Issue: PCS register read/write is failing due to wrong value of
 XPCS_REG_VALUE_MASK;

Fix: update XPCS_REG_VALUE_MASK value to 0x3FF

Bug 3591736

Change-Id: Id62aff5f8749b94810475ff79665899a10bec3e4
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2701996
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-25 18:37:21 -07:00
Bibhay Ranjan
4fae8741fb nvethernetrm: fix code defects 
Issue: SPARSE errors
Fix: Fix code as per the guidelines in the errors

Bug 3568991

Change-Id: If52bf7d5b3e8d4ca10a254e802ee5257a8816633
Signed-off-by: Bibhay Ranjan <bibhayr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2688520
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-21 15:53:24 -07:00
Nagaraj Annaiah
221989d875 osi core: Fix compiler warnings for HVRTOS 
Issue: Unused variables are treated as errors with HVRTOS compiler.

Fix:
1. Add unused attributes macro for unused function arguments.
2. Fix typecast errors.
3. Add flag to check if ethernet server status, this is needed to
   skip check for function pointer validation.

Bug 3562777

Change-Id: I0a4a36fb330c580d1879f46304842c610e62316c
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2670097
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-21 15:52:01 -07:00
Sanath Kumar Gampa
70fdb56a05 osi:macsec: Separate lut_status for each IP 
Issue: If macsec is created on EQOS and then created on MGBE, we are
over writing the lut_status of EQOS with MGBE lut_status.

Fix: Create different lut_status structure in osi_core so that each
IP will have its own lut_status structure.

Bug 3587231

Change-Id: I826c3d210ed18350140f1cbcb41b748550f92844
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2690839
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-04-15 04:29:14 -07:00
Om Prakash Singh
5e933f3234 osi: macsec: set ICV error threshold to 1 
Issue: default IVC error threshoud 16k. Which is not same as
  Other error like RX/TX CRC error. It is conflicting with
  expection of DT based error reporting threshold
  "nvidia,hsi_err_count_threshold"

Fix: Set ICV error threshold to 1 to match the other error interrupt
 frequnecy.

Bug 3543410

Change-Id: Ic64fcdaa007e9a57823515dc8f970d636b34eaa1
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2696380
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-14 17:05:08 -07:00
Sanath Kumar Gampa
37ab92517f osi:macsec: Fix osi macsec Misra/coverity issues 
Issue: Found aroung 900 MISRA?COVERITY defects on
OSI MACSEC changes

Fix: Fixed the defects by making minor changes without
impacting the functionality

Removed calling poll_for_dbg_buf_update, poll_for_kt_update
and poll_for_lut_update before lut_write as we are anyhow
polling after the lut_write

Bug 3460422

Change-Id: Ib33e8188cd90472b851732f0936c3e29142bb4a3
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2618714
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-04-11 13:17:05 -07:00
Om Prakash Singh
65f78eba09 osi: core: add support for HSI 
1) Add OSI IOCTL to enable HSI feature at runtime
2) Enable LIC interrupt for Correctable, Uncorrectable and
   Parity error
3) Program register to enable safety feature

Bug 3543410

Change-Id: I8a9f33bab72eb37e8aa64c16c610be6e5271c7f8
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2670989
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-09 16:26:37 -07:00
Sanath Kumar Gampa
6dc6e28282 osi:macsec:Change to update MACSEC MTU 
Issue: If MTU is increased after Supplicant is initialized
we are not updating the MACSEC MTU so the frames will get
dropped as the MACSEC MTU is lesser than the frames received

Fix: Changes to update the MACSEC MTU along with MAC MTU

Bug 3577143

Change-Id: Iff61099ff2a9ae1f6fe6e48948d842604fd9e2c4
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2685281
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-07 03:18:33 -07:00
Mahesh Patil
78a2949c0f core: eqos: Fix pad calibration change coverity 
Fixed pad calibration change coverity issue

Bug 3461002

Change-Id: I2e040dfcd4c1f7fd34637cd6b7c43e5ab3d9d7c4
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2686833
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-04 15:55:11 -07:00
Gaurav Asati
4bfcf13098 osi: Change barrier. 
Issue: Using "asm volatile" is leading to compilation
issues with new coverity version.

Fix: Change "asm volatile" to __sync_synchronize as
same functionality is achieved without any issues.

Bug 200699678

Change-Id: I685d27efab48443f2d2a664ae803e724cccde3fc
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2481631
(cherry picked from commit 63cdb70b76f3ae2b214d1ca371d42bdc7680e617)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2486720
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-03-17 10:14:09 -07:00
Bhadram Varka
9d2e1695f6 osi: mgbe: fix MGBE channels mask 
Bug 3420115

Change-Id: If086f090082bda7972d01776543f24c8cf9b060f
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2680952
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-03-14 17:14:22 -07:00
Sanath Kumar Gampa
3ba0e448b7 osi:macsec: fix coverity defect 
Issue: Coverity issue : "Unchecked return value"

Fix: Check the return value and print error

Bug 3460422

CID 10127972

Change-Id: I78df96d969cbd23b22969cc02b79a64c17e8fe18
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2678123
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-03-14 07:39:52 -07:00
Gaurav Asati
b034e9c60c nvethernetrm: mgbe: Remove stale PTP timestamp. 
- When PTP Tx timestamp list is full with timestamps and
 a new timestamp is generated by Hw, remove oldest entry.

Bug 3554871
Signed-off-by: Gaurav Asati <gasati@nvidia.com>

Change-Id: If4fdb884638687609798827d3ee6b5a0a3919c1e
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2679260
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Tested-by: Gaurav Asati <gasati@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-03-11 05:37:22 -08:00
Sanath Kumar Gampa
92924602ba osi:macsec: Address SC over-writing issue 
Issue: In multi VM use case if multiple SCs are added using supplicants
Then we may over-write an exisitng SC if we stop and start the first
supplicant

Fix: Before adding an SC find the vacant SC slot

Bug 3522740

Change-Id: Ic10f7a542a01328876b0103c34cc1115bfd426b5
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2675003
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-03-09 21:04:38 -08:00
Bhadram Varka
f65faa73f2 osi: dma: Define macro for DMA TX max buffer size 
Bug 3528173

Change-Id: If7152ec75bcf21d820cd68c3aff31e3c6aa8ae6b
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2675628
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-03-02 18:05:00 -08:00
Rakesh Goyal
288c525a36 nvethenetrm: core: SW WAR implementation for switching of Gates 
Issue: switching of Gates did not happen for
intermediate cycles when CTR is
less than GCL execution time

Fix: SW WAR as per recommendation.
1) At the programming time make sure
  (CTR - total TI) should be 0 or more than
  8PTP clock time.
2) Switching to New List
   check for following
   Old BTR + n(CTR) - New GCL list's BTR >= 8PTP or
   New GCL list's BTR – (Old BTR + n(CTR)) >= 8PTP

Bug 200724911

Change-Id: I19127a134655a66bb66d025f964b85afc6c23c2e
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2622942
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-02-28 10:49:29 -08:00
Gaurav Asati
85da4dbc4d osi: dma: update tx and rx completion API's. 
- Add tx and rx completion API's with
  failure return value.

JIRA T23XMGBE-443

Change-Id: Ib6aa3b559f1356e9285f8d4cc129abc049884342
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2618556
(cherry picked from commit 6bd8b7fe13f258928bb81ebe22c30fe5b51688c0)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2658600
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-02-27 18:09:02 -08:00
Gaurav Asati
3ac0bf273d core: eqos: update structure and function documentation 
Update eqos_core.c function definitions to address new SWUD guidelines.

JIRA T23XMGBE-839

Change-Id: I8f4953c2756c9a550739b6c9f049669dbaa7cf89
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2604786
(cherry picked from commit 47043b9343640807c2f66beb8026b6a1f81bc42d)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2657436
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-02-27 18:08:57 -08:00
Gaurav Asati
f1125b7063 osi: update API headers 
Use @usage instead of @note and group all classification and API
group details under @usage.

Bug 3350640

Change-Id: If77cfd76519f17427b95a2300ad722dc6f83f518
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2587106
(cherry picked from commit 0002e2d0b2cf85811b09e8c7157dbd777c8fc117)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2657079
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-02-27 18:08:46 -08:00
Gaurav Asati
9a6c5dbc4b osi: Add Async-sync details to API header 
Issue:
Async-sync details to API header is needed.

Fix:
Add Async-sync details to API header and remove duplicate Thread
details.

Bug 3350640

Change-Id: I0838e53951389c9fa408323324cedba0268f4706
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2572939
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Gaurav Asati <gasati@nvidia.com>
(cherry picked from commit 8acef05c924ed72e256e792a8cd623a221494287)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2657054
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-02-27 18:08:35 -08:00
Sanath Kumar Gampa
65a9cb659e macsec: get next PN and IRQ stats cmd with server 
Some of the commands such as get next PN and irq stats
are not working if thernet server is enabled, fixed the same.
And also moved HKEY generation to OSD, to avoid dependency on
Crypto libs on LK. devmemr/w can read/write to macsec addresses

Bug 3522740

Change-Id: Id3b328cfd83aa976ef5bde8adc057588bb6fed38
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2652212
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-02-27 18:07:30 -08:00
Narayan Reddy
97d5787a79 mgbe: modify AXI clock to 480MHz 
480MHz APP clock needs to be used for 10G speed as per IAS.
Change the clock source to reflect the same.

Bug 200778229

Change-Id: Idf60c4a090ed82b0a1be58d5b45b3a557c59fdfc
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2660870
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-02-10 14:05:50 -08:00
Bhadram Varka
f2f5cbf648 osi: fix coverity defects 
CID 10060746 Big parameter passed by value
CID 10060747 Big parameter passed by value
CID 10127879 Dereference after null check

Bug 3461002

Change-Id: Ib1d88177ade979e43e9177ff69f7817982b39be0
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2665777
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-02-09 20:53:58 -08:00
Om Prakash Singh
bc8f866fac osi: fix mmc.h dependency on osi_common.h 
mmc.h uses few definition from osi_common.h

Bug 3500728

Change-Id: I95696ddd63cee4979c0a79cda9a87e65b895dee0
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2663878
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-02-09 09:47:04 -08:00
Sanath Kumar Gampa
f88c313a87 To fecilitate calling the PTP-TSC capture in ISR 
Change the usleep used to udelay, so that PTP-TSC
fetching can happen in ISR context

Bug 3430408

Change-Id: I2d6f3755e94fafabe80913fd81cbf1a85c83d407
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2639986
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-02-02 21:41:38 -08:00
Mahesh Patil
393cfedcf7 nvethernetrm: macsec qnx OSI changes 
Macsec qnx driver OSI changes

Bug 3338180

Change-Id: I2ad4f1b8b919893f2823a120973c1805b58bbb88
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2612659
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Tested-by: Sanath Kumar Gampa <sgampa@nvidia.com>
 2022-02-02 21:40:44 -08:00
Bhadram Varka
5461678a44 osi: dma: combine global DMA status functions 
Global DMA status register offsets are same for
EQOS and MGBE. Combine EQOS and MGBE function
into single function instead of two functions.

Bug 200770328

Change-Id: Ia5dfebfd4625daa7bfd04e53e13a6df6a111047e
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2660067
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-01-28 04:51:37 -08:00
Gaurav Asati
92592afeed nvethernetrm: add support desc dump on QNX. 
- Enable desc dump on normal builds
 - export API osi_dma_ioctl

Bug 3375445

Change-Id: I66f33f6c370ebcfcfa194e88d598633cd0892a15
Signed-off-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2645253
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-01-21 09:16:52 -08:00
Sanath Kumar Gampa
fb4dde440b osi: Avoid macsec and fpe coexistance on MGBE 
Issue: Internal FIFO over/underflows if MACSEC and FPE are enabled on MGBE
interafce and pre-emptable and express frames are sent in interleaved
fashion

Fix: Do not allow enabling any of MACSEC and FPE if the other is already
enabled.

Bug 3484034

Change-Id: Ifc80eb9333c836652a86362a1f7788a0ce70dbb7
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2647788
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-01-20 15:36:57 -08:00
Mahesh Patil
b106e60bd9 Revert "nvethernetrm: pad calibration" 
This reverts commit 54263d6ea5.

Bug 3494618

Change-Id: I8e609fb2d42be713d255703d79e1b318078f2907
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2651963
Reviewed-by: Hyong Bin Kim <hyongbink@nvidia.com>
Reviewed-by: Kasinadha Dendukuri <kdendukuri@nvidia.com>
Reviewed-by: Sumeet Gupta <sumeetg@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Kasinadha Dendukuri <kdendukuri@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-01-13 19:34:36 -08:00
Rakesh Goyal
2246e3a2a5 core: add support configure pps out signal 
Issue: Default pps output is 1 pulse (of width
clk_ptp_i) every second.

Fix: option to configure to binary rollover is 2 Hz,
and the digital rollover is 1 Hz.

Bug 3462227

Change-Id: Ic777bfaf51a72ec91c8f165910e824c55cae3057
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2641896
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-01-11 20:06:08 -08:00
Mahesh Patil
54263d6ea5 nvethernetrm: pad calibration 
Enable update pad caliration code under UPDATED_PAD_CAL
macro and remove old pad calibration code
Bug 2831220

Change-Id: I01daa72ff6e6cfb016de85f22b55404a9d8a54ba
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2562771
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-01-06 17:17:51 -08:00
Prateek Patel
68e89375a3 nvethernetrm: fix large_shift coverity defect 
Checking vid_idx == 32U implies that vid_idx is 32 on the true branch.
In expression OSI_BIT(vid_idx), left shifting by more than 31 bits has
undefined behavior. The shift amount, vid_idx, is 32. Return with "-1"
error condition to fix the defect.

CID 10060748

Bug 3461002

Change-Id: I7711152fcf93e50f3c85eddf20b3e9721fb4f853
Signed-off-by: Prateek Patel <prpatel@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2642992
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-12-22 08:35:15 -08:00
Rakesh Goyal
bdf6243c69 core: eqos: fix PTP register offset 
Issue: ETHER_QOS_PTP_CAPTURE_* register offset was wrong.
low and high offset are swapped.

Fix: correct the offset value.

Bug 3471827

Change-Id: Ia7e13209e123f1c58655af9b79186aa6a21ad316
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2642729
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-12-16 09:11:49 -08:00
Mohan Thadikamalla
c2b4bf8204 mgbe: Fix FRP DMA route issue 
Issue:
FRP MC/BC packets routing to
multiple DMA channels is not happening.

Fix:
Correct the FRP entry DCH programming to
enable multiple DMA channels route.

Bug 3417901

Change-Id: Ib3d5794253b89d7d3a00164fa7fd011e4ac9e50b
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2629966
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-12-14 02:45:56 -08:00
Sanath Kumar Gampa
f1e4661f1e osi:macsec:Changes to enable AN after key program 
Issue: In longer stress tests we see unint_key_slot
errors if the key programing is done after AN is
enabled.

Fix: Fix is to program the key and then enable AN.
Done some code cleanup as well

Bug 3422356

Change-Id: I7aeb2f9ab681509b54e9f6763464dfedb46cd26e
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2626062
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-12-14 02:45:34 -08:00
Rakesh Goyal
a5c2423f63 core: enable m2m_sync for primary and secondary interfaces 
Issue: Ask is to enable Mac-to-Mac tsync
on interface for primary and secondary interface.

Fix: update default value.

Bug 200733666

Change-Id: Ie00e3cf96d0deb75d7c623a63bc0d06ed637ca2c
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2628723
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: Sheetal Tigadoli <stigadoli@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
jetson_34.1.1 jetson-r34.1_dp 		2021-12-06 04:35:42 -08:00
Sanath Kumar Gampa
d190c203da osi:macsec:Fix to address sc_an_not_valid counter 
Issue: tx_sc_an_not_valid counter is increasing in
stress tests when there is AN roll over happens

Fix: Program the SCI LUT with vaid AN map and then
enable AN in sc_state LUT

Bug 3422356

Change-Id: I17021d435076ff94367a58a4c74b50124c97d68a
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2623649
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-12-02 07:39:53 -08:00
Bibhay Ranjan
97c73020e2 nveqos:fix MISRA_C-2012_Rule_8.13 and 10.4 issues 
MISRA FIXES
===== DIFF ======
Total misra violation count changed by -21
Rule: MISRA_C-2012_Rule_10.4 Diff: -1
Rule: MISRA_C-2012_Rule_8.13 Diff: -20
Rule: Total Diff: -21

CERT FIXES
===== DIFF ======
Total cert violation count changed by 0

Bug 200770325

Change-Id: Ib6cca8c2eaff5ae8cddd718b2f0c309c6888d4fc
Signed-off-by: Bibhay Ranjan <bibhayr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2605632
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-11-17 12:47:39 -08:00
Sanath Kumar Gampa
c52ad89f9d osi:macsec:lowest pn changes to enable sa 
Enhancement to receive lowest_pn from supplicant
as part of receive AN enable

Bug 3371004

Change-Id: If81f8449f7ebda996c95117e2c84722fdc57c5d0
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2619949
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-11-11 20:39:08 -08:00
Mohan Thadikamalla
ee1da8d41d osi: xpcs: Remove XPCS lane bring up retry 
Issue:
When the ethernet server got enabled the boot time KPI
increased due to the XPCS lane up retry.

Fix:
Remove retry from OSI and add SET_SPEED ioctl
retry from OSD.

Bug 3414276

Change-Id: I617ab51ee6ddd50b449f78ecc9c858b1d9196b3e
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2617516
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-11-10 00:19:36 -08:00
Rakesh Goyal
81e1442693 nvethernetrm: core: MAC to MAC tsync dynamic support 
Add code to support enable/disable M2M sync using
ioctl.

Bug 200733666

Change-Id: Ifedad7981644c816345f3e10a0b0f8289e032200
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2614964
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-11-02 04:07:38 -07:00
Rakesh Goyal
61be2488de nvethernetrm: MAC to MAC time sync 
- Add code to store role of FD
- Function to return osi_core pointer for
  first role match.
- add code to calculate time offset between
  Primary and Secondary PTP controller HW time.
- calculate frequency adjustment calculation.
- call appropriate HAL function for
  secondary interface.

Bug 200733666

Change-Id: I7a141ea691d80d9f69fd18b28ae0964cb1bf2fb3
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2614283
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-11-02 04:07:33 -07:00
Sanath Kumar Gampa
b8e03a8b43 osi:macsec: changes to send next PN to supplicant 
As part of MKA, supplicant requests for Next PN
used by SecY. Added changes to OSI to send to
send the Next PN for a given SCI and AN.

Bug 3371004

Change-Id: Iaf001ba5e6b5480396e2f774a42927831160a2e5
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2614365
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-10-28 01:06:06 -07:00
Bhadram Varka
15aec6d712 osi: dma: check TDES3_ES_BITS for EQOS 
Issue: TDES3_ES_BITS not valid for MGBE which results
wrong error stats in ethtool o/p

Fix: Check TDES3_ES_BITS only for EQOS.

Bug 200779501

Change-Id: Idccc8cca54b2fe6f8ac30ed99f2cc69d093acea9
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2609473
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-10-22 02:09:16 -07:00