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Author SHA1 Message Date
Mahesh Patil
caae00f95b osi: Mask MMC_IPC_Rx_Interrupt_Mask interrupts 
Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3072520

Bug 4297728

Change-Id: I9e14e9ebfe6a40f793e2ebd3c0aede0b95018466
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-06 00:37:38 +00:00
Mahesh Patil
28b35b22c1 osi: add idle timer window interrupt support 
Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2963541

Bug 4246781

Change-Id: I89554a105be26958e17878b299aaadb13c39c130
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-06 00:37:32 +00:00
Rakesh Goyal
be2b32250c osi: core: remove vDMA code from onestep 
Issue: Bug 4287805 was not clear for one-step
Fix: pktid/vdmaid are supported in 2-step only
remove code added for bug 4287805

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3056314

Bug 4287805

Change-Id: Ia02877889ef36a18304e194d413ed1688d881c39
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:07:09 +00:00
Mahesh Patil
68addfdb39 osi: Properly calc completed rx descriptors 
Properly calc number of Rx descriptors to be processed
based of completed write back offset and rx_cur_idx

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3032445

Bug 4408683

Change-Id: Id4af063f2a8eb49921ecf10d4d7fff0c5b4bcb5b
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:07:09 +00:00
Rakesh Goyal
b3b589004f osi: ptp support for upcoming chip 
Support for PTP and TSN added

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2968052

Bug 4221043

Change-Id: I68287c3961aa194c30ca265dfe646e733fcb52cc
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:07:09 +00:00
Mahesh Patil
0c2228a485 osi: configure mtl Q's size 
Max Tx/Rx MTL Q size in uFPGA is 64K, so adjust
Tx/Rx MTL Q's accordingly

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3031129

Bug 4413578

Change-Id: I7510cb230bd1400dd1ce565092b445c6a6def30d
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:07:09 +00:00
Mahesh Patil
275769b28a osi: Allow more than 31 l2 filter index 
Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3027948

Bug 4297989

Change-Id: I0365f2136b5d7519946113fc728a58ed8fcccab4
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:07:09 +00:00
Mahesh Patil
84310ba297 osi: In T26x, Q2TCMAP field marked reserved 
Avoid read/writing to MTL_TxQ0_Operation_Mode[Q2TCMAP] as
it is marked reserved.

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3003833

Bug 4287563

Change-Id: I578a647200c967449bdda94ea0f34a0895bff393
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:07:09 +00:00
Nagaraj Annaiah
23dc94a26a osi: Add FRP and L2 support for t264 
Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2992833

Bug 4334269

Change-Id: Iceade85fa54b407135ec94b4bb11cc204132efe0
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:07:09 +00:00
Sanath Kumar Gampa
ea9c74eb3d osi:macsec Defeature MACSEC features on T264 
Defeature fpe and macsec co-exisitannce, confidentiality offset
and MACSEC debug buffers

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3016483

Bug 4134804

Change-Id: I70679c51eb3dbc3965c3acb689901a523b37ba44
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:06:47 +00:00
Sanath Kumar Gampa
a8361d9fb6 osi:macsec: Update LUT programming for 48 SCs 
Issue: SCI LUT has wrong SC Indexfor Indices greater than 16

Fix: Accomodate more bits from lut_data to read more bits to find the
sc_index.

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/3010673

Bug 4361623

Change-Id: I6cd9fd11e05a202c06785940733d4f64af541675
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:05:51 +00:00
Mahesh Patil
38bcfb8041 osi: Rx write back descriptor ring offset 
Check Rx descriptor write back ring offset(index) with current
ring index before processing Rx packet to avoid processing Rx
packet before it is actually trasfered to system memory

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2964259

Bug 4246781

Change-Id: Iaa947c6e01e1cc59a5e6dc6ea93ef43a757e3317
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:01:50 +00:00
Sanath Kumar Gampa
cbdac87b2c osi: macsec: Adding support for encryption and confidentiality offset support 
Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2935716

Bug 4193186

Change-Id: I39669992b11e9ef032ca43f539494d48fd31ed2a
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:01:50 +00:00
Mahesh Patil
c604c5f2f2 osi: Macsec bring up for t264 
Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2904857

Bug 4122114

Change-Id: I85248181de4898293672a56199044e2deea5729a
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:01:50 +00:00
Mahesh Patil
0bbdb9b46a osi: Add 5-tuple L3L4 fitler match 
Add combined L3 and L4 filters support

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2964434

Bug 4246781

Change-Id: I32c5fcff7068a1c2245936fc435cb433729be6b9
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:01:50 +00:00
Mahesh Patil
0c152e73d9 osi: Add T264 changes to include 48 filters 
Add support to include 48 filters for T264 from feature register

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2982588

Bug 4291865

Change-Id: Ib1e81932798d5d3c77679e8c3645887a9ad70faa
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:01:50 +00:00
Sanath Kumar Gampa
801a28ceab osi: mgbe adding correct SID for SMMU 
Lower 8 bits of the StreamID are obtaioned from MGBE registers and the
upper 8 bits are obtaioned from MSS HW. Programming lower 8 bits to 0s
in non-virtualization case. Once virtualization is enabled for other VFs
of MGBE diferent lower 8 bits of StreamID have to be programmed.

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2939709

Bug 3891884

Change-Id: I0d5587c71b7b497143a2bab3ae262b759b5e4526
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:01:50 +00:00
Mahesh Patil
f8df147841 osi: T264 Ethernet NET07 bring up 
- Update the mac version
- Program PDMA receive enable
- Program DDS bit of DPCSEL register as XDCS is removed for T26x

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2969471

Bug 4266891

Change-Id: Icf7e9df4033a9ea6af3c8d5759694717c0cf1145
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:01:50 +00:00
Mahesh Patil
992e66178b osi: T264 VDMA 20 channel support 
Enable VDMA 20 channels and interrupts

Ported from -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2940792

Bug 4043836

Change-Id: I4c22c7006c8813d9b39fe54d872b28ca7c123c74
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
 2024-06-05 12:01:50 +00:00
Mahesh Patil
8c7f7328e8 osi: T264 VDMA feature and bring up changes 
Bug 4043836

Ported from the change -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2896005

Change-Id: Iabbbde0d2733f04bba5d7128e7b8ac5956605424
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3149288
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Tested-by: Bhadram Varka <vbhadram@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-06-05 02:51:04 -07:00
Narayan Reddy
d28da6a10b xpcs: update lane programming sequence 
1) Updated the HW programming sequence of XPCS lane bring up
2) As a part of the link bringup, link partners exchange fault
sequence (local and remote faults) initially. Driver was enabling
the Link fault interrupt before the fault sequence is fully complete,
so added a condition to wait until the initial fault sequence
is complete before enabling the link fault interrupt in the MAC.

Bug 4301751

Change-Id: I369023d8ed5eef8e436105148d9f28b87aab1ca1
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3095516
(cherry picked from commit 7522e79f6d6f0b39c4ee1f3d078fbb5da45592b0)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3133226
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-05-22 10:04:27 -07:00
Rakesh Goyal
3b1e1b7370 osi: core: Add function trace for SEQ/UML validation tests 
Added RtosCWrapStringLog() based function tracing for
Ethernet Server and slogf() based function tracing for
OSD

Bug 4550849

Change-Id: I75d5fd7cbc6b27f8893265216b6599a707fb10ed
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3121802
(cherry picked from commit 90533a099885de45dae46311127e94230eb91ff3)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3137118
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-05-21 04:20:02 -07:00
Hareesh Kesireddy
aa57af8328 osi dma: fix mgbe rx checksum flags 
Issue description:
- IPV4 CSUM SW flag is always set without checking HW flags.

Fix description:
- Set IPV4 CSUM SW flag only if packet type is > 0 in rdes3.
- Check for IPHE and CSUM errors from rdes3.ellt only if
  rdes3.es bit is set.

Bug 4611476

Change-Id: Iaaf56b4cc122fd51e29f12f759ac7e3a3905a067
Signed-off-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3119885
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
(cherry picked from commit 39e36ad2cad9c7e4254c2f6eef91a7f074b207df)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3137117
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2024-05-21 04:19:52 -07:00
Ajay Gupta
face9ac97b NvEthernetCL: Add function trace support 
Bug 4550849

Jira NET-1363

Change-Id: I6712ff223f6844ee45793f97acf935c704288d4c
Signed-off-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3097969
(cherry picked from commit d623e89d159bcc904739ede7223072966a579b9d)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3137115
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Tested-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
 2024-05-21 04:19:47 -07:00
Hareesh Kesireddy
0acc3d66b8 osi: rename OSI_TRUE/OSI_FALSE macros for misra 
- Renamed OSI_TRUE/OSI_FALSE macros for resolving misra.

Bug 4550849

Change-Id: Ic9d8b673c077d33295f405dd5e8e36d36eef5c75
Signed-off-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3095193
(cherry picked from commit dc768942fdee0dd8fddfc5a0d9fa5a202c13eb33)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3137113
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-05-21 04:19:42 -07:00
Hareesh Kesireddy
4ed7e20962 osi: update OSI_TRUE and OSI_FALSE values 
- Modify OSI_TRUE and OSI_FALSE values to 1 and 0 only
  to avoid l3l4 filter issues.
- Use right shift operations to resolve misra for these
  macros.

Bug 4545417

Change-Id: I23dc04fe61120e1af7f13bbeb41f748743c58344
Signed-off-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3088790
(cherry picked from commit 362b3572e27d51248c30e6dc5eb67777cb2d5ff9)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3137112
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2024-05-21 04:19:32 -07:00
Narayan Reddy
d9caf2b991 osi: core: move err injec code to vltest 
issue: HSI error injection logic is enabled by default
and is exposed as an ioctl which is a safety-related concern.

fix: move HSI error injection code only for
VLTEST build

Jira NET-1235
Bug 4449611

Change-Id: I9a23895249c7db52586a83a042cf514ef0e5faae
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3077931
(cherry picked from commit 5af42a33298f5408b4209223802139501acf9d39)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3132843
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-05-17 00:21:13 -07:00
Narayan Reddy
545dbfe28a osi: core: remove unused code 
osd_msleep is no longer used, so remove it

Bug 4449611
Jira NET-1411

Change-Id: I2277506e99749d45197f88382070b596c3b9427d
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3122916
(cherry picked from commit 11b9c5cfb950cba0fc50da0ff12aae180244e4d3)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3134312
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-05-15 14:18:38 -07:00
Narayan Reddy
c9a9df02cf osi: core: add null check for osd call back functions 
add null checks for missing osd callback functions

Bug 4449611

Change-Id: I17629774f01b346c69d331f7d89226d003a01b8e
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3116534
(cherry picked from commit c33d6965c99981e78f3f03c7d523dd4ebc3f10ea)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3134311
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-05-15 14:18:12 -07:00
Hareesh
19e39b43ea osi: mgbe: enable interrupt after link up 
- Enable LS interrupt on link up detection.

Bug 4382126

Change-Id: Ie1177f129ce3e4f5539cebae1a5a3435f6ec2c88
Signed-off-by: Hareesh <hkesireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3068694
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3132892
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2024-05-15 14:16:11 -07:00
Bhadram Varka
a294d1ce9d osi: core: increment with actual value 
Issue: Counters always incremented by one.

Fix: Increment the counter based on actual value.

Bug 4449611

Change-Id: I583da6db58524bd1c203b51da5a1208d7dcff744
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3085443
(cherry picked from commit 84fe2b1f915c81f45e2ef1cab0c3ffc8f323cd4c)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3137111
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-05-15 13:57:54 -07:00
Rakesh Goyal
a5d304e68a osi: core: add range checker for ppb 
issue: missing ppb range checker
fix: add ppb check within range of MAX_FREQ_POS
and MAX_FREQ_NEG.

Bug 4449611

Change-Id: I21e195d2f6fa015ff79f8944ccc67e994ddecf63
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3091396
(cherry picked from commit b7e30eb2fa3fd18de5f3984b8919473e24a8dfac)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3100271
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-05-15 13:57:20 -07:00
Narayan Reddy
1ec150d96d osi: core: fix doxygen comment for macsec 
Bug 4449611
Bug 4550849
Jira NET-1331

Change-Id: If98d4d3a531849b1ea9265830f5a97ba775ff08f
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3093508
(cherry picked from commit f13c12301e060a045ef32a95651c99578ac10af0)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3133376
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Tested-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
 2024-05-15 13:57:10 -07:00
Narayan Reddy
c2d9f13da3 osi: core: modify core osd ops check 
add check only in case of virtualization disable,
where server initializes these ops incase of QNX
and Guest OS does in case of Linux

Bug 4449611
Bug 4455158

Change-Id: I86fea0e26e8d98c6522129c8cb4c364354fb936a
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3083330
(cherry picked from commit 142e022ebdea7cff52eb545db002a60ccf412042)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3132847
Tested-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
 2024-05-09 03:28:22 -07:00
Mohan Thadikamalla
bcf446f5dc core: mgbe: Handle TX and RX FSMs on link status 
Issue:
Unwanted timeouts for TRC, RPERXLPI, RXLPI-GMII,
and RARP FSMs are being reported during
the link down state.

Fix:
Disable TRC, RPERXLPI, RXLPI-GMII,
and RARP FSMs when link is down.

Bug 4502985

Change-Id: I7e3e5cc9c1452f4b148bcc7701d38d08b0c0ec17
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3106693
(cherry picked from commit e8b4299015b3e4a75e0c13e81469896c159d7dd3)
(cherry picked from commit 5b8d297ea2adc2d9fcbd9874292daa5463bd9afa)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3127755
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
 2024-05-03 04:23:40 -07:00
Mohan Thadikamalla
ce8941f7a4 mgbe: Set MAC_FSM_ACT_Timer.NTMRMD to 5 
Issue:
Regression bugs related to MGBE HSI
errors are observed due to the
enablement of MAC_FSM_CONTROL.TMOUTEN

Fix:
Based on software experiments and the hardware team's
recommendation in bug 3584387,
Set MAC_FSM_ACT_Timer.NTMRMD to 0x5  to use 256ms interval.

Bug 3584387
Bug 4502985
Bug 4502569
Bug 4502581

Change-Id: I7e29ff6673c2179bed74770f9f0bd6a6c1725fe7
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3087196
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2024-03-02 09:10:43 -08:00
Sanath Kumar Gampa
15bb82c842 Initialize the FRP entries as part of core init 
Bug: Uncorrectable errors are seen for every rx frame,
when FRP rules are added on EQOS

Fix: Initialize the FRP entries with Bypass rules

Bug 4502478
Bug 4449611

Change-Id: I1a5b181dbe1c7bea685b696d458ed1333e0fee88
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
(cherry picked from commit 4019a2e1d94fad7e891c8e5b973b55d430bda54d)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3087288
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2024-03-02 02:31:32 -08:00
Bhadram Varka
f8043809fc osi: fix regression stats increment 
Issue: Stats are getting incremented by
one irrespective of the passed value.

Fix: Increment the counter with passed
incr value.

Bug 4506095

Change-Id: Ib8a74b8baff82657cf0935dd46638169536d45b9
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3084602
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2024-02-28 11:16:09 -08:00
Bhadram Varka
50f657461c osi: add the t19x eqos support 
Bug 4506095

Change-Id: I6669ccc10db9888a14b0e03a2592de4531d43e75
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3083937
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
 2024-02-28 11:16:04 -08:00
Bhadram Varka
d385f4ee2c osi: fix compilation issues 
Fix compilations issues with linux safety builds

Bug 4506095

Change-Id: I2609611da6fe3110c730ef5ae67de1d503ab1700
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3081413
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Narayana Reddy P <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
 2024-02-28 11:15:59 -08:00
Bhadram Varka
b6134cbb6d Merge remote-tracking branch 'origin/dev/rel-37' into dev-main 
Merge the changes from rel-37 to dev-main for nvethernetrm repo.

Bug 4506095

Change-Id: Ie0509b8fd85fad5d55f0f967a433c4b7461527f1
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:33:10 +05:30
Bhadram Varka
ac97c26d7a NvEthernetRm: Fix SWUD 
Fix SWUD compilation errors

Bug 4449611

Change-Id: I28819d7a5c5f29affb1fa855aa899507e5c61020
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3072783
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2024-02-21 16:32:07 +05:30
Bhadram Varka
2e95e1f88a osi: dma: remove unreachable branch 
As a part of unit testing/integration testing Rx_PBL
value is always > 256. Remove the dead code and program
with max PBL value.

Bug 4284096

Change-Id: I04d75af28065360af452f4803ab0d7eebf66e3b0
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3070963
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2024-02-21 16:32:07 +05:30
Sanath Kumar Gampa
52c1d70334 osi: core: Removal of dead code 
As a part of unit testing cleaned up the
dead code and the redundunt checks

Bug 4284096

Change-Id: Ic0a8f68468b437e45d277cca5296da5232d4a5a7
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3069601
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:07 +05:30
Michael Hsu
10be2a6a3c nvethernetrm: Fix SWUD 
Change-Id: Iefc4bdab12ac26662555148d76f2ca972c81a43b
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3070826
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2024-02-21 16:32:07 +05:30
Bhadram Varka
9a2f67acf6 osi: core: cleanup the code 
Removed unneeded code as a part of clean up

Bug 4284096

Change-Id: I72d2315bd641f4a46c7f78029214c23599c9b831
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3063333
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Tested-by: Narayan Reddy <narayanr@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2024-02-21 16:32:07 +05:30
Bhadram Varka
d8397a68dc nvethernetcl: clean up the code 
o Remove redundent checks in the code
o Remove osi_dma_memset

Bug 4284096

Change-Id: I40e3af8be3fd9b5709e22084ba21dbef71d0d3d3
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3059343
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2024-02-21 16:32:07 +05:30
Narayan Reddy
9ec6ef675b osi: core: cleanup the code 
Clean up the code to remove unnecessary branches

Bug 4284096

Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Change-Id: I7cef09e14818016b68e0297cb8446d10880b1b13
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3058726
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2024-02-21 16:32:07 +05:30
Narayan Reddy
d68e9e1bdc osi: core: fix hsi configuration 
Enable below for the HSI configuration
  RXCRCERPIE of MMC_Receive_Interrupt_Enable
  TMOUTEN of MAC_FSM_Control
  OPE of MTL_DPP_Control
  TMOUTEN of MAC_FSM_Control
  FSM_TO_SEL of VR_XS_PCS_SFTY_TMR_CTRL

Bug 4437102

Change-Id: Iaef9bc3e8e44572fd953dbc4d846d871bb2d16a0
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3051420
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:07 +05:30
Rakesh Goyal
33aad27714 osi: core: Fix frp code 
Issue: input argument check missing
Fix: fix input argument check

Jira NET-1213

Change-Id: Ia651a33ba8181a1f98bfcf48fe3c9a39869fe3e6
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3052400
Tested-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2024-02-21 16:32:07 +05:30