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Narayan Reddy
016ce07cdc osi: core: combine config_rxcsum_offload 
Bug 3701869

Change-Id: I802497b6f973c69b994373697251964e532243f7
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2739139
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Narayan Reddy
33b312f9b4 osi: core: combine config_fw_err_pkts 
Bug 3701869

Change-Id: I5a0fe6e24d8aa69054a18f927d7135552482e8b9
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2739131
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Narayan Reddy
58b59f709e osi: core: combine flush_mtl_tx_queue 
Bug 3701869

Change-Id: Ifea025c0eb2d4373a348283aaa93eb7d0eca193a
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2739121
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Narayan Reddy
a19a5a80bd osi: core: combine set_speed 
Bug 3701869

Change-Id: Ie41b31e94f0ec0fb0b8d2d52cca7fafa81fd54c2
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2738062
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Narayan Reddy
9ab0b61bfa osi: core: combine set_mode 
Bug 3701869

Change-Id: I01d8e45b5818277441775d17e332c246ffa13a0e
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2738021
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Narayan Reddy
a67b77e501 osi: core: combine stop_mac 
Bug 3701869

Change-Id: I27a16c3f7c088be815b36d416ae068b5e60db143
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2738006
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Narayan Reddy
287352f3ad osi: core: combine start_mac 
Bug 3701869

Change-Id: Ice5ea78f32da1641cc847138869df97149eb72c9
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2737988
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
586252598f osi: core: common poll_for_swr 
Combine MGBE/EQOS HW level functions into single function.

Bug 3701869

Change-Id: I02c4881ec95cc5637867d68e560f4790c3548737
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2732106
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
101d2bc95c osi: dma: combine init_dma_channel 
This change combines EQOS and MGBE init into
single function and also removes the safety
registers validation.

Bug 200770328

Change-Id: I75b575a53318b10770b40d76e209b6f6aa9bbead
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2737141
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
9d859872fe osi: dma: combine rx_buf_len 
Bug 200770328

Change-Id: I573462275d13eba1417203eb44606913b7885552
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2736236
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
6d36080089 osi: dma: perform rx_pkt_cx memset after OWN bit check 
Bug 200770328

Change-Id: Ibf89ec6e6e3ffec845120ad4d6da159ef9782eb5
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2734689
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
da2c294c45 osi: dma: combine stop_dma 
Bug 200770328

Change-Id: I7ecf219ce16ca9bbdde1c5301eaa8accb105e048
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2734404
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
6bb29cfeb7 osi: dma: combine start_dma 
Bug 200770328

Change-Id: I106acca1253dd3d03b5e032f8b0acd7484828c58
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2734346
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
3ebcd062da osi: dma: combine update_rx_tail_ptr func 
Bug 200770328

Change-Id: I14a298a6fcfb9a869226580bba46ed0e470721bc
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2734314
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
7eb3b46b78 osi: dma: combine update_tx_tailptr func 
Bug 200770328

Change-Id: I6eba39420850ffc39b7eb0dad63829245faa0bde
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2734299
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
3f1f396f4d osi: dma: combine set_rx_ring_start_addr func 
Bug 200770328

Change-Id: Id5c4eec460daab8424e28ed77d46079be24811e7
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2734293
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
61c12c4e3f osi: dma: combine set_tx_ring_start_addr func 
Bug 200770328

Change-Id: Iae8994211d1b30dee8f43de5064919a5c62a39cd
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2734261
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
58ab37ee6f osi: dma: combine set_rx_ring_len func 
Bug 200770328

Change-Id: I3d1005b2540ec1de7b87b12a96ecf0c72befdd5a
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2734212
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
2da0c261a2 osi: dma: combine set_tx_ring_len func 
Bug 200770328

Change-Id: I86670a482539da2bf164f0f3f3292d338cec28a4
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2734191
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
1ed620e7d6 osi: macsec: fixes for misra defects 
Below are the rules addressed

Rule: MISRA_C-2012_Rule_15.5 Diff: -90
Rule: MISRA_C-2012_Rule_2.5 Diff: -34
Rule: MISRA_C-2012_Rule_8.13 Diff: -5
Rule: MISRA_C-2012_Rule_8.6 Diff: -1

Rule: CERT_INT31-C Diff: -2

Bug 3691236

Change-Id: I0b943b7626ea47e34eee585e42f0c9b98d67a7f4
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2732627
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Rakesh Goyal
df87f05184 core: delete stale TX time stamp from OSI hw queue 
Issue: In corner case TX TS form hardware in OSI list,
not claimed by OSD which lead to stale time at OSI.

Fix: if there is no timestamp read from OSD in last
2 seconds, remove that time stamp from OSI list

Bug 3620425

Change-Id: I0a77cfe716aa13ddf49bdd32f56fb49b74b9d265
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2731974
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Narayan Reddy
4621665fca osi: core: Fix MISRA issues 
Fixed straight forward MISRA issues

===== DIFF ======
Total misra violation count changed by -319
Rule: MISRA_C-2012_Directive_4.4 Diff: -3
Rule: MISRA_C-2012_Directive_4.6 Diff: -32
Rule: MISRA_C-2012_Directive_4.9 Diff: 3
Rule: MISRA_C-2012_Rule_10.1 Diff: -4
Rule: MISRA_C-2012_Rule_10.3 Diff: -2
Rule: MISRA_C-2012_Rule_10.4 Diff: -21
Rule: MISRA_C-2012_Rule_11.1 Diff: -20
Rule: MISRA_C-2012_Rule_12.1 Diff: -74
Rule: MISRA_C-2012_Rule_15.5 Diff: 1
Rule: MISRA_C-2012_Rule_15.7 Diff: -2
Rule: MISRA_C-2012_Rule_16.1 Diff: -1
Rule: MISRA_C-2012_Rule_16.3 Diff: -1
Rule: MISRA_C-2012_Rule_17.7 Diff: -5
Rule: MISRA_C-2012_Rule_2.5 Diff: -157
Rule: MISRA_C-2012_Rule_8.6 Diff: -1
Rule: Total Diff: -319

JIRA NET-96
Bug 3695218

Change-Id: I221f95aaf23e9214fde21632b68425b705552752
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2735077
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
89d76f5336 osi: macsec: Update the sak len to 256 
Bug 3673435

Change-Id: I841a9d631ff1b186f1a59e29d26822698b6e6e3d
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2730246
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
5daa8d86da osi: core: support for suspend/resume IOCTL's 
Issue: While ethernet going into suspend all registers
of controllers saved through save_registers IOCTL and
same will be restored during resume. Register restoring
without following sequence will lead to multiple issues.

Fix: For every dynamic configuration save the input
parameters and use the same parameters through API's
to restore the controller configuration. API approach
will follow the specific sequence for programming the
controller registers.

Bug 3665476

Change-Id: Ia31303daf0ba5c78f3eb5cd2706a1ce420536539
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2662333
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Om Prakash Singh
f24879b270 ivc: add change to support diag interface 
Add below IVC commands that will be use by nvethmgr
for diag test:
 nvethmgr_get_status
 nvethmgr_verify_ts
 nvethmgr_get_avb_perf

Bug 3620612
Change-Id: I900e97e12988035648b86fe2e8becaa6f312b256
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2709692
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Om Prakash Singh
fc32c7794b osi: core: enable FSM_CONTROL.TMOUTEN 
1) set NTMRMD value 2 to avoid timeout at the time of interface up
2) FSM_CONTROL.TMOUTEN bit

Bug 3584387

Change-Id: I46cba0cc2322e4752f4c9abff0bd72f01d5b9fd2
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2713538
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Rakesh Goyal
59f0ab1185 osi: core: removed unused code 
Issue: Called same function 2 times in interrupt
handler.

Fix: Remove extra call and write operation to
status register.

Change-Id: Iaa2a4815c90430e293b1d66b45855035cc03e6c4
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2711620
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Bhadram Varka
01da9dcc09 osi: dma: remove unused functions 
Remove below functions which are not used.
osi_enable_chan_tx_intr
osi_disable_chan_tx_intr
osi_disable_chan_rx_intr
osi_enable_chan_rx_intr

Bug 3503523

Change-Id: I1b414c3d763922d3d87b29516de8d0bdc0ac5526
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2714137
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Om Prakash Singh
e494f847b3 osi: dma/core: add interface to configure debug interrupt 
add interface to configure debug related interrupt

Bug 3600647
Change-Id: Iae43ceb441254b89a5b32ef9441ce42fca812e49
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2703337
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
759a471d35 osi: dma: interrupt enable/disable retry 
Adds retry for interrupt enable/disable and
combine interrupt handling part for EQOS/MGBE

Bug 3503523

Change-Id: Icc8b10cd786c878972e2e508ede3edb8d52addf8
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2652907
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
1d10e8c3ff osi:macsec: Changs to program key thorugh TzVault 
Bug 3568672

Change-Id: I35607905da986c50737f253874c090368e017388
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2676624
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Tested-by: Mahesh Patil <maheshp@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
3922b834da osi: dma: Support for variable Tx/Rx ring length 
o Adds support for variable Tx/Rx ring length
o Default ring size 1K used if ring size passed
from OSD is zero.

Bug 3489814

Change-Id: I9c57b8d9e0c424bf39633998e0845fc97975de8f
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2652960
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Nagaraj Annaiah
6c550940bc osi core: Fix macsec and eqos compiler warnings for HVRTOS 
Issue:
1. conversion to ‘nveu16_t {aka short unsigned int}’ from
‘unsigned int’ may alter its value.
2. mac_tcr may be used uninitialized in this function
3. Explicitly assigning value of variable of type 'nveu32_t' (aka
'unsigned int') to itself - mac_tcr |= mac_tcr;

Fix:
1. Add Typecast before conversion.
2. init mac_tcr to zero
3. Remove unused get_rx_err_stats function.
4. Remove mac_tcr from default.

Bug 3562777

Change-Id: I9030bf73d13ffd1d848266301a1df97144eaa391
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2707197
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Om Prakash Singh
0c754dc009 core: add pcs register readback after write support 
As per T23X-MGBE_HSIv2-14 requirement for PCS register
we need to perform readback for each write operation
to verify write operation was successful

Bug 3606649
Change-Id: I7cca6baa43feaa4207b6158f0abc796e656338dd
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2700845
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Hareesh Kesireddy
e0e2a6b200 osi: remove extra args for tx complete callback 
Dma phy address, virtual address and packet length can be
obtained from tx swcx structure. Hence passing
pointer to tx swcx is sufficient. In future, if more information
from osi is needed, it can be embedded into tx swcx itself rather than
adding more arguments to osd tx complete call back.

Bug 3576506

Change-Id: I061ea27cd1b4d68c19f3e9d95a247505c511ce0c
Signed-off-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2700341
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Bhadram Varka
037b30e505 osi: core: program 0xF's while deleting MAC address 
Issue: After deleting the MAC address its observed that
old MAC address values are there in low/high registers
which creates confusion while checking the register dump/

Fix: Program 0xF's in low/high registers while deleting
the MAC address.

Bug 3609583

Change-Id: I1d93d6bc31eb1c49e7641ff97f73d0ed4bb0345f
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2702855
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
0a01e7abf3 osi:macsec reduce complexity of MACSEC APIs 
Issue: Complexity of OSI APIs cannot be greater than 10

Fix: Split the functionality of complex APIs to multiple APIs.
Added De-oxygen comments as well for macsec osi APIs

Bug 3460422

Change-Id: I2383904d8581efa54a8d2ec2f85a50cb12b22e89
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2688990
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
325e60b63c osi:macsec: Fix MISRA defects in QNX OSD 
Dependent change made in osi to fix a misra defect in QNX OSD

Bug 3598679

Change-Id: Ie6b48a6d1cb8d34b00c437cc3b57971ad447fa3b
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2695627
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Om Prakash Singh
9775acba84 osi: core: fix XPCS_REG_VALUE_MASK 
Issue: PCS register read/write is failing due to wrong value of
 XPCS_REG_VALUE_MASK;

Fix: update XPCS_REG_VALUE_MASK value to 0x3FF

Bug 3591736

Change-Id: Id62aff5f8749b94810475ff79665899a10bec3e4
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2701996
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bibhay Ranjan
83082b51e3 nvethernetrm: fix code defects 
Issue: SPARSE errors
Fix: Fix code as per the guidelines in the errors

Bug 3568991

Change-Id: If52bf7d5b3e8d4ca10a254e802ee5257a8816633
Signed-off-by: Bibhay Ranjan <bibhayr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2688520
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Nagaraj Annaiah
b3b3455115 osi core: Fix compiler warnings for HVRTOS 
Issue: Unused variables are treated as errors with HVRTOS compiler.

Fix:
1. Add unused attributes macro for unused function arguments.
2. Fix typecast errors.
3. Add flag to check if ethernet server status, this is needed to
   skip check for function pointer validation.

Bug 3562777

Change-Id: I0a4a36fb330c580d1879f46304842c610e62316c
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2670097
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
f238abc016 osi:macsec: Separate lut_status for each IP 
Issue: If macsec is created on EQOS and then created on MGBE, we are
over writing the lut_status of EQOS with MGBE lut_status.

Fix: Create different lut_status structure in osi_core so that each
IP will have its own lut_status structure.

Bug 3587231

Change-Id: I826c3d210ed18350140f1cbcb41b748550f92844
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2690839
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Om Prakash Singh
0ffef9743a osi: macsec: set ICV error threshold to 1 
Issue: default IVC error threshoud 16k. Which is not same as
  Other error like RX/TX CRC error. It is conflicting with
  expection of DT based error reporting threshold
  "nvidia,hsi_err_count_threshold"

Fix: Set ICV error threshold to 1 to match the other error interrupt
 frequnecy.

Bug 3543410

Change-Id: Ic64fcdaa007e9a57823515dc8f970d636b34eaa1
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2696380
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
8cad7eb750 osi:macsec: Fix osi macsec Misra/coverity issues 
Issue: Found aroung 900 MISRA?COVERITY defects on
OSI MACSEC changes

Fix: Fixed the defects by making minor changes without
impacting the functionality

Removed calling poll_for_dbg_buf_update, poll_for_kt_update
and poll_for_lut_update before lut_write as we are anyhow
polling after the lut_write

Bug 3460422

Change-Id: Ib33e8188cd90472b851732f0936c3e29142bb4a3
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2618714
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Om Prakash Singh
a7c927d757 osi: core: add support for HSI 
1) Add OSI IOCTL to enable HSI feature at runtime
2) Enable LIC interrupt for Correctable, Uncorrectable and
   Parity error
3) Program register to enable safety feature

Bug 3543410

Change-Id: I8a9f33bab72eb37e8aa64c16c610be6e5271c7f8
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2670989
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
a0d542c61c osi:macsec:Change to update MACSEC MTU 
Issue: If MTU is increased after Supplicant is initialized
we are not updating the MACSEC MTU so the frames will get
dropped as the MACSEC MTU is lesser than the frames received

Fix: Changes to update the MACSEC MTU along with MAC MTU

Bug 3577143

Change-Id: Iff61099ff2a9ae1f6fe6e48948d842604fd9e2c4
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2685281
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Mahesh Patil
4cc2559b5c core: eqos: Fix pad calibration change coverity 
Fixed pad calibration change coverity issue

Bug 3461002

Change-Id: I2e040dfcd4c1f7fd34637cd6b7c43e5ab3d9d7c4
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2686833
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Gaurav Asati
ebe520fb28 osi: Change barrier. 
Issue: Using "asm volatile" is leading to compilation
issues with new coverity version.

Fix: Change "asm volatile" to __sync_synchronize as
same functionality is achieved without any issues.

Bug 200699678

Change-Id: I685d27efab48443f2d2a664ae803e724cccde3fc
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2481631
(cherry picked from commit 63cdb70b76f3ae2b214d1ca371d42bdc7680e617)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2486720
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Bhadram Varka
2c8f5614f9 osi: mgbe: fix MGBE channels mask 
Bug 3420115

Change-Id: If086f090082bda7972d01776543f24c8cf9b060f
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2680952
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Sanath Kumar Gampa
5663a3cf40 osi:macsec: fix coverity defect 
Issue: Coverity issue : "Unchecked return value"

Fix: Check the return value and print error

Bug 3460422

CID 10127972

Change-Id: I78df96d969cbd23b22969cc02b79a64c17e8fe18
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2678123
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30