Issue: DMA will be in suspend state if there is no buffer allocation
happen to HW. If DMA is in suspend state, no interrupt will
occur for channel which leads to not calling of
osd_receive_packet().
Fix: Whenever there is rx buffer kernel memory allocation failure, desc
will be updated with reserve rx buffer. This reserved buffer is
already allocated at the time of ether_open. Aim of same to
make sure rx DMA always have buffer and not go in suspend state.
Bug 200650229
Change-Id: If8ff5f2dbfb631e8d1bc2383f958ed389643d7a4
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2399010
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Issue: RM server is not aware of what L2 address
should be removed from local list and register as
index passed by OSD/OSI_Core may mis-match in case
multi FD instance usecase.
Fix: As RM server finds index/offset on its own corresponding
to MAC address, Core software should reset AE bit and pass
other user provided argument as it is. Legacy
way of removing L2 address is still supported.
Bug 200626200
Change-Id: I43919827422d176334198ee09e822047b606da79
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2359969
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
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Issue:
When 2 OSD's are part of single compilation process, only one
OSD can be linked at compile time. This causes issues in handling
TX and RX communication from OSI to OSD.
Fix:
Add callbacks for TX and RX communication which can be registered by
OSD to receive callback communication from OSI for TX and RX. Use
existing API's if OSD doesn't register a callback.
Bug 200603660
Change-Id: I0b246a78a3d1bc4bb690e1ad7dac82108500b625
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2343967
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Adds VM IRQ handling support at OSI layer and adds
corresponding support for EQOS as well.
Need to pass below parameters from DT -
o Number of VM IRQ's assigned per OS/VM.
o Number of VM channels assigned to a VM IRQ.
o List of DMA channels assigned to a VM IRQ.
Below is the sample DT representation -
vm_irq_config: vm-irq-config {
nvidia,num-vm-irqs = <4>;
vm_irq1 {
nvidia,num-vm-channels = <2>;
nvidia,vm-channels = <0 1>;
};
vm_irq2 {
nvidia,num-vm-channels = <2>;
nvidia,vm-channels = <2 3>;
};
vm_irq3 {
nvidia,num-vm-channels = <2>;
nvidia,vm-channels = <4 5>;
};
vm_irq4 {
nvidia,num-vm-channels = <2>;
nvidia,vm-channels = <6 7>;
};
};
ethernet@<base_addr> {
[...]
nvidia,vm-irq-config = <&vm_irq_config>;
[...]
}
Bug 200546379
Change-Id: Id20780d573aa70baf42b003728ba416ed61832d2
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2250403
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2198595
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Issue:
When virtualization is enabled and registers are accessed during
UDP line rate transfer or receive then spurious common interrupts
gets generated for buffer unavailable which hangs the ethernet server.
Fix:
1. Add Flag which decides virtualization is enabled(1) or
disabled(0)
2. If virtualization is enabled then disable receive and transmit
buffer Unavailable interrupts.
Bug 2694285
Change-Id: I2c65b724c15abf5d4f0101d96b067ad9f4f3d99e
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2330034
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
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GVS: Gerrit_Virtual_Submit
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Issue: When JE is set, HW will accept any valid packet on Rx
upto 9K or 16K (depending on GPSCLE bit), irrespective of
whether MTU set is lower than these specific values. When
Rx buf len is allocated to be exactly same as MTU, HW will
consume more than 1 Rx desc to place the larger packet.
Fix: Drop Rx packets which are longer than currently set
MTU since HW cannot drop them.
Bug 2870545
Signed-off-by: narayanr <narayanr@nvidia.com>
Change-Id: I869f4858f8d2b502a3965dc2ca40cda8805f9886
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2308379
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Issue: During SOC suspend, the MAC is placed in reset.
This causes all dynamic configurations done by
SW on the MAC core registers is lost. When SOC
resumes, MAC is initialized to power-on-default
configuration, while other SW components still
have previously set configuration. This results
in mismatch between HW/SW configuration.
Fix: Add APIs osi_save_registers(), osi_restore_registers()
to backup and restore the MAC core configuration
registers before suspend and after resume respectively.
Bug 200561046
Change-Id: I6d7b39d39a6f3fa882cfd905bc49a5850163ea4c
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2267390
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Tested-by: Narayan Reddy <narayanr@nvidia.com>
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Issue: osi_process_tx_completions is run in the BH for
processing Tx done irq. This function always loops
till the Tx status for all packets that are Tx'd so
far is processed.
1) The NAPI budget for this Tx completions handler is
not honored.
2) The variable 'processed' is expected to keep track
of Tx'd packets. Currently it is counting Tx'd descriptors.
There can be multiple Tx descriptors consumed for one packet.
Fix: 1) Add budget parameter to osi_process_tx_completions() API.
2) Break out of loop in this API if packets to process
exceeds budget
3) Increment the processed count variable only after checking
last descriptor for a packet.
Bug 2756439
Change-Id: Id538343f6853881ea41109b8b46c8d0e82dce98a
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2237822
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Praveen Mallaiah <pmallaiah@nvidia.com>
Tested-by: Praveen Mallaiah <pmallaiah@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
GVS: Gerrit_Virtual_Submit
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Add an API to configure the EEE LPI mode.
Tx LPI is enabled with a default entry time of 1sec.
The MAC controller has capability to automatically
enter LPI mode when all transmissions are complete.
Bug 2594864
Change-Id: I765ddfda908b1922abd46c11fa217a35fe6190f1
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2160787
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Issue:
Data packets sent via EQOS hardware are not
following any packet gaping. The AVB use-cases
have different timing requirements for class A
data packets. For example, the time difference
between two class A data packets are supposed
to be 125 microseconds for audio data of
frequency 48 kHz.
Fix:
Add slot function support to schedule
the data fetching from the system memory
by the DMA. This will help the AVB SW stack
timing requirements for class A data.
Bug 200545374
Change-Id: Id7c606f7491a423051667811bd6d459ee58f6700
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2222282
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
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Issue: APIs like osi_clear_tx/rx_intr, osi_update_rx_tailptr
are redundant. The operations that are done in these
functions can be included as part of other existing
OSD-OSI interface API. OSD need not micro-manage the
hardware controller by using such fine grain APIs.
Fix: Remove the redundant APIs and implement their functionality
as part of existing APIs.
Bug 2715391
Change-Id: I47851c204988475cac1cadf6fe678d7d446a3cc3
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2211093
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
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Receive timestamp for a received packet will be in context descriptor
which is immediate of normal descriptor (has valid packet data)
In current case nvethernet driver only unmap normal descriptor buffer
address and provide the buffer to the network stack for data processing.
Context descriptor buffer is not unmapped which leads to running out of
IOVA space for the new buffers.
Context descriptor buffer can be used as is since that is not provided
to the network stack. So this change to a flag for context descriptor.
Based on this flag OSD can skip new buffer allocation and mapping for
the context descriptor and use already allocated buffer.
Bug 2700522
Change-Id: I18c8ebe39bf2eaaaeb13a9de3c9595cbe2ada45d
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214726
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