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3fff0cd9baffb3b2f8a7c08ba7e4041a8b25b51d
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45 Commits

Author SHA1 Message Date
Narayan Reddy
3fff0cd9ba osi: core: fix Doxygen warnings 
1) Fix Doxygen warnings
2) include debug.h code only when OSI_DEBUG
is defined

JIRA NET-570

Change-Id: I5d002b959925bec3898cc2faafe3f506b3c9bd22
Signed-off-by: Narayan Reddy<narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2847327
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-02-04 16:49:50 -08:00
Bibhay Ranjan
91511ff641 nvethernetrm: Log compilation using LOG_OSI flag 
Based on the cflag LOG_OSI logging code will be
compiled

Bug 3759976
Bug 3954687

Change-Id: Ief57c926bc4d3b1d0d251e5da77d0eb73d928d62
Signed-off-by: Bibhay Ranjan <bibhayr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2811077
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-01-27 20:00:22 -08:00
Mahesh Patil
8b8527d5f0 macsec: Rename LOG to MACSEC_LOG 
Rename LOG to MACSEC_LOG to avoid conflicts with
other modules LOG macro

Bug 3338608

Change-Id: Ib746dc4cddd835308cf6a6da8e79135c566a8135
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2798519
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-12-09 15:12:45 -08:00
Bibhay Ranjan
aa21c9e4bf nvethernet: Fix the incorrect code in CFLAGS 
Issue:
Few places incorrect CFLAGS are used.
OSD based flags cannot be used in OSI

Fix:
Move the code under correct CFLAGS
remove the OSD based codes

Note:
The OSD based logging need to be reimplemnedted
by  the macsec module.

Bug 3759976

Change-Id: I407b945a24028792f146bc08adf67428612978c3
Signed-off-by: Bibhay Ranjan <bibhayr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2811917
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-12-05 20:33:14 -08:00
Om Prakash Singh
36a6a3d487 osi: core: macsec: enable SECURE_REG_VIOL intr 
enable SECURE_REG_VIOL interrupt to generate
uncorrected Error for illegal access errors
for MACSEC Registers

Bug 3590939

Change-Id: I4f50c1b709ed3662eb6062dcbbbe42a8e36f101c
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2767836
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-11-09 11:18:14 -08:00
Narayan Reddy
4c85b5e49e osi: core: Fix MISRA issues 
===== DIFF ======
Total misra violation count changed by -71
Rule: MISRA_C-2012_Directive_4.5 Diff: -3
Rule: MISRA_C-2012_Rule_11.1 Diff: -5
Rule: MISRA_C-2012_Rule_11.3 Diff: -1
Rule: MISRA_C-2012_Rule_11.5 Diff: 1
Rule: MISRA_C-2012_Rule_12.1 Diff: -6
Rule: MISRA_C-2012_Rule_12.2 Diff: -7
Rule: MISRA_C-2012_Rule_15.1 Diff: -1
Rule: MISRA_C-2012_Rule_15.6 Diff: -1
Rule: MISRA_C-2012_Rule_16.1 Diff: -1
Rule: MISRA_C-2012_Rule_16.3 Diff: -1
Rule: MISRA_C-2012_Rule_17.7 Diff: -4
Rule: MISRA_C-2012_Rule_17.8 Diff: -5
Rule: MISRA_C-2012_Rule_2.4 Diff: -4
Rule: MISRA_C-2012_Rule_2.5 Diff: -18
Rule: MISRA_C-2012_Rule_20.5 Diff: -1
Rule: MISRA_C-2012_Rule_5.6 Diff: -1
Rule: MISRA_C-2012_Rule_5.8 Diff: -1
Rule: MISRA_C-2012_Rule_5.9 Diff: -4
Rule: MISRA_C-2012_Rule_8.3 Diff: -2
Rule: MISRA_C-2012_Rule_8.9 Diff: -5
Rule: MISRA_C-2012_Rule_9.5 Diff: -1
Rule: Total Diff: -71

Bug 3695218

Change-Id: I9bd904f8a77195ca34fb2d47639a214f0083ccf7
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2776281
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-09-29 19:38:37 -07:00
Sanath Kumar Gampa
0addd2969b osi: macsec: Fix CERT INT31-C issues in macsec 
Bug 3745813

Change-Id: I36ea0483857d82bc60277be33f279057689ffef1
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2763014
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-09-15 07:25:29 -07:00
Mahesh Patil
7a5d06ad23 osi: core: Change macsec log level 
Change macsec log level for general prints and disable DEBUG_MACSEC
macro for safety build

Bug 3708920

Change-Id: Iec9b28d0e1eeb4ceb17767d7311cb7945a42009d
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2745325
Reviewed-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-08-10 09:50:51 -07:00
Narayan Reddy
f971d40513 osi: core: skip out not required code for Safety QNX 
Bug 3701869

Change-Id: Ic1f676708ff6e3faf7dbed09f0e7048448252e57
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2739627
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Bhadram Varka <vbhadram@nvidia.com>
 2022-08-06 05:04:15 -07:00
Sanath Kumar Gampa
aedaf1db80 osi: macsec API cleanup 
Bug 3709820

Change-Id: I935ca2d373bea1b7d8b15f790ffc3719fa9d0881
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2738227
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-07-26 10:06:20 -07:00
Sanath Kumar Gampa
b3d2774241 osi: macsec: fixes for misra defects 
Below are the rules addressed

Rule: MISRA_C-2012_Rule_15.5 Diff: -90
Rule: MISRA_C-2012_Rule_2.5 Diff: -34
Rule: MISRA_C-2012_Rule_8.13 Diff: -5
Rule: MISRA_C-2012_Rule_8.6 Diff: -1

Rule: CERT_INT31-C Diff: -2

Bug 3691236

Change-Id: I0b943b7626ea47e34eee585e42f0c9b98d67a7f4
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2732627
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-07-08 13:37:45 -07:00
Om Prakash Singh
6bdbdb32c6 osi: dma/core: add interface to configure debug interrupt 
add interface to configure debug related interrupt

Bug 3600647
Change-Id: Iae43ceb441254b89a5b32ef9441ce42fca812e49
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2703337
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-05-16 17:41:38 -07:00
Nagaraj Annaiah
bdc90d7ddc osi core: Fix macsec and eqos compiler warnings for HVRTOS 
Issue:
1. conversion to ‘nveu16_t {aka short unsigned int}’ from
‘unsigned int’ may alter its value.
2. mac_tcr may be used uninitialized in this function
3. Explicitly assigning value of variable of type 'nveu32_t' (aka
'unsigned int') to itself - mac_tcr |= mac_tcr;

Fix:
1. Add Typecast before conversion.
2. init mac_tcr to zero
3. Remove unused get_rx_err_stats function.
4. Remove mac_tcr from default.

Bug 3562777

Change-Id: I9030bf73d13ffd1d848266301a1df97144eaa391
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2707197
Reviewed-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-05-09 15:46:39 -07:00
Sanath Kumar Gampa
62917832dc osi:macsec reduce complexity of MACSEC APIs 
Issue: Complexity of OSI APIs cannot be greater than 10

Fix: Split the functionality of complex APIs to multiple APIs.
Added De-oxygen comments as well for macsec osi APIs

Bug 3460422

Change-Id: I2383904d8581efa54a8d2ec2f85a50cb12b22e89
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2688990
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-04-27 20:18:14 -07:00
Nagaraj Annaiah
221989d875 osi core: Fix compiler warnings for HVRTOS 
Issue: Unused variables are treated as errors with HVRTOS compiler.

Fix:
1. Add unused attributes macro for unused function arguments.
2. Fix typecast errors.
3. Add flag to check if ethernet server status, this is needed to
   skip check for function pointer validation.

Bug 3562777

Change-Id: I0a4a36fb330c580d1879f46304842c610e62316c
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2670097
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-21 15:52:01 -07:00
Sanath Kumar Gampa
70fdb56a05 osi:macsec: Separate lut_status for each IP 
Issue: If macsec is created on EQOS and then created on MGBE, we are
over writing the lut_status of EQOS with MGBE lut_status.

Fix: Create different lut_status structure in osi_core so that each
IP will have its own lut_status structure.

Bug 3587231

Change-Id: I826c3d210ed18350140f1cbcb41b748550f92844
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2690839
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-04-15 04:29:14 -07:00
Om Prakash Singh
5e933f3234 osi: macsec: set ICV error threshold to 1 
Issue: default IVC error threshoud 16k. Which is not same as
  Other error like RX/TX CRC error. It is conflicting with
  expection of DT based error reporting threshold
  "nvidia,hsi_err_count_threshold"

Fix: Set ICV error threshold to 1 to match the other error interrupt
 frequnecy.

Bug 3543410

Change-Id: Ic64fcdaa007e9a57823515dc8f970d636b34eaa1
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2696380
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-14 17:05:08 -07:00
Sanath Kumar Gampa
37ab92517f osi:macsec: Fix osi macsec Misra/coverity issues 
Issue: Found aroung 900 MISRA?COVERITY defects on
OSI MACSEC changes

Fix: Fixed the defects by making minor changes without
impacting the functionality

Removed calling poll_for_dbg_buf_update, poll_for_kt_update
and poll_for_lut_update before lut_write as we are anyhow
polling after the lut_write

Bug 3460422

Change-Id: Ib33e8188cd90472b851732f0936c3e29142bb4a3
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2618714
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-04-11 13:17:05 -07:00
Om Prakash Singh
65f78eba09 osi: core: add support for HSI 
1) Add OSI IOCTL to enable HSI feature at runtime
2) Enable LIC interrupt for Correctable, Uncorrectable and
   Parity error
3) Program register to enable safety feature

Bug 3543410

Change-Id: I8a9f33bab72eb37e8aa64c16c610be6e5271c7f8
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2670989
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-09 16:26:37 -07:00
Sanath Kumar Gampa
6dc6e28282 osi:macsec:Change to update MACSEC MTU 
Issue: If MTU is increased after Supplicant is initialized
we are not updating the MACSEC MTU so the frames will get
dropped as the MACSEC MTU is lesser than the frames received

Fix: Changes to update the MACSEC MTU along with MAC MTU

Bug 3577143

Change-Id: Iff61099ff2a9ae1f6fe6e48948d842604fd9e2c4
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2685281
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-07 03:18:33 -07:00
Sanath Kumar Gampa
3ba0e448b7 osi:macsec: fix coverity defect 
Issue: Coverity issue : "Unchecked return value"

Fix: Check the return value and print error

Bug 3460422

CID 10127972

Change-Id: I78df96d969cbd23b22969cc02b79a64c17e8fe18
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2678123
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-03-14 07:39:52 -07:00
Sanath Kumar Gampa
92924602ba osi:macsec: Address SC over-writing issue 
Issue: In multi VM use case if multiple SCs are added using supplicants
Then we may over-write an exisitng SC if we stop and start the first
supplicant

Fix: Before adding an SC find the vacant SC slot

Bug 3522740

Change-Id: Ic10f7a542a01328876b0103c34cc1115bfd426b5
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2675003
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-03-09 21:04:38 -08:00
Sanath Kumar Gampa
65a9cb659e macsec: get next PN and IRQ stats cmd with server 
Some of the commands such as get next PN and irq stats
are not working if thernet server is enabled, fixed the same.
And also moved HKEY generation to OSD, to avoid dependency on
Crypto libs on LK. devmemr/w can read/write to macsec addresses

Bug 3522740

Change-Id: Id3b328cfd83aa976ef5bde8adc057588bb6fed38
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2652212
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-02-27 18:07:30 -08:00
Mahesh Patil
393cfedcf7 nvethernetrm: macsec qnx OSI changes 
Macsec qnx driver OSI changes

Bug 3338180

Change-Id: I2ad4f1b8b919893f2823a120973c1805b58bbb88
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2612659
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Tested-by: Sanath Kumar Gampa <sgampa@nvidia.com>
 2022-02-02 21:40:44 -08:00
Sanath Kumar Gampa
fb4dde440b osi: Avoid macsec and fpe coexistance on MGBE 
Issue: Internal FIFO over/underflows if MACSEC and FPE are enabled on MGBE
interafce and pre-emptable and express frames are sent in interleaved
fashion

Fix: Do not allow enabling any of MACSEC and FPE if the other is already
enabled.

Bug 3484034

Change-Id: Ifc80eb9333c836652a86362a1f7788a0ce70dbb7
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2647788
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-01-20 15:36:57 -08:00
Sanath Kumar Gampa
f1e4661f1e osi:macsec:Changes to enable AN after key program 
Issue: In longer stress tests we see unint_key_slot
errors if the key programing is done after AN is
enabled.

Fix: Fix is to program the key and then enable AN.
Done some code cleanup as well

Bug 3422356

Change-Id: I7aeb2f9ab681509b54e9f6763464dfedb46cd26e
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2626062
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-12-14 02:45:34 -08:00
Sanath Kumar Gampa
d190c203da osi:macsec:Fix to address sc_an_not_valid counter 
Issue: tx_sc_an_not_valid counter is increasing in
stress tests when there is AN roll over happens

Fix: Program the SCI LUT with vaid AN map and then
enable AN in sc_state LUT

Bug 3422356

Change-Id: I17021d435076ff94367a58a4c74b50124c97d68a
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2623649
GVS: Gerrit_Virtual_Submit
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-12-02 07:39:53 -08:00
Sanath Kumar Gampa
c52ad89f9d osi:macsec:lowest pn changes to enable sa 
Enhancement to receive lowest_pn from supplicant
as part of receive AN enable

Bug 3371004

Change-Id: If81f8449f7ebda996c95117e2c84722fdc57c5d0
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2619949
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-11-11 20:39:08 -08:00
Sanath Kumar Gampa
b8e03a8b43 osi:macsec: changes to send next PN to supplicant 
As part of MKA, supplicant requests for Next PN
used by SecY. Added changes to OSI to send to
send the Next PN for a given SCI and AN.

Bug 3371004

Change-Id: Iaf001ba5e6b5480396e2f774a42927831160a2e5
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2614365
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-10-28 01:06:06 -07:00
Sanath Kumar Gampa
2a3bdce7c8 nvethernetrm: MTL_EST CTOV config for MACSEC 
Issue: h/w requirement to change the MTL_EST value
depending on MACSEC

Fix: Change the value in MACSEC enable/disable flow

Bug 200630202

Change-Id: Iefdb14e44841941ab3e8f8c116746b0db6c63ba5
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2604830
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-10-14 12:02:52 -07:00
Nagaraj Annaiah
801815742d osi: core: macsec: Add macsec fix 
Issue: macsec doesn't work for virtualization.

Fix:
1.Move virtualization checks before address check.
2. Copy PTP config to ioctl structure.

Bug 2694285

Change-Id: I81f47cf23e37a62a3e5b8ecece8ae905ec1a5df3
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2587833
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-15 19:06:59 -07:00
Mahesh Patil
3af55e0c58 nvethernetrm: change MAC ipg as per macsec req 
Change MAC ipg value as macsec IAS requirement when
macsec is used

Bug 3335658

Change-Id: Ie681bb0a66b256c32ac6093114fe29c65bf20a07
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2558031
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-10 02:10:19 -07:00
Mahesh Patil
f7e004c653 nvethernetrm: adjust macsec mtu configuration 
Adjust macsec mtu setting as osi_core->mtu is not reducing
mtu for macsec SECTAG

Bug 200730979

Change-Id: I69399b5b9ebd04b5c2c8964bab5b6635f66cfef8
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2558623
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-07-15 17:16:57 -07:00
Mahesh Patil
330acf2e3d nvethernetrm: address review comments 
- Convert primitive data type to nv_ type's
- Replace debug pr_ prints with OSI_CORE_ print macro's
- Add all macsec register macro's with prefix MACSEC_
- Update all osi function header as per 5.2 coding guidelines(PLC)
- Remove printk.h header file and use OSI_CORE_ERR macro's in all prints
- Implement clean up LUT's in add_upd_sc() and del_upd_sc()

Bug 3264523

Change-Id: Ie41097c85fbcb90ce0c4cac470fe0f068ed22247
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2548476
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-07-13 19:27:38 -07:00
nannaiah
41b0480d3b nvethernetrm: Update IVC support for macsec 
1. Cleanup ivc_cmd to remove unwanted commands.
2. Update macsec IVC API's.
3. Add HAL read and write register.

Bug 2694285
Bug 2694285

Change-Id: I4d120b7bcfdc9ed65e2bf35a54fa4233a8b6e534
Signed-off-by: Nagaraj annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2529496
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
 2021-06-21 07:07:10 +05:30
Mahesh Patil
e63cf8ff80 nvethernetrm: Remove osd callback from osi 
Remove calling osd callback from osi to program SAK and
program SAK from OSD itself.

Bug 3308383

Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Change-Id: I2b27cea66bd9770aec52ed53ba430eb276cf73f7
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2528707
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-06-21 07:07:10 +05:30
Mahesh Patil
d3fd593f50 nvethernetrm: Update mac/macsec init 
Update mac/macsec init programming
1. macsec clock and reset programming order at init and deinit
2. macsec SOT values as per macsec IAS
3. mac IPG values as per macsec IAS

Bug 3266535

Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Change-Id: Ie6351f632b0ac7487ec7b5bfd34d9337d3782a59
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2506488
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-06-21 07:07:10 +05:30
Bhadram Varka
1858fe9406 osi: macsec: fix build issue 
Bug 200722499

Change-Id: I75cd89350954bc8ed7632ec0788d2efe7c6848aa
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2522868
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
 2021-06-21 07:07:10 +05:30
Mahesh Patil
96cd8fb10d nvethernetrm: Add aes 128/256bit macsec config 
Adding aes 128/256 bit config support through sysfs node

Bug 3257779

Change-Id: Ic1736b309a28faa7591184167a94156ca816fb57
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2484200
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2021-06-21 07:07:10 +05:30
Mahesh Patil
474ed78e6d nvethernetrm: Enable key program through TZ 
Enabling macsec key's programming using TZ

Bug 3246511

Change-Id: I1e7633b042e1ebedef78fff9812aeaaa2480a1c4
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2478489
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2021-06-21 07:07:10 +05:30
nannaiah
6644553603 osi: Add virtualization fix. 
- Change osi_readl to osi_readla
- Change osi_writel to osi_writela
- Add IVC macsec commands.
- Add OSI_MGBE_MAC_3_00 as valid list of version.
- Disable validate_func_ptrs as it returns failure.

Bug 2694285
JIRA T23XMGBE-118

Signed-off-by: Nagaraj annaiah <nannaiah@nvidia.com>
Change-Id: I49187c0decb3de4184b7ef5e3a2e553a60c1d54f
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2515254
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2021-06-21 07:07:10 +05:30
Mahesh Patil
2e5440e9e4 nvethernetrm: Enable macsec debug feature 
Validate input parameters and handle debug buffer interrupts

Bug 3265346

Change-Id: I8a7ebf66d20867fe4fb890d7d09d044d15108a17
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2496672
Tested-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2021-06-21 07:07:10 +05:30
Mahesh Patil
5d26aedc95 nvethernetrm: Use correct sc start_idx in delete 
Use correct sc start_idx when deleting SC/AN

Bug 3206033

Change-Id: I38fc92c743e905d04a5cdc671b5cb59f55ba7c97
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
 2021-06-21 07:07:10 +05:30
Mahesh Patil
f6fe93c7e5 nvethernetrm: Update mmc counter properly 
Don't add accumulated previous counter value when
counter is updated with latest value. Register value
itself is accumulated counter.

Bug 200688810

Change-Id: I93c971724557813a317cc118ce1b4459b9772d83
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
 2021-06-21 07:07:10 +05:30
Srinivas Ramachandran
3be3b7a90c nvethernetrm: Add support for MACsec controller 
This commit adds support for MACsec controller HW
operations. The MACsec HW ops can be accessed via
osi_core layer.

Currently, MACsec HW is enabled when MAC interface
is brough up, with no LUT entry so that packets
will still be bypassed. MTU check is enabled and
default interrupts are enabled for statistics.

Bug 2913560

Change-Id: I62e8567fac6603db47f4069a40458038f9b4178a
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
 2021-06-21 07:07:10 +05:30