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3fff0cd9baffb3b2f8a7c08ba7e4041a8b25b51d
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74 Commits

Author SHA1 Message Date
Narayan Reddy
3fff0cd9ba osi: core: fix Doxygen warnings 
1) Fix Doxygen warnings
2) include debug.h code only when OSI_DEBUG
is defined

JIRA NET-570

Change-Id: I5d002b959925bec3898cc2faafe3f506b3c9bd22
Signed-off-by: Narayan Reddy<narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2847327
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-02-04 16:49:50 -08:00
Narayan Reddy
2a82c10c8f osi: core: mgbe: Fix 9K Jumbo issue 
Issue: Not able to transfer 9K Jumbo frame.
Currently each TxQ is divided into 12KB of size
which leads to not making use of 8KB in total which
is affecting 9K Jumbo

Fix: Instead of using 12KB per TxQ, 128KB is equally
divided among 10 Tx Ques.

Bug 3934258

Change-Id: I86623e2726789d42a683aa755f47d77e04391dc1
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2848255
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2023-01-27 20:03:06 -08:00
Mohan Thadikamalla
a114ece241 osi: core: mgbe: Enable HSI for TXESIE interrupt 
Issue:
Need HSI support for TXESIE interrupt

Fix:
Handle TXESIE interrupt for safety builds
and update HSI CE counters

Bug 3846917

Change-Id: Ie431f4b166d8adb524fba74e0da80570aa162bf1
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2827634
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-12-16 03:34:06 -08:00
Hareesh Kesireddy
3be2a1e7f3 osi: l3l4: support four tuple for l3l4 fitlers 
Following implemented for non safety.
- Moved l3l4 filter index assignment to OSI for better management.
  OSDs need not worry about managing l3l4 filter indexes.
- Restructured code to support four tuple for osi l3 l4 filter.
- Added a wildcard l3l4 filter at highest filter index to allow the
  the packets to receive on default dma channel (from l2 filter) for the
  packets which do not match with any of the configured l3 l4 filters.
- For IPv4, allowed user to configure all SA+DA+SP+DP together at a
  single l3l4 filter index or user can selectively add any
  combination among them (e.g, only SA or SP+DA, etc.).
- For IPV6, only restriction is to add either of the SA or DA only
  but not both at a time at a single l3l4 index.

Bug 3576506
Bug 3825731

Change-Id: I20bd197f5bf793a77f5e723d1875875d442af66e
Signed-off-by: Hareesh Kesireddy <hkesireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2802626
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-11-30 06:16:47 -08:00
Mohan Thadikamalla
20f52bb866 osi: core: Disable TXESIE for safety 
Issue:
Observed common intrrupt on
safety builds as TXESIE is not
served.

Fix:
Disable TXESIE intrrupt for
safety builds

Bug 3846917

Change-Id: I8f01d382eb2979439f7a82fce346c66f1133061f
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2814604
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-11-24 18:16:09 -08:00
Narayan Reddy
67ffdc1d3c osi: core: merge ioctl calls to osi_core_init 
By default enable below settings during core init,
so that we can avoid the same by calling from Guest OS

1) bring mac out of reset
2) forward error packets
3) set mode to full duplex
4) enable rx csum
5) Configure PTP
6) start mac

Bug 3701869

Change-Id: I26578b7a0b8c91c4880d9ef6a3a171ab1c1945aa
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2809705
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-11-23 08:06:55 -08:00
Bhadram Varka
2fb7d1d324 osi: eqos: configure MTL RXFIFO and PFC threshold 
MTL RXFIFO memory available for EQOS - 64KB
Below is the distribution -
1) Q0 - 36KB
2) Q1 to Q6 - 2KB
3) Q8 - 16KB

It also update flow control parameters for
the Rx queues
1) Q0 - FULL_MINUS_16K
2) Q1 to Q7 - FULL_MINUS_1_5K

Bug 3787316

Change-Id: I59031ad03f02d5804fcc65cb24e05559e6358500
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2789263
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-11-14 20:55:16 -08:00
Om Prakash Singh
70bf517f34 osi: core: add support for HSI error injection 
Add new osi ioctl command OSI_CMD_HSI_INJECT_ERR for
IP specific error injection configuration.
different type of error is injected based on input
error code value.

Bug 3806923
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Change-Id: I01269d211293aa67471fadcf6e349f049f9c1a51
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2786840
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-11-09 11:18:59 -08:00
Om Prakash Singh
aaf12511a3 osi: core: enable HSI_SUPPORT and fix MISRA issue 
enable HSI_SUPPORT at OSI unit level and address
misra issues.

Bug 3590939
Change-Id: Ia87bafe077553d0140219047a578100c3f5684aa
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2784224
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-11-09 11:18:49 -08:00
Narayan Reddy
4c85b5e49e osi: core: Fix MISRA issues 
===== DIFF ======
Total misra violation count changed by -71
Rule: MISRA_C-2012_Directive_4.5 Diff: -3
Rule: MISRA_C-2012_Rule_11.1 Diff: -5
Rule: MISRA_C-2012_Rule_11.3 Diff: -1
Rule: MISRA_C-2012_Rule_11.5 Diff: 1
Rule: MISRA_C-2012_Rule_12.1 Diff: -6
Rule: MISRA_C-2012_Rule_12.2 Diff: -7
Rule: MISRA_C-2012_Rule_15.1 Diff: -1
Rule: MISRA_C-2012_Rule_15.6 Diff: -1
Rule: MISRA_C-2012_Rule_16.1 Diff: -1
Rule: MISRA_C-2012_Rule_16.3 Diff: -1
Rule: MISRA_C-2012_Rule_17.7 Diff: -4
Rule: MISRA_C-2012_Rule_17.8 Diff: -5
Rule: MISRA_C-2012_Rule_2.4 Diff: -4
Rule: MISRA_C-2012_Rule_2.5 Diff: -18
Rule: MISRA_C-2012_Rule_20.5 Diff: -1
Rule: MISRA_C-2012_Rule_5.6 Diff: -1
Rule: MISRA_C-2012_Rule_5.8 Diff: -1
Rule: MISRA_C-2012_Rule_5.9 Diff: -4
Rule: MISRA_C-2012_Rule_8.3 Diff: -2
Rule: MISRA_C-2012_Rule_8.9 Diff: -5
Rule: MISRA_C-2012_Rule_9.5 Diff: -1
Rule: Total Diff: -71

Bug 3695218

Change-Id: I9bd904f8a77195ca34fb2d47639a214f0083ccf7
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2776281
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-09-29 19:38:37 -07:00
Bhadram Varka
5fba408c31 osi: mgbe: configure MTL RXFIFO and flow control 
MTL RXFIFO memory available for MGBE - 192KB
Below is the distribution -
1) Q0 - 160KB
2) Q1 to Q8 - 2KB
3) Q9 - 16KB

It also update flow control parameters for
the Rx queues
1) Q0 - FULL_MINUS_32K
2) Q1 to Q9 - FULL_MINUS_1_5K

Bug 3787316

Change-Id: I3049d742e784aa3273090191856482121a3e1d3e
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2779472
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-09-28 12:47:58 -07:00
Rakesh Goyal
6b4ddb8043 nvethernetrm: take exported ioctl related header out 
Issue: SW needs to support IOCTL on safety builds and
these header should be exposed to user

Fix: Create new header file which is exposed externally
     Fix Coverity issues
     Enable TSN and FRP for safety build
     Optimize the code between eqos and mgbe

Bug 3704251

Change-Id: I2807f8283a296de1f96d3f902cb4ad5a4781be50
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2759333
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
 2022-09-12 20:52:00 -07:00
Narayan Reddy
e03254a23d osi: core: combine config_l3_l4_filter_enable 
Bug 3701869

Change-Id: Ic36cb61075495589c9aaf9bafb7ce1eeda4de673
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2740674
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-09-08 21:02:01 -07:00
Narayan Reddy
d3bd103871 osi: core: combine config_mac_pkt_filter_reg 
Bug 3701869

Change-Id: I603bd57511f115fb5af42dca2a5804cf4926ebbb
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2740658
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-09-08 21:01:51 -07:00
Narayan Reddy
28053a560e osi: core: fix misra 2.x rules 
===== DIFF ======
Total misra violation count changed by -591
Rule: MISRA_C-2012_Rule_2.2 Diff: -1
Rule: MISRA_C-2012_Rule_2.3 Diff: -3
Rule: MISRA_C-2012_Rule_2.4 Diff: -2
Rule: MISRA_C-2012_Rule_2.5 Diff: -585
Rule: Total Diff: -591

Bug 3695218

Change-Id: I57e85ba94f434cb3bd729b4f5f75bb4a592fb279
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2768383
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-09-02 04:58:41 -07:00
Narayan Reddy
f816ebf1e8 osi: core: fix misra 4.6 rule 
===== DIFF ======
Total misra violation count changed by -240
Rule: MISRA_C-2012_Directive_4.6 Diff: -240
Rule: Total Diff: -240

Bug 3695218

Change-Id: Ida2d3a775872637eda3058ea361a00346c86f7f7
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2767895
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-08-30 00:05:29 -07:00
Rakesh Goyal
d31916e761 core: configure ETS as default selection algorithm 
Issue: Default TX selection is SP, due to which
highest TX queue get most of TX bandwidth.

Fix: Set ETS as selection policy (WRR)with equal
weights given to all Tx Queue.
 Set default configuration on disabling CBS.

Bug 3735907

Change-Id: I33b849695641ceaeef77ff819121d51e132214aa
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2749330
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-08-29 05:12:48 -07:00
Narayan Reddy
02e8ac20c5 osi: core: combine ptp_tsc_capture 
Bug 3701869

Change-Id: Ib8b2ea895866e2d260aa5e5aa753ecfd49b663ae
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2740494
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-08-25 19:06:59 -07:00
Narayan Reddy
cc6c76912d osi: core: combine config_ssir 
1) Combine config_ssir
2) Store MAC version in local core/dma variable for differentiating across SoCs.

Bug 3701869

Change-Id: I43dd9f7d2194191d849ea10f15b84b2c40111ee0
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2740328
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-08-25 19:06:47 -07:00
Narayan Reddy
f20eda41e2 osi: core: combine config_tscr 
Bug 3701869

Change-Id: I1eb04dd9cf439ce55b1bdc6df73f793af85eddcd
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2740317
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-08-25 19:06:41 -07:00
Narayan Reddy
cc9c350697 osi: core: combine config_addend 
Bug 3701869

Change-Id: I6a656ac72e8d87b96ac9efa9bf9e1c9a979306b1
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2740109
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-08-25 19:06:34 -07:00
Narayan Reddy
3b34cf8978 osi: core: combine set_systime_to_mac 
Bug 3701869

Change-Id: I7df8c486b9fea489bf16c700d93e070f0d455dd2
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2740056
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-08-25 19:06:27 -07:00
Narayan Reddy
3bf72bdd4a mgbe: core: call lane bringup on local fault 
call lane bringup when there are local faults
and stop the network queues.
restart the network queues when proper link is up

Bug 3744088
Bug 3654543
Bug 3665378

Change-Id: I33180c965b29543dcdfb0d8f611be06b6b97a42e
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2730882
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-08-17 10:38:17 -07:00
Narayan Reddy
be51977e02 osi: core: combine config_fw_err_pkts 
Bug 3701869

Change-Id: I5a0fe6e24d8aa69054a18f927d7135552482e8b9
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2739131
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-07-13 16:28:15 -07:00
Narayan Reddy
46f06fed42 osi: core: combine flush_mtl_tx_queue 
Bug 3701869

Change-Id: Ifea025c0eb2d4373a348283aaa93eb7d0eca193a
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2739121
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-07-13 16:28:04 -07:00
Bhadram Varka
dea34fa933 osi: core: common poll_for_swr 
Combine MGBE/EQOS HW level functions into single function.

Bug 3701869

Change-Id: I02c4881ec95cc5637867d68e560f4790c3548737
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2732106
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-07-13 16:27:31 -07:00
Narayan Reddy
21b6f6aeb9 osi: core: Fix MISRA issues 
Fixed straight forward MISRA issues

===== DIFF ======
Total misra violation count changed by -319
Rule: MISRA_C-2012_Directive_4.4 Diff: -3
Rule: MISRA_C-2012_Directive_4.6 Diff: -32
Rule: MISRA_C-2012_Directive_4.9 Diff: 3
Rule: MISRA_C-2012_Rule_10.1 Diff: -4
Rule: MISRA_C-2012_Rule_10.3 Diff: -2
Rule: MISRA_C-2012_Rule_10.4 Diff: -21
Rule: MISRA_C-2012_Rule_11.1 Diff: -20
Rule: MISRA_C-2012_Rule_12.1 Diff: -74
Rule: MISRA_C-2012_Rule_15.5 Diff: 1
Rule: MISRA_C-2012_Rule_15.7 Diff: -2
Rule: MISRA_C-2012_Rule_16.1 Diff: -1
Rule: MISRA_C-2012_Rule_16.3 Diff: -1
Rule: MISRA_C-2012_Rule_17.7 Diff: -5
Rule: MISRA_C-2012_Rule_2.5 Diff: -157
Rule: MISRA_C-2012_Rule_8.6 Diff: -1
Rule: Total Diff: -319

JIRA NET-96
Bug 3695218

Change-Id: I221f95aaf23e9214fde21632b68425b705552752
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2735077
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-07-06 02:37:19 -07:00
Om Prakash Singh
6bdbdb32c6 osi: dma/core: add interface to configure debug interrupt 
add interface to configure debug related interrupt

Bug 3600647
Change-Id: Iae43ceb441254b89a5b32ef9441ce42fca812e49
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2703337
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-05-16 17:41:38 -07:00
Om Prakash Singh
65f78eba09 osi: core: add support for HSI 
1) Add OSI IOCTL to enable HSI feature at runtime
2) Enable LIC interrupt for Correctable, Uncorrectable and
   Parity error
3) Program register to enable safety feature

Bug 3543410

Change-Id: I8a9f33bab72eb37e8aa64c16c610be6e5271c7f8
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2670989
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-09 16:26:37 -07:00
Bhadram Varka
9d2e1695f6 osi: mgbe: fix MGBE channels mask 
Bug 3420115

Change-Id: If086f090082bda7972d01776543f24c8cf9b060f
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2680952
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-03-14 17:14:22 -07:00
Rakesh Goyal
288c525a36 nvethenetrm: core: SW WAR implementation for switching of Gates 
Issue: switching of Gates did not happen for
intermediate cycles when CTR is
less than GCL execution time

Fix: SW WAR as per recommendation.
1) At the programming time make sure
  (CTR - total TI) should be 0 or more than
  8PTP clock time.
2) Switching to New List
   check for following
   Old BTR + n(CTR) - New GCL list's BTR >= 8PTP or
   New GCL list's BTR – (Old BTR + n(CTR)) >= 8PTP

Bug 200724911

Change-Id: I19127a134655a66bb66d025f964b85afc6c23c2e
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2622942
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-02-28 10:49:29 -08:00
Narayan Reddy
97d5787a79 mgbe: modify AXI clock to 480MHz 
480MHz APP clock needs to be used for 10G speed as per IAS.
Change the clock source to reflect the same.

Bug 200778229

Change-Id: Idf60c4a090ed82b0a1be58d5b45b3a557c59fdfc
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2660870
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-02-10 14:05:50 -08:00
Rakesh Goyal
2246e3a2a5 core: add support configure pps out signal 
Issue: Default pps output is 1 pulse (of width
clk_ptp_i) every second.

Fix: option to configure to binary rollover is 2 Hz,
and the digital rollover is 1 Hz.

Bug 3462227

Change-Id: Ic777bfaf51a72ec91c8f165910e824c55cae3057
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2641896
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-01-11 20:06:08 -08:00
Mohan Thadikamalla
c2b4bf8204 mgbe: Fix FRP DMA route issue 
Issue:
FRP MC/BC packets routing to
multiple DMA channels is not happening.

Fix:
Correct the FRP entry DCH programming to
enable multiple DMA channels route.

Bug 3417901

Change-Id: Ib3d5794253b89d7d3a00164fa7fd011e4ac9e50b
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2629966
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-12-14 02:45:56 -08:00
Sanath Kumar Gampa
6108b6e8a1 nvethernetrm:Disabled DIC as part of mgbe init 
Issue:seeing 0 Throughput after MACSEC is enabled

Fix: Disable DIC to fix 0 Tput issue

Bug 200770840

Change-Id: I8cceee8fd8509ec484bfbb6063ca4dd8be091fa5
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2606457
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-10-14 12:03:15 -07:00
Sanath Kumar Gampa
2a3bdce7c8 nvethernetrm: MTL_EST CTOV config for MACSEC 
Issue: h/w requirement to change the MTL_EST value
depending on MACSEC

Fix: Change the value in MACSEC enable/disable flow

Bug 200630202

Change-Id: Iefdb14e44841941ab3e8f8c116746b0db6c63ba5
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2604830
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-10-14 12:02:52 -07:00
Rakesh Goyal
e6a2dd50b4 osi: core: Set QHLBF bit 
As per HW fix, program QHLBF to 1 to get
HLBF error in 1-2 cycle of GCL.

Bug 200778825
Bug 200649072
case: 01085007

Change-Id: I18cfa6ad4eda56e2684abd86b7dc02c7a143c0ef
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2601421
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-10-07 17:51:50 -07:00
Narayan Reddy
b9be4579b7 osi: core: Enable Transparent Tx LPI Mode 
In this mode, the transmit LPI state-machine
does not move to TX_QUIET state. On detecting Lower-Power Idle
on XGMII/GMII Tx interface, xpcs goes to the TX_SLEEP state and
remains in this state till MAC stops sending LPI.

Bug 200764486

Change-Id: I376ac481e880472d7a11b60931a90d6f9c7a0067
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2598380
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-24 12:31:56 -07:00
Rakesh Goyal
972305578c core: add CMD_PTP_TSC_CAP to capture time 
issue: Requirement is to have a method by which
       TSC-PTP-CAPTURE can be initiated.

fix: Having osi_core ioctl to trigger and capture
     TSC-PTP timestamp using HW logic.
     Caller need to call osi_handle_ioctl with
     command as OSI_CMD_CAP_TSC_PTP,
     osi_core pointer and osi_core_ptp_tsc_data
     structure.

Bug 200736396

Change-Id: I511dc4f490fdef81655a62c18268764741855fe4
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2554284
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-22 15:39:49 -07:00
Bhadram Varka
a0c20c02f6 osi: mgbe: add handling of tx errors 
handle Tx buffer underflow
handle Tx jabber timeout
handle Tx IP header error
handle Tx Payload checksum error

Bug 200565898

Change-Id: I2de4cd11580251f0387039c1f8f3c39792c1ab65
Signed-off-by: narayanr <narayanr@nvidia.com>
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2596092
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-21 13:40:58 -07:00
Rakesh Goyal
2200f3d921 core: update code for TSN 
- Update CTOV recommended value
- Update PTOV recommended value
- Disable PEC filed on preemption disable
- Disable EEST with message to reprogram
  GCL instead of dropping packet on HLBF/HLBS
- Configure code not to drop any packet silently
  on HLBF and HLBS error
- Q2TC mapping with CBS enable

Bug 200763256
Bug 200765943

Change-Id: I7a2581af488e22a23d32ce1819440c21f4748800
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2593162
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-20 11:10:24 -07:00
Bhadram Varka
0372ac4f94 osi: eqos: mgbe: program SID through HV window 
Issue: In non-hypervisor configurations SID programmed
through RM window. In orin EQOS/MGBE these SID should
program through HV window to get reflected in controller
register space.

Fix: Program SID based on MAC instance ID through HV window

Bug 200761024

Change-Id: I1a37455647429e917e7558e812fe7e512d646918
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2592482
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-09-15 09:18:17 -07:00
Mahesh Patil
3af55e0c58 nvethernetrm: change MAC ipg as per macsec req 
Change MAC ipg value as macsec IAS requirement when
macsec is used

Bug 3335658

Change-Id: Ie681bb0a66b256c32ac6093114fe29c65bf20a07
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2558031
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-10 02:10:19 -07:00
Bhadram Varka
7b29b58c95 Revert "osi: eqos: mgbe: program SID through HV window" 
This reverts commit b16c09af3b.

Reason for revert: Created regression for AV + L

Bug 3358505
Bug 200761024

Change-Id: I31fbd921f9655cd62073918be9d4151f5cc29f8b
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2584378
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2021-08-28 02:46:52 -07:00
Bhadram Varka
b16c09af3b osi: eqos: mgbe: program SID through HV window 
Issue: In non-hypervisor configurations SID programmed
through RM window. In orin EQOS/MGBE these SID should
program through HV window to get reflected in controller
register space.

Fix: Program SID through HV window

Bug 3358505
Bug 200761024

Change-Id: I1db99c85e875aeaf6c692011a0d2fbe16277d288
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2582062
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-08-25 09:07:33 -07:00
rakesh goyal
1a2c9a3d94 osi: common: Add support for MGBE 2 step timestamp 
- OSI DMA
-- During Trasnmit:
--- For EQOS/MGBE one steps PTP Reads TS and update
    in TX done structure.

--- For MGBE 2 steps PTP or 1 step slave, update flags
    TS_POLL and update pkt_id as unique ID to be used
    for polling by OSD after Common interrupt handling.
    packet_id = MSB 4 bits channel_number and LSB 6-bits,
    local index of PTP TS FIFO.

-- On transmit complete
--- If TS is part of Tx done context set OSI_TXDONE_CX_TS
--- If TS is not part of Tx done context and delayed set
OSI_TXDONE_CX_TS_DELAY.

- OSI Core
-- On Common interrupt:
--- If MGBE_ISR_TSIS is set, read time stamp to internal
    array from HW fifo, until it is completely read or array
    is full.
--- Provide an IOCTL OSI_CMD_GET_TX_TS, to read TS for the
    specified pkt_id from OSD via structure osi_core_tx_ts
--- Provide an IOCTL OSI_CMD_FREE_TS, to free TS for the
    specified pkt_id from OSD path

Bug 200603265

Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Change-Id: Ib3e02031393e40988074095e5a135bb4e839d7f4
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2543792
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-06-29 10:36:51 -07:00
Nagarjuna Kristam
81f1a71214 osi: common: Move VM IRQ configuration core to dma 
Issue:
VM IRQ configuration needs is done using DMA base, instead of RM
base.

Fix:
Add VM IRQ configuration code to osi core init sequence.
Remove the same code in DMA.

Bug 200718904
Bug 200730767

Change-Id: I5bf41c85d745a977875ed2eeb044b4db088e0b64
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2539623
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
 2021-06-21 07:07:10 +05:30
Mahesh Patil
d3fd593f50 nvethernetrm: Update mac/macsec init 
Update mac/macsec init programming
1. macsec clock and reset programming order at init and deinit
2. macsec SOT values as per macsec IAS
3. mac IPG values as per macsec IAS

Bug 3266535

Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Change-Id: Ie6351f632b0ac7487ec7b5bfd34d9337d3782a59
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2506488
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-06-21 07:07:10 +05:30
rakesh goyal
b877989eab osi: mgbe: add support for PMCBCQ and OVHD 
Issue:	MCBC queue for preemptable packet is default Queue
	0 and update Overhead Bytes Value default value is
	not sufficient as per HW update.

Fix:	MCBCQ for preemptable packet should be different
	from express packet Q. Using residual Queue for
	same.
	Add OVHD for MGBE as per programming information
	from HW team.

Bug 200561100
Bug 200630202

Change-Id: Ib37e37c4d229b62589e76b1879538cd66707024c
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
 2021-06-21 07:07:10 +05:30
Mohan Thadikamalla
96d41b190e nvethernetrm: mgbe: Add XDCS support 
Enable multiple DMA Channels routing support
for MC/BC MAC Address with XDCS.

Bug 200565911

Change-Id: I7c9f9347361dd72e68696846a0a59e2e241e20c9
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
 2021-06-21 07:07:10 +05:30