Issue:
Data packets sent via EQOS hardware are not
following any packet gaping. The AVB use-cases
have different timing requirements for class A
data packets. For example, the time difference
between two class A data packets are supposed
to be 125 microseconds for audio data of
frequency 48 kHz.
Fix:
Add slot function support to schedule
the data fetching from the system memory
by the DMA. This will help the AVB SW stack
timing requirements for class A data.
Bug 200545374
Change-Id: Id7c606f7491a423051667811bd6d459ee58f6700
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2222282
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
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Issue: APIs like osi_clear_tx/rx_intr, osi_update_rx_tailptr
are redundant. The operations that are done in these
functions can be included as part of other existing
OSD-OSI interface API. OSD need not micro-manage the
hardware controller by using such fine grain APIs.
Fix: Remove the redundant APIs and implement their functionality
as part of existing APIs.
Bug 2715391
Change-Id: I47851c204988475cac1cadf6fe678d7d446a3cc3
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2211093
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
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issue: Currently when TSA is set in normal descriptor, SW will poll for
OWN bit in context descriptor to fetch the time stamp. In long run
scenario OWN bit is not reset in context descriptor even though the
driver polls for 10 iterations. After maximum iterations driver returns
timeout and hence only PTP data which is there normal descriptor will be
delivered to NW stack without timestamp and hence the application
results in throwing "received a PTP packet without timestamp" message.
fix: add a 1usec delay between the iterations so that hardware can get
enough time to reset the OWN bit of context descriptor.
Bug 200560728
Change-Id: I6b94ebc4ac0e52c6887999b7183ac60dda2cc005
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2225571
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
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Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
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Issue: For every normal descriptor which has RS1V (RDES1 valid)
set current code will go and check for timestamp in next descriptor.
Fix: Check rx timestamp status in context descriptor if normal
descriptor have RS1V (RDES1 valid) and TSA (Timestamp available)
bits are set and TD (timestamp dropped) is reset.
Bug 200443762
Change-Id: If910c462f7c306facba95ec37f860395fb3bacd4
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2220139
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Issue: Ethernet transmit routine called with a Tx packet then
OSI layer invoked with osi_hw_transmit() routine to update
the descriptor with packet details. As part of this process
Tx ring cur_tx_idx not updated actual entry before updating
Tx ring tail pointer.
Programming Tx ring tail pointer will initiate the transmission.
Here transmit routine got preempted because of Tx done interrupt.
As part of ISR Tx NAPI got scheduled - osi_process_tx_completions.
In Tx completions cur_tx_idx used for processing of the transmit
completion ring. Since cur_tx_idx has some old value its not
entering into the loop for packets processing.
Actually entered into loop for next Tx interrupt and processed
the Tx ring. This leads to tx timeout in handling of timestamped
packets from the application point of view.
Fix: Update Tx ring current tx index before updating Tx ring
tail pointer.
Bug 200443762
Change-Id: I27e07b17c0c8a8c32913236a3aaa97803c50b2a9
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2219894
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
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Issue: eqos_poll_for_swr() function sleep for one millisecond
and then read DMA Basic Mode register to check on SWR bit
for reset or set. Because of this there would be atleast
one millisecond delay.
Fix: One millisecond sleep only if SWR bit not reset
in DMA Basic Mode register.
Bug 2715328
Change-Id: I690df18190f4ad2f4630b5aeddd35c07c161fd25
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214195
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Receive timestamp for a received packet will be in context descriptor
which is immediate of normal descriptor (has valid packet data)
In current case nvethernet driver only unmap normal descriptor buffer
address and provide the buffer to the network stack for data processing.
Context descriptor buffer is not unmapped which leads to running out of
IOVA space for the new buffers.
Context descriptor buffer can be used as is since that is not provided
to the network stack. So this change to a flag for context descriptor.
Based on this flag OSD can skip new buffer allocation and mapping for
the context descriptor and use already allocated buffer.
Bug 2700522
Change-Id: I18c8ebe39bf2eaaaeb13a9de3c9595cbe2ada45d
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2214726
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Issue: Current sw allows only non-zero VLAN tag to be added
in register.
Fix:
1) Allow adding VLAN id 0 in VLAN tag register. By this all
VLAN tag packets are allowed even filter enable.
2) Don't update VLAN ID to VLAN TR register for eqos so it
set to default 0x0.
Bug 200544722
Change-Id: Icbc89a8318cc2acd5a346da802244c213dcc15e6
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2180240
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Issue: Pad calibration failed when the OSI API function
osi_pad_calibrate is invoked, but works when pad calibration
is triggered internally in osi_hw_core_init. Issue is the
OSI API passes incorrect argument for base address.
Fix: Provide the correct base address in OSI interface API.
Bug 200512422
Change-Id: I625f3269452e31e89fef07f960c80a2fd2024634
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2163995
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With this feature filtered Rx packet will be redirect to
corresponding DMA channel based on register configuration.
Function driver code need to pass 2 extra parameters enable/disable
and dma channel number within the valid range to utilize this
functionality.
For L2 filtering, function driver code can also pass address mask
and src_dest for filter index 1-31.
Bug 200525721
Change-Id: Ibf3fb93cdd4c3b7c0384a0e36e7bbe467bb41e04
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2133197
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
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These stats are read from MAC HW RMON counters as well as from Core
and DMA path.
ethtool -S <interface> is used to get statistics.
There are 3 stats captured currently
1) ether_mmc_counters: EQOS HW RMON counters
2) ether_xtra_stat_counters: SW counters from osi/core
3) ether_xtra_dma_stat_counters: SW counters from osi/dma
Bug 200519211
Change-Id: I5bbeb340cf2ffccb6399687b254f79c67f480179
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2114208
GVS: Gerrit_Virtual_Submit
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
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1. ARP offload can be configured private ioctl.
The IP address to be configured for ARP offload
needs to be provided by application as unsigned
char array. Refer to struct ether_ifr_data and
struct arp_offload_param for details.
2. Tx/Rx checksum offload. Enabled by default (can
be toggled using ethtool)
3. TCP Segmentation offload. Enabled by default (can
be toggled using ethtool)
Bug 2571001
Change-Id: Ifcf2982557e80655e3cd7ebf3c70f49c538133b5
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2109677
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
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