Commit Graph

29 Commits

Author SHA1 Message Date
Om Prakash Singh
f661fdd189 core: add pcs register readback after write support
As per T23X-MGBE_HSIv2-14 requirement for PCS register
we need to perform readback for each write operation
to verify write operation was successful

Bug 3606649
Change-Id: I7cca6baa43feaa4207b6158f0abc796e656338dd
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2700845
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2022-05-04 23:24:27 -07:00
Nagaraj Annaiah
221989d875 osi core: Fix compiler warnings for HVRTOS
Issue: Unused variables are treated as errors with HVRTOS compiler.

Fix:
1. Add unused attributes macro for unused function arguments.
2. Fix typecast errors.
3. Add flag to check if ethernet server status, this is needed to
   skip check for function pointer validation.

Bug 3562777

Change-Id: I0a4a36fb330c580d1879f46304842c610e62316c
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2670097
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-04-21 15:52:01 -07:00
Om Prakash Singh
65f78eba09 osi: core: add support for HSI
1) Add OSI IOCTL to enable HSI feature at runtime
2) Enable LIC interrupt for Correctable, Uncorrectable and
   Parity error
3) Program register to enable safety feature

Bug 3543410

Change-Id: I8a9f33bab72eb37e8aa64c16c610be6e5271c7f8
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2670989
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-04-09 16:26:37 -07:00
Rakesh Goyal
288c525a36 nvethenetrm: core: SW WAR implementation for switching of Gates
Issue: switching of Gates did not happen for
intermediate cycles when CTR is
less than GCL execution time

Fix: SW WAR as per recommendation.
1) At the programming time make sure
  (CTR - total TI) should be 0 or more than
  8PTP clock time.
2) Switching to New List
   check for following
   Old BTR + n(CTR) - New GCL list's BTR >= 8PTP or
   New GCL list's BTR – (Old BTR + n(CTR)) >= 8PTP

Bug 200724911

Change-Id: I19127a134655a66bb66d025f964b85afc6c23c2e
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2622942
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2022-02-28 10:49:29 -08:00
Sanath Kumar Gampa
65a9cb659e macsec: get next PN and IRQ stats cmd with server
Some of the commands such as get next PN and irq stats
are not working if thernet server is enabled, fixed the same.
And also moved HKEY generation to OSD, to avoid dependency on
Crypto libs on LK. devmemr/w can read/write to macsec addresses

Bug 3522740

Change-Id: Id3b328cfd83aa976ef5bde8adc057588bb6fed38
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2652212
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-02-27 18:07:30 -08:00
Rakesh Goyal
2246e3a2a5 core: add support configure pps out signal
Issue: Default pps output is 1 pulse (of width
clk_ptp_i) every second.

Fix: option to configure to binary rollover is 2 Hz,
and the digital rollover is 1 Hz.

Bug 3462227

Change-Id: Ic777bfaf51a72ec91c8f165910e824c55cae3057
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2641896
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2022-01-11 20:06:08 -08:00
Rakesh Goyal
61be2488de nvethernetrm: MAC to MAC time sync
- Add code to store role of FD
- Function to return osi_core pointer for
  first role match.
- add code to calculate time offset between
  Primary and Secondary PTP controller HW time.
- calculate frequency adjustment calculation.
- call appropriate HAL function for
  secondary interface.

Bug 200733666

Change-Id: I7a141ea691d80d9f69fd18b28ae0964cb1bf2fb3
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2614283
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-11-02 04:07:33 -07:00
Sanath Kumar Gampa
2a3bdce7c8 nvethernetrm: MTL_EST CTOV config for MACSEC
Issue: h/w requirement to change the MTL_EST value
depending on MACSEC

Fix: Change the value in MACSEC enable/disable flow

Bug 200630202

Change-Id: Iefdb14e44841941ab3e8f8c116746b0db6c63ba5
Signed-off-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2604830
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-10-14 12:02:52 -07:00
Nagaraj Annaiah
5df5eefe5a osi: core & dma : Increase osi and dma instances
- Increase OSI and DMA instances to 10 to support
  multiple VF's.
- Copy PTP config to ioctl structure.

Bug 2694285

Change-Id: I558b161c64a5467dc9e7260e58801eb6b1735d50
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2605781
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-10-07 22:39:51 -07:00
Rakesh Goyal
972305578c core: add CMD_PTP_TSC_CAP to capture time
issue: Requirement is to have a method by which
       TSC-PTP-CAPTURE can be initiated.

fix: Having osi_core ioctl to trigger and capture
     TSC-PTP timestamp using HW logic.
     Caller need to call osi_handle_ioctl with
     command as OSI_CMD_CAP_TSC_PTP,
     osi_core pointer and osi_core_ptp_tsc_data
     structure.

Bug 200736396

Change-Id: I511dc4f490fdef81655a62c18268764741855fe4
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2554284
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-09-22 15:39:49 -07:00
Rakesh Goyal
a9b03b83a9 core: mgbe: use lock for time stamping
Using lock for protect critical section between
common interrupt and ioctl call to read
timestamp

Add mmc counters for lock failure during node
addition and deletion.

Bug 200743666

Change-Id: I12a2e57993e91d6ed50ed0efc84d1b60ef736677
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2590099
Tested-by: Gaurav Asati <gasati@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Gaurav Asati <gasati@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-09-20 11:09:19 -07:00
Mahesh Patil
3af55e0c58 nvethernetrm: change MAC ipg as per macsec req
Change MAC ipg value as macsec IAS requirement when
macsec is used

Bug 3335658

Change-Id: Ie681bb0a66b256c32ac6093114fe29c65bf20a07
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2558031
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-09-10 02:10:19 -07:00
Rakesh Goyal
993cd8cf81 nvethrnetrm: add debug prints and validation function
issue: 1) Missing code related to GCL validation in MGBE
       2) Missing debug prints

Fix:   Fix above issues
       1) Add call for validate GCL entries for MGBE
       2) Add debug prints for all errors before return

Bug 200622871

Change-Id: I060597fec2de1cb17b80c0c14f257401d3ff8d31
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2557029
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-07-15 17:17:13 -07:00
Bhadram Varka
d4e6ad6ec6 osi: use max_chans based on MAC version
Issue: Maximum number of DMA channels is different for
Xavier/Orin EQOS/MGBE IP's. Using macro of maximum number
of channels will create problem for other IP's.

Fix: Assign maximum number of DMA channels based on MAC version.

Bug 200741194

Change-Id: I321780b6868dfb36700863a5852b76424d3bbf6b
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2556425
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-07-13 09:22:21 -07:00
rakesh goyal
1a2c9a3d94 osi: common: Add support for MGBE 2 step timestamp
- OSI DMA
-- During Trasnmit:
--- For EQOS/MGBE one steps PTP Reads TS and update
    in TX done structure.

--- For MGBE 2 steps PTP or 1 step slave, update flags
    TS_POLL and update pkt_id as unique ID to be used
    for polling by OSD after Common interrupt handling.
    packet_id = MSB 4 bits channel_number and LSB 6-bits,
    local index of PTP TS FIFO.

-- On transmit complete
--- If TS is part of Tx done context set OSI_TXDONE_CX_TS
--- If TS is not part of Tx done context and delayed set
OSI_TXDONE_CX_TS_DELAY.

- OSI Core
-- On Common interrupt:
--- If MGBE_ISR_TSIS is set, read time stamp to internal
    array from HW fifo, until it is completely read or array
    is full.
--- Provide an IOCTL OSI_CMD_GET_TX_TS, to read TS for the
    specified pkt_id from OSD via structure osi_core_tx_ts
--- Provide an IOCTL OSI_CMD_FREE_TS, to free TS for the
    specified pkt_id from OSD path

Bug 200603265

Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Change-Id: Ib3e02031393e40988074095e5a135bb4e839d7f4
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2543792
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-06-29 10:36:51 -07:00
Rakesh Goyal
6cb30389f3 nvethernetrm: add interface operations for virtualization/non-virtualization
Issue:  In current implementation virualization
	callback are at HW ops level, which leads
        to multiple IVC calls.
Fix:	- IVC call happens only for core API's in case
	virtualization
	- For non-virtualization case HW operations will
	be invoked directly from OS OSD.
	- From Ethernet server OSD - OSI HAL API's
	should be called to access the HW operations

Bug 200671160

Change-Id: Ic3730fb822ae37fdf29fabf429f18f5d5bacd210
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2509243
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
2021-06-21 07:07:10 +05:30
nannaiah
6644553603 osi: Add virtualization fix.
- Change osi_readl to osi_readla
- Change osi_writel to osi_writela
- Add IVC macsec commands.
- Add OSI_MGBE_MAC_3_00 as valid list of version.
- Disable validate_func_ptrs as it returns failure.

Bug 2694285
JIRA T23XMGBE-118

Signed-off-by: Nagaraj annaiah <nannaiah@nvidia.com>
Change-Id: I49187c0decb3de4184b7ef5e3a2e553a60c1d54f
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2515254
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
2021-06-21 07:07:10 +05:30
Bhadram Varka
1d1a2d24d7 osi: add support for handling multiple IP's
Issue: Since core_ops/dma_chan_ops are static global
variables and these are stored in data segment of
a process. In linux when insmod happens eqos and mgbe
will get probe which inturn initialize osi core ops.
Since data segment is shared here eqos core ops pointer
overwritten by mgbe core operations.

Fix: Use separe core ops and local global variable
for each instance.

Bug 200671160

Change-Id: I7f093608d812e2ced1bf73339dbd70f0091fe5b4
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
2021-06-21 07:07:10 +05:30
mohant
88f37dcfd5 nvethernetrm: Add PTP offload support
Bug 200562286

Change-Id: I7adf08da12458c7291391ef726fe1fa65cb1bda1
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2319556
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
2021-06-21 07:07:10 +05:30
Mohan Thadikamalla
b3ff3bb215 nvethernetrm: Add Flexible Receive Parser support
- Define new data structure for the FRP table entry,
declare new frp_table and NVE variables in the OSI
core private structure.
- Define a new data structure for the OSI FRP command.
Add new OSI API to initiate FRP commands from OSD.

Bug 200565623

Change-Id: I84660a6e8270a681b82236d0c39423660b3821ff
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2330182
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
2021-04-05 16:35:54 +05:30
rakesh goyal
aa89068135 nvethernetrm: eqos: TSN support for EQOS IP
1. Adds basic OSI API's for EST/FPE
2. EST/FPE support for EQOS
3. MMC counters for FPE
4. EST errors and state counter

Bug 200561100

Change-Id: Iee3e6caac5d16e1620c25420d72700f9cdd00465
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2319820
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
2021-04-05 16:35:54 +05:30
Rakesh Goyal
36c1924486 nvethernetrm: mgbe: add PTP support
Change takes care of -
o Enable PTP for MGBE
o Added flags for One step/two step and also
for PTP master/slave
o Getting timestamp from MAC registers for MGBE.

Bug 200565914

Change-Id: I17346451f2619f0526a737a4a6bffdf130af4fc0
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2314201
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
2021-04-05 16:35:54 +05:30
vbhadram
c6a390123f nvethernetrm: mgbe: add support for RSS
This change programs 40byte Hash key and indirection table
(Hash table) (has DMA channel numbers) in MAC
Once packet received by MAC - 4-tuples will be extracted
from the packet and given to RSS hash engine. Hash function
will generate hash value by using 40byte key.
From hash value LSB bits used as index to RSS lookup table to
find out DMA channel number. If there is a match - packet is
routed to corresponding DMA channel. If there is no match -
packet will be dropped and error will be returned in receive desc.

Bug 200565647

Change-Id: Iffbb5a452f03278b3ba0bc061f09b43c7c994289
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2263398
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
2021-04-05 16:35:54 +05:30
Mohan Thadikamalla
164e29e693 nvethernetrm: Add RX Route support
- Add new ptp_rx_queue variable in
  osi_ptp_config structure.
- Declare an IP callback function
  for PTP RX queue index programming.
- Check and call IP based PTP RX queue
  callback in osi_ptp_configuration.

Bug 200596985

Change-Id: Ief040dc5b607ad729af5e9c0c1870249b456dcc7
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
2021-04-05 16:35:54 +05:30
Bhadram Varka
95f86be943 nvethernetrm: xpcs: XPCS initialization
Add support for XPCS initialization in USXMII mode
and start of XPCS will happen once speed set for MAC.

Bug 200552796

Change-Id: I4c98bec2e92d9b189c7d2404705e28b969592f33
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2258482
2021-04-05 16:35:53 +05:30
Bhadram Varka
731abcdc1e nvethernetrm: add support for MGBE initialization
Adds MAC CORE and DMA initialization support for
MGBE MAC Controller.

Bug 200548572

Change-Id: I6796229852b47ff0748a848a6dbe9addab6ab74f
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2250401
2021-04-05 16:35:53 +05:30
Bhadram Varka
3c12450bc7 osi: core: fix coverity/misra issues
Bug 200671160

Change-Id: I98f0bb2a4a0fde05b81551cd2dd0cab4ddac13dc
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
2021-04-05 16:35:53 +05:30
Bhadram Varka
696f45972b osi: don't expose core_ops to OSD
Issue: Currently OSD has access to osi_core_ops
so these operations can be changed by OSD.
Also each entry funnction has checks for validating
these function pointers which would increase the
unit tests and complexity as well.

Fix: Move dma_ops to inside OSI and set a flag
indicate that CORE software init done. Each entry
function needs to check only flag

Bug 200671160

Change-Id: I6def9e5c39f90a08eb4f48a124a1c2c8c65175a4
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2435991
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
2021-03-09 21:54:36 -08:00
rakesh goyal
93d87716de core: move get_hw_feat to osi_core
No api from osi_common should be direclty accessible
from OSD code. moving osi_get_hw_feat to osi core.

Moving following API to common/common.h
osi_memset()
osi_memcpy()

Bug 200671160

Change-Id: Idd6269b01ee8ec21c7f3c5b7f3376cf9a91bb661
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2488875
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
2021-03-05 19:35:28 -08:00