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fcbf3cf7e2b4ff3ce7cb50c7dab7d055f3e22a5d
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413 Commits

Author SHA1 Message Date
Bhadram Varka
fcbf3cf7e2 Revert "osi: eqos: mgbe: program SID through HV window" 
This reverts commit b16c09af3b.

Reason for revert: Created regression for AV + L

Bug 3358505
Bug 200761024

Change-Id: I31fbd921f9655cd62073918be9d4151f5cc29f8b
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2584378
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Bhadram Varka
5b45034d1c osi: eqos: mgbe: program SID through HV window 
Issue: In non-hypervisor configurations SID programmed
through RM window. In orin EQOS/MGBE these SID should
program through HV window to get reflected in controller
register space.

Fix: Program SID through HV window

Bug 3358505
Bug 200761024

Change-Id: I1db99c85e875aeaf6c692011a0d2fbe16277d288
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2582062
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Narayan Reddy
9d30f1630f eqos: set ssnic to 6 
Set SSIN to 6 for EQOS mac version 5.3

Bug 200760072

Change-Id: I72923d42313880dd362b7b6b197269f3495a18de
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2575178
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Bhadram Varka
7eb67cff3e osi: Add core debug for registers/structures 
- Adds core debugging for registers/structures.
- Add change to use single macro for CORE and DMA.

Bug 200737108

Change-Id: If96af2ef0c39e01b6c1dad74ee11fd820df76a8d
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2559319
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Bhadram Varka
6bf817d42b osi: Update MGBE MAC version 
On uFPGA MGBE MAC version is 0x31 and it got updated
to 0x40 on silicon.

Bug 200751806

Change-Id: Ic9d35b7a36cff158dd17feeddce6267a3ec2a082
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2559464
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Mahesh Patil
ee41c275a3 nvethernetrm: address review comments 
- Convert primitive data type to nv_ type's
- Replace debug pr_ prints with OSI_CORE_ print macro's
- Add all macsec register macro's with prefix MACSEC_
- Update all osi function header as per 5.2 coding guidelines(PLC)
- Remove printk.h header file and use OSI_CORE_ERR macro's in all prints
- Implement clean up LUT's in add_upd_sc() and del_upd_sc()

Bug 3264523

Change-Id: Ie41097c85fbcb90ce0c4cac470fe0f068ed22247
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2548476
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
a1ee9f8156 osi: use max_chans based on MAC version 
Issue: Maximum number of DMA channels is different for
Xavier/Orin EQOS/MGBE IP's. Using macro of maximum number
of channels will create problem for other IP's.

Fix: Assign maximum number of DMA channels based on MAC version.

Bug 200741194

Change-Id: I321780b6868dfb36700863a5852b76424d3bbf6b
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2556425
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Bhadram Varka
c4efd17817 osi: dma: Add debug capabilities 
- Dumps the descriptor if enable_desc_dump flag enabled.
- Dumps registers/structure through OSI DMA IOCTL.

Bug 200737108

Change-Id: I75924cdbd815528dcddba7b9d33dbd4a162f9bbe
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2550985
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Mahesh Patil
b1be67f7cf eqos: core: pad calibration 
Issue:
   1. Current pad calibration does not check for RGMII/MDIO
      interfaces idle
Fix:
  1. Make sure RGMII and MDIO interface are idle before
     doing pad calibration as per spec

Bug 2831220

Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Change-Id: I6b3f35017f62444575d16366d9ac31a5c96fecf7
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2321641
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Narayan Reddy
13808b2444 osi: core: add different XFI/USXGMII modes 
This change takes care of configuring different
connection speeds of XFI/USXGMII modes

Bug 200718307

Change-Id: I28aedb4f7b3a8e4a6bd4acd319487785c8294c05
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2550414
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
rakesh goyal
9c0bebcfd4 osi: common: Add support for MGBE 2 step timestamp 
- OSI DMA
-- During Trasnmit:
 2024-02-21 16:32:06 +05:30
Nagarjuna Kristam
fce6bc8aaa osi: common: Move VM IRQ configuration core to dma 
Issue:
VM IRQ configuration needs is done using DMA base, instead of RM
base.

Fix:
Add VM IRQ configuration code to osi core init sequence.
Remove the same code in DMA.

Bug 200718904
Bug 200730767

Change-Id: I5bf41c85d745a977875ed2eeb044b4db088e0b64
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2539623
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
 2024-02-21 16:32:00 +05:30
nannaiah
5008d33c8b nvethernetrm: Update IVC support for macsec 
1. Cleanup ivc_cmd to remove unwanted commands.
2. Update macsec IVC API's.
3. Add HAL read and write register.

Bug 2694285
Bug 2694285

Change-Id: I4d120b7bcfdc9ed65e2bf35a54fa4233a8b6e534
Signed-off-by: Nagaraj annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2529496
Reviewed-by: Mahesh Patil <maheshp@nvidia.com>
 2024-02-21 16:32:00 +05:30
Mahesh Patil
1e48034244 nvethernetrm: Remove osd callback from osi 
Remove calling osd callback from osi to program SAK and
program SAK from OSD itself.

Bug 3308383

Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Change-Id: I2b27cea66bd9770aec52ed53ba430eb276cf73f7
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2528707
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:00 +05:30
Nagarjuna Kristam
0710ba642b osi: common: Fix mgbe xpcs and osi_common code 
- Return success xpcs-base is null for now.
- Add is mac enable support for MGBE.
- Call HW type common API base on MAC HW.
- Add generic channel mask macro.

Bug 200718904

Change-Id: Icc228697d0464c18af77312457a6bcfbf484ab7d
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2532466
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:32:00 +05:30
Nagarjuna Kristam
cee49f109c osi: dma: Add vm_num entry in irq_data 
Issue:
irq_data structure uses index of its array as VM number assosciated
with that channel. Which is not true.

Fix:
Add vm_num entry in irq_data which is updated by OSD to its corresponding
DMA channels.

Bug 200730767

Change-Id: Ida3219f8d4cef9bda1890e50a20853553f9bd930
Signed-off-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2532465
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:32:00 +05:30
Bhadram Varka
f1c23b4adf osi: update XPCS speed based UPHY GBE mode 
Bug 3288030

Change-Id: Ic33774fce09d1d426d107a8c4bfa883e9a576f6e
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2531231
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
 2024-02-21 16:32:00 +05:30
nannaiah
43aa0ee73d nvethernetrm: Add PTP config to ioctl 
Bug 200671160

Signed-off-by: Nagaraj annaiah <nannaiah@nvidia.com>
Change-Id: I71bad68eb995b9a64f6fdfa85147a722bf751e91
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2525909
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:32:00 +05:30
rakesh goyal
84ddd18b48 core: remove void input argument 
- Changed void input arguments to proper type
- Modifed ivc_msg_common to ivc_msg_common_t

Bug 2739123

Change-Id: Id7964440f6c5d377ba3dd1a7661a2571fdc681d8
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2514922
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:32:00 +05:30
Mahesh Patil
3c7d8ee332 nvethernetrm: Add aes 128/256bit macsec config 
Adding aes 128/256 bit config support through sysfs node

Bug 3257779

Change-Id: Ic1736b309a28faa7591184167a94156ca816fb57
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2484200
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:31:59 +05:30
praveen
8c167c25ac osi: eqos: Add support for clause 45 direct access 
- Add support for clause 45 direct access.

Jira ESDP-11141
Bug 200713249

Change-Id: I647ccc3f57ab35cf4b9e7ef098d807d636dcb692
Signed-off-by: praveen <pbajantri@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2480826
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2517425
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
 2024-02-21 16:31:59 +05:30
Rakesh Goyal
1bcbb28656 nvethernetrm: add interface operations for virtualization/non-virtualization 
Issue:  In current implementation virualization
	callback are at HW ops level, which leads
        to multiple IVC calls.
Fix:	- IVC call happens only for core API's in case
	virtualization
	- For non-virtualization case HW operations will
	be invoked directly from OS OSD.
	- From Ethernet server OSD - OSI HAL API's
	should be called to access the HW operations

Bug 200671160

Change-Id: Ic3730fb822ae37fdf29fabf429f18f5d5bacd210
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2509243
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:31:59 +05:30
Mahesh Patil
4562e552e4 nvethernetrm: Enable key program through TZ 
Enabling macsec key's programming using TZ

Bug 3246511

Change-Id: I1e7633b042e1ebedef78fff9812aeaaa2480a1c4
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2478489
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:31:59 +05:30
nannaiah
17756932dc osi: Add virtualization fix. 
- Change osi_readl to osi_readla
- Change osi_writel to osi_writela
- Add IVC macsec commands.
- Add OSI_MGBE_MAC_3_00 as valid list of version.
- Disable validate_func_ptrs as it returns failure.

Bug 2694285
JIRA T23XMGBE-118

Signed-off-by: Nagaraj annaiah <nannaiah@nvidia.com>
Change-Id: I49187c0decb3de4184b7ef5e3a2e553a60c1d54f
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2515254
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:31:59 +05:30
rakesh goyal
d3116f4cf2 core: handle ioctl in single API 
To reduce number of external interface APIs,
consolidate all IOCTL API to one interface API.

Bug 200671160

Change-Id: I407ee5c50c8b3293c5be613beda68e1e450dce89
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
 2024-02-21 16:31:59 +05:30
Bhadram Varka
b60b44dc67 osi: add support for handling multiple IP's 
Issue: Since core_ops/dma_chan_ops are static global
variables and these are stored in data segment of
a process. In linux when insmod happens eqos and mgbe
will get probe which inturn initialize osi core ops.
Since data segment is shared here eqos core ops pointer
overwritten by mgbe core operations.

Fix: Use separe core ops and local global variable
for each instance.

Bug 200671160

Change-Id: I7f093608d812e2ced1bf73339dbd70f0091fe5b4
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:31:59 +05:30
Mahesh Patil
8273721434 nvethernetrm: Reduce 2 byte ethertype from mtu 
Add 2 byte to SECTAG+ICV length to reduce 2 byte mtu size
Bug 200690445

Change-Id: I4ccab6958e73fdfe90e386714a5ea4a8454ed8d9
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
 2024-02-21 16:31:59 +05:30
Srinivas Ramachandran
bc73f82428 nvethernetrm: Add support for MACsec controller 
This commit adds support for MACsec controller HW
operations. The MACsec HW ops can be accessed via
osi_core layer.

Currently, MACsec HW is enabled when MAC interface
is brough up, with no LUT entry so that packets
will still be bypassed. MTU check is enabled and
default interrupts are enabled for statistics.

Bug 2913560

Change-Id: I62e8567fac6603db47f4069a40458038f9b4178a
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
 2024-02-21 16:31:59 +05:30
Mohan Thadikamalla
57847505ed nvethernetrm: mgbe: Add XDCS support 
Enable multiple DMA Channels routing support
for MC/BC MAC Address with XDCS.

Bug 200565911

Change-Id: I7c9f9347361dd72e68696846a0a59e2e241e20c9
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
 2024-02-21 16:31:59 +05:30
narayanr
b5a12c85e6 osi: mgbe: program recommended values 
program the recommended values by HW team for
better performance

Bug 200565630
Bug 200570017

Change-Id: I96a870114623ce76804c49706d2961010448ca86
Signed-off-by: narayanr <narayanr@nvidia.com>
 2024-02-21 16:31:59 +05:30
mohant
c5df9eacea nvethernetrm: Add PTP offload support 
Bug 200562286

Change-Id: I7adf08da12458c7291391ef726fe1fa65cb1bda1
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2319556
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:31:59 +05:30
Mohan Thadikamalla
984a87dfff nvethernetrm: Add Flexible Receive Parser support 
- Define new data structure for the FRP table entry,
declare new frp_table and NVE variables in the OSI
core private structure.
- Define a new data structure for the OSI FRP command.
Add new OSI API to initiate FRP commands from OSD.

Bug 200565623

Change-Id: I84660a6e8270a681b82236d0c39423660b3821ff
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2330182
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:31:59 +05:30
rakesh goyal
75a529b2f0 nvethernetrm: eqos: TSN support for EQOS IP 
1. Adds basic OSI API's for EST/FPE
2. EST/FPE support for EQOS
3. MMC counters for FPE
4. EST errors and state counter

Bug 200561100

Change-Id: Iee3e6caac5d16e1620c25420d72700f9cdd00465
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2319820
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:31:59 +05:30
Bhadram Varka
ed13225788 nvethernetrm: update SSINC & ptp_ref_clk 
Configure SSINC and ptp_ref_clk based on ethernet IP

Bug 200565914

Change-Id: I0a29d4506f56c7e4bdb36cc2cee9276f849b4a26
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2320590
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:31:59 +05:30
Rakesh Goyal
f6cbb32a42 nvethernetrm: mgbe: add PTP support 
Change takes care of -
o Enable PTP for MGBE
o Added flags for One step/two step and also
for PTP master/slave
o Getting timestamp from MAC registers for MGBE.

Bug 200565914

Change-Id: I17346451f2619f0526a737a4a6bffdf130af4fc0
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2314201
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:31:59 +05:30
vbhadram
d17a9e4c63 nvethernetrm: mgbe: add support for RSS 
This change programs 40byte Hash key and indirection table
(Hash table) (has DMA channel numbers) in MAC
Once packet received by MAC - 4-tuples will be extracted
from the packet and given to RSS hash engine. Hash function
will generate hash value by using 40byte key.
From hash value LSB bits used as index to RSS lookup table to
find out DMA channel number. If there is a match - packet is
routed to corresponding DMA channel. If there is no match -
packet will be dropped and error will be returned in receive desc.

Bug 200565647

Change-Id: Iffbb5a452f03278b3ba0bc061f09b43c7c994289
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2263398
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
 2024-02-21 16:31:59 +05:30
Mohan Thadikamalla
e540dd4386 nvethernetrm: Add RX Route support 
- Add new ptp_rx_queue variable in
  osi_ptp_config structure.
- Declare an IP callback function
  for PTP RX queue index programming.
- Check and call IP based PTP RX queue
  callback in osi_ptp_configuration.

Bug 200596985

Change-Id: Ief040dc5b607ad729af5e9c0c1870249b456dcc7
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
 2024-02-21 16:31:59 +05:30
Narayan Reddy
d7e31f4de7 nvethernetrm: mgbe: add flow control support 
Add flow control support for MGBE.

Bug 200565905

Change-Id: I4edb82225cfd60fcff47d0aef11b516d9960961a
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2278454
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:31:59 +05:30
Bhadram Varka
99ad1ad78e nvethernetrm: mgbe/eqos: Add support for VLAN 
Adds support for VLAN insertion/deletion and filtering
on receive side.

Perfect filtering enabled for the VLAN filtering.
HW maximum has 32 VLAN perfect filters. If user adds
more than 32 then all VID's will be allowed

Bug 200565888

Change-Id: I75bdc261a77df4f9d9f5fff9a2943731de9dd4ef
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2312144
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
 2024-02-21 16:31:59 +05:30
Mohan Thadikamalla
06a55f9c41 nvethernetrm: mgbe: Add AVB CBS support 
Add AVB CBS set and get operations
support.

Bug 200565900

Change-Id: I5402a5ac9dcb080c69a11aaa2eec52f68fe833b8
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2309941
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
 2024-02-21 16:31:59 +05:30
Mohan Thadikamalla
00e4638fa3 nvethernetrm: mgbe: Add L3 and L4 filtering 
Add L3 IP address filtering support and
L4 port filtering support

Bug 200565909

Change-Id: I31748cfacf41bb6358813b80eabb57dd6416da5c
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2274443
 2024-02-21 16:31:59 +05:30
Mohan Thadikamalla
68a1d27ab0 nvethernetrm: mgbe: Add DA/SA/MC/BC filtering 
Add support for DA/SA/MC/BC L2 address filtering.
Enable MCBC queue, and set queue1 for MCBC queue.

Bug 200565909

Change-Id: I79c2608d1f878695eb8f9c8c3c836c1d458095a0
Signed-off-by: Mohan Thadikamalla <mohant@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2274442
 2024-02-21 16:31:59 +05:30
Bhadram Varka
41ef64576a nvethernetrm: xpcs: XPCS initialization 
Add support for XPCS initialization in USXMII mode
and start of XPCS will happen once speed set for MAC.

Bug 200552796

Change-Id: I4c98bec2e92d9b189c7d2404705e28b969592f33
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2258482
 2024-02-21 16:31:59 +05:30
Bhadram Varka
a2b8d81e43 nvethernetrm: mgbe: support for MAC speed set 
Adds support for programming MAC speed based
on PHY speed.

Bug 200565886

Change-Id: I486444186b5575f68d6336229e0672e219725444
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2258483
 2024-02-21 16:31:59 +05:30
Bhadram Varka
c0091a34ef nvethernetrm: add support for MGBE initialization 
Adds MAC CORE and DMA initialization support for
MGBE MAC Controller.

Bug 200548572

Change-Id: I6796229852b47ff0748a848a6dbe9addab6ab74f
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2250401
 2024-02-21 16:31:59 +05:30
Bhadram Varka
d2dd7fefbf osi: core: fix coverity/misra issues 
Bug 200671160

Change-Id: I98f0bb2a4a0fde05b81551cd2dd0cab4ddac13dc
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:31:59 +05:30
Rakesh Goyal
cd35e725a8 Revert "core: handle ioctl in single API" 
This reverts commit 6b8e39f6d3.

Bug 200671160

Change-Id: Icf22d93e83efbff7cb2a3cdfd5d169e3fd454b4a
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
 2024-02-21 16:31:59 +05:30
nannaiah
49f168e572 nvethernetrm: Add IVC support to read mmc counters. 
Bug 2694285

Change-Id: I4d88b99968a90108fcb218eb607318da14875834
Signed-off-by: Nagaraj Annaiah <nannaiah@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2499175
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Ajay Gupta <ajayg@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:31:59 +05:30
rakesh goyal
a16b1a8a03 core: handle ioctl in single API 
To reduce number of external interface APIs,
consolidate all IOCTL API to one interface API.

Bug 200671160

Change-Id: I324bf794b66f6267b9cf4c64059bdd07b90579d4
Signed-off-by: rakesh goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2493164
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:31:59 +05:30
Bhadram Varka
64afd564e4 osi: single API to handle DMA interrupts 
Issue: Currently there are multiple API's for
handling DMA interrupts.

Fix: Creating single API to handle DMA interrupts.

Bug 200671160

Change-Id: I9385e8fb0ca044c7a01d38483226e2e83f76f5b9
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2497610
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:31:59 +05:30