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6c637ac71e
Bug 3918941 Change-Id: Iae1cce6bb0bffaa20d601a0c5da62045ce9458fc Signed-off-by: Revanth Kumar Uppala <ruppala@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2852448 Tested-by: mobile promotions <svcmobile_promotions@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
106 lines
3.6 KiB
C
106 lines
3.6 KiB
C
/*
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* Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef INCLUDED_MGBE_DMA_H
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#define INCLUDED_MGBE_DMA_H
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/**
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* @addtogroup MGBE AXI Clock defines
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*
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* @brief AXI Clock defines
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* @{
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*/
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#define MGBE_AXI_CLK_FREQ 480000000U
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/** @} */
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/**
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* @addtogroup MGBE_DMA DMA Channel Register offsets
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*
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* @brief MGBE DMA Channel register offsets
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* @{
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*/
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#define MGBE_DMA_CHX_TX_CTRL(x) ((0x0080U * (x)) + 0x3104U)
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#define MGBE_DMA_CHX_RX_CTRL(x) ((0x0080U * (x)) + 0x3108U)
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#ifndef OSI_STRIPPED_LIB
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#define MGBE_DMA_CHX_SLOT_CTRL(x) ((0x0080U * (x)) + 0x310CU)
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#endif /* !OSI_STRIPPED_LIB */
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#define MGBE_DMA_CHX_INTR_ENA(x) ((0x0080U * (x)) + 0x3138U)
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#define MGBE_DMA_CHX_CTRL(x) ((0x0080U * (x)) + 0x3100U)
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#define MGBE_DMA_CHX_RX_WDT(x) ((0x0080U * (x)) + 0x313CU)
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#define MGBE_DMA_CHX_TX_CNTRL2(x) ((0x0080U * (x)) + 0x3130U)
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#define MGBE_DMA_CHX_RX_CNTRL2(x) ((0x0080U * (x)) + 0x3134U)
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#define MGBE_DMA_CHX_TDLH(x) ((0x0080U * (x)) + 0x3110U)
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#define MGBE_DMA_CHX_TDLA(x) ((0x0080U * (x)) + 0x3114U)
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#define MGBE_DMA_CHX_TDTLP(x) ((0x0080U * (x)) + 0x3124U)
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#define MGBE_DMA_CHX_RDLH(x) ((0x0080U * (x)) + 0x3118U)
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#define MGBE_DMA_CHX_RDLA(x) ((0x0080U * (x)) + 0x311CU)
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#define MGBE_DMA_CHX_RDTLP(x) ((0x0080U * (x)) + 0x312CU)
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/** @} */
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/** @} */
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/**
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* @addtogroup MGBE_BIT BIT fields for MGBE channel registers
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*
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* @brief Values defined for the MGBE registers
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* @{
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*/
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#define MGBE_DMA_CHX_RX_WDT_RWT_MASK 0xFFU
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#define MGBE_DMA_CHX_RX_WDT_RWTU 2048U
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#define MGBE_DMA_CHX_RX_WDT_RWTU_2048_CYCLE 0x3000U
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#define MGBE_DMA_CHX_RX_WDT_RWTU_MASK 0x3000U
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#ifdef OSI_DEBUG
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#define MGBE_DMA_CHX_INTR_TBUE OSI_BIT(2)
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#define MGBE_DMA_CHX_INTR_RBUE OSI_BIT(7)
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#define MGBE_DMA_CHX_INTR_FBEE OSI_BIT(12)
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#define MGBE_DMA_CHX_INTR_AIE OSI_BIT(14)
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#define MGBE_DMA_CHX_INTR_NIE OSI_BIT(15)
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#endif
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#ifndef OSI_STRIPPED_LIB
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#define MGBE_DMA_CHX_SLOT_ESC OSI_BIT(0)
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#endif /* !OSI_STRIPPED_LIB */
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#define MGBE_DMA_CHX_TX_CNTRL2_ORRQ_RECOMMENDED 64U
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#define MGBE_DMA_CHX_TX_CNTRL2_ORRQ_SHIFT 24U
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#define MGBE_DMA_CHX_RX_CNTRL2_OWRQ_SCHAN 32U
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#define MGBE_DMA_CHX_RX_CNTRL2_OWRQ_MCHAN 64U
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#define MGBE_DMA_CHX_RX_CNTRL2_OWRQ_SHIFT 24U
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#define MGBE_DMA_CHX_CTRL_PBL_SHIFT 16U
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/** @} */
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/**
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* @addtogroup MGBE PBL settings.
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*
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* @brief Values defined for PBL settings
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* @{
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*/
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/* Tx Queue size is 128KB */
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#define MGBE_TXQ_SIZE 131072U
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/* Rx Queue size is 192KB */
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#define MGBE_RXQ_SIZE 196608U
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/* MAX PBL value */
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#define MGBE_DMA_CHX_MAX_PBL 256U
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#define MGBE_DMA_CHX_MAX_PBL_VAL 0x200000U
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/* AXI Data width */
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#define MGBE_AXI_DATAWIDTH 128U
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/** @} */
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#endif
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