mirror of
git://nv-tegra.nvidia.com/kernel/nvethernetrm.git
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8c7f7328e8
Bug 4043836 Ported from the change - https://git-master.nvidia.com/r/c/nvethernet-docs/+/2896005 Change-Id: Iabbbde0d2733f04bba5d7128e7b8ac5956605424 Signed-off-by: Mahesh Patil <maheshp@nvidia.com> Signed-off-by: Michael Hsu <mhsu@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3149288 GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com> Tested-by: Bhadram Varka <vbhadram@nvidia.com> Tested-by: Seema Khowala <seemaj@nvidia.com> Reviewed-by: Ashutosh Jha <ajha@nvidia.com> Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
209 lines
7.1 KiB
C
209 lines
7.1 KiB
C
/* SPDX-License-Identifier: LicenseRef-NvidiaProprietary
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* SPDX-FileCopyrightText: Copyright (c) 2020-2024 NVIDIA CORPORATION & AFFILIATES.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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#ifndef INCLUDED_XPCS_H_
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#define INCLUDED_XPCS_H_
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#include "common.h"
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#include <osi_core.h>
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/**
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* @addtogroup XPCS Register offsets
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*
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* @brief XPCS register offsets
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* @{
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*/
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#define XPCS_ADDRESS 0x03FC
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#define XPCS_SR_XS_PCS_STS1 0xC0004
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#define XPCS_SR_XS_PCS_CTRL2 0xC001C
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#define XPCS_VR_XS_PCS_DIG_CTRL1 0xE0000
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#define XPCS_VR_XS_PCS_KR_CTRL 0xE001C
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#define XPCS_SR_AN_CTRL 0x1C0000
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#define XPCS_SR_MII_CTRL 0x7C0000
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#define XPCS_VR_MII_AN_INTR_STS 0x7E0008
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#define XPCS_WRAP_UPHY_HW_INIT_CTRL 0x8020
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#define XPCS_WRAP_UPHY_STATUS 0x8044
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#define XPCS_WRAP_UPHY_RX_CONTROL_0_0 0x801C
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#define XPCS_WRAP_INTERRUPT_STATUS 0x8050
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#define T26X_XPCS_WRAP_UPHY_HW_INIT_CTRL 0x8034
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#define T26X_XPCS_WRAP_UPHY_STATUS 0x8074
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#define T26X_XPCS_WRAP_INTERRUPT_STATUS 0x8080
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/** @} */
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#ifndef OSI_STRIPPED_LIB
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#define XPCS_VR_XS_PCS_EEE_MCTRL0 0xE0018
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#define XPCS_VR_XS_PCS_EEE_MCTRL1 0xE002C
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#define XPCS_VR_XS_PCS_EEE_MCTRL1_TRN_LPI OSI_BIT(0)
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#define XPCS_VR_XS_PCS_EEE_MCTRL0_LTX_EN OSI_BIT(0)
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#define XPCS_VR_XS_PCS_EEE_MCTRL0_LRX_EN OSI_BIT(1)
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#endif /* !OSI_STRIPPED_LIB */
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/**
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* @addtogroup XPCS-BIT Register bit fileds
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*
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* @brief XPCS register bit fields
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* @{
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*/
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#define XPCS_SR_XS_PCS_CTRL2_PCS_TYPE_SEL_BASE_R 0x0U
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#define XPCS_SR_XS_PCS_STS1_RLU OSI_BIT(2)
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#define XPCS_SR_XS_PCS_STS1_FLT OSI_BIT(7)
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#define XPCS_VR_XS_PCS_DIG_CTRL1_USXG_EN OSI_BIT(9)
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#define XPCS_VR_XS_PCS_DIG_CTRL1_VR_RST OSI_BIT(15)
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#define XPCS_VR_XS_PCS_DIG_CTRL1_USRA_RST OSI_BIT(10)
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#define XPCS_VR_XS_PCS_DIG_CTRL1_CL37_BP OSI_BIT(12)
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#define XPCS_SR_AN_CTRL_AN_EN OSI_BIT(12)
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#define XPCS_SR_MII_CTRL_AN_ENABLE OSI_BIT(12)
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#define XPCS_VR_MII_AN_INTR_STS_CL37_ANCMPLT_INTR OSI_BIT(0)
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#define XPCS_SR_MII_CTRL_SS5 OSI_BIT(5)
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#define XPCS_SR_MII_CTRL_SS6 OSI_BIT(6)
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#define XPCS_SR_MII_CTRL_SS13 OSI_BIT(13)
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#define XPCS_USXG_AN_STS_SPEED_MASK 0x1C00U
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#define XPCS_USXG_AN_STS_SPEED_2500 0x1000U
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#define XPCS_USXG_AN_STS_SPEED_5000 0x1400U
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#define XPCS_USXG_AN_STS_SPEED_10000 0xC00U
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#define XPCS_REG_ADDR_SHIFT 10U
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#define XPCS_REG_ADDR_MASK 0x1FFFU
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#define XPCS_REG_VALUE_MASK 0x3FFU
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#define XPCS_VR_XS_PCS_KR_CTRL_USXG_MODE_MASK (OSI_BIT(12) | \
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OSI_BIT(11) | \
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OSI_BIT(10))
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#define XPCS_VR_XS_PCS_KR_CTRL_USXG_MODE_5G OSI_BIT(10)
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#define XPCS_WRAP_UPHY_HW_INIT_CTRL_TX_EN OSI_BIT(0)
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#define XPCS_WRAP_UPHY_HW_INIT_CTRL_RX_EN OSI_BIT(2)
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#define XPCS_WRAP_IRQ_STATUS_PCS_LINK_STS OSI_BIT(6)
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#define XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_DATA_EN OSI_BIT(0)
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#define XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_IDDQ OSI_BIT(4)
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#define XPCS_WRAP_UPHY_RX_CONTROL_0_0_AUX_RX_IDDQ OSI_BIT(5)
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#define XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_SLEEP (OSI_BIT(6) | \
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OSI_BIT(7))
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#define XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_CAL_EN OSI_BIT(8)
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#define XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_CDR_RESET OSI_BIT(9)
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#define XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_PCS_PHY_RDY OSI_BIT(10)
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#define XPCS_WRAP_UPHY_RX_CONTROL_0_0_RX_SW_OVRD OSI_BIT(31)
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#define XPCS_WRAP_UPHY_STATUS_TX_P_UP_STATUS OSI_BIT(0)
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#define XPCS_WRAP_UPHY_STATUS_RX_P_UP_STATUS OSI_BIT(2)
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#ifdef HSI_SUPPORT
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#define XPCS_WRAP_INTERRUPT_CONTROL 0x8048
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#define T26X_XPCS_WRAP_INTERRUPT_CONTROL 0x8078
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#define XPCS_CORE_CORRECTABLE_ERR OSI_BIT(10)
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#define XPCS_CORE_UNCORRECTABLE_ERR OSI_BIT(9)
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#define XPCS_REGISTER_PARITY_ERR OSI_BIT(8)
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#define XPCS_VR_XS_PCS_SFTY_UE_INTR0 0xE03C0
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#define XPCS_VR_XS_PCS_SFTY_CE_INTR 0xE03C8
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#define XPCS_VR_XS_PCS_SFTY_TMR_CTRL 0xE03D4
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#define XPCS_SFTY_1US_MULT_MASK 0xFFU
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#define XPCS_SFTY_1US_MULT_SHIFT 0U
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#define XPCS_FSM_TO_SEL_SHIFT 10U
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#define XPCS_FSM_TO_SEL_MASK 0xC00U
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#define XPCS_FEC_EN OSI_BIT(0)
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#endif
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/** @} */
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nve32_t xpcs_init(struct osi_core_priv_data *osi_core);
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nve32_t xpcs_start(struct osi_core_priv_data *osi_core);
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#ifndef OSI_STRIPPED_LIB
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nve32_t xpcs_eee(struct osi_core_priv_data *osi_core, nveu32_t en_dis);
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#endif /* !OSI_STRIPPED_LIB */
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/**
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* @brief xpcs_read - read from xpcs.
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*
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* Algorithm: This routine reads data from XPCS register.
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*
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* @param[in] xpcs_base: XPCS virtual base address
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* @param[in] reg_addr: register address to be read
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*
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* @retval value read from xpcs register.
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*/
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static inline nveu32_t xpcs_read(void *xpcs_base, nveu32_t reg_addr)
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{
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osi_writel(((reg_addr >> XPCS_REG_ADDR_SHIFT) & XPCS_REG_ADDR_MASK),
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((nveu8_t *)xpcs_base + XPCS_ADDRESS));
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return osi_readl((nveu8_t *)xpcs_base +
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((reg_addr) & XPCS_REG_VALUE_MASK));
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}
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/**
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* @brief xpcs_write - write to xpcs.
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*
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* Algorithm: This routine writes data to XPCS register.
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*
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* @param[in] xpcs_base: XPCS virtual base address
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* @param[in] reg_addr: register address for writing
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* @param[in] val: write value to register address
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*/
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static inline void xpcs_write(void *xpcs_base, nveu32_t reg_addr,
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nveu32_t val)
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{
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osi_writel(((reg_addr >> XPCS_REG_ADDR_SHIFT) & XPCS_REG_ADDR_MASK),
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((nveu8_t *)xpcs_base + XPCS_ADDRESS));
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osi_writel(val, (nveu8_t *)xpcs_base +
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(((reg_addr) & XPCS_REG_VALUE_MASK)));
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}
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/**
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* @brief xpcs_write_safety - write to xpcs.
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*
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* Algorithm: This routine writes data to XPCS register.
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* And verifiy by reading back the value
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*
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* @param[in] osi_core: OSI core data structure
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* @param[in] reg_addr: register address for writing
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* @param[in] val: write value to register address
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*
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* @retval 0 on success
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* @retval XPCS_WRITE_FAIL_CODE on failure
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*
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*/
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static inline nve32_t xpcs_write_safety(struct osi_core_priv_data *osi_core,
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nveu32_t reg_addr,
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nveu32_t val)
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{
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void *xpcs_base = osi_core->xpcs_base;
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nveu32_t read_val;
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nve32_t retry = 10;
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nve32_t ret = XPCS_WRITE_FAIL_CODE;
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while (--retry > 0) {
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xpcs_write(xpcs_base, reg_addr, val);
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read_val = xpcs_read(xpcs_base, reg_addr);
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if (val == read_val) {
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ret = 0;
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break;
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}
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osi_core->osd_ops.udelay(OSI_DELAY_1US);
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}
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#ifndef OSI_STRIPPED_LIB
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if (ret != 0) {
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OSI_CORE_ERR(osi_core->osd, OSI_LOG_ARG_HW_FAIL,
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"xpcs_write_safety failed", reg_addr);
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}
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#endif /* !OSI_STRIPPED_LIB */
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return ret;
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}
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#endif /* INCLUDED_XPCS_H_ */
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