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8c7f7328e854c984a5e820c67915ebd60cb15f2f
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43 Commits

Author SHA1 Message Date
Mahesh Patil
8c7f7328e8 osi: T264 VDMA feature and bring up changes 
Bug 4043836

Ported from the change -
https://git-master.nvidia.com/r/c/nvethernet-docs/+/2896005

Change-Id: Iabbbde0d2733f04bba5d7128e7b8ac5956605424
Signed-off-by: Mahesh Patil <maheshp@nvidia.com>
Signed-off-by: Michael Hsu <mhsu@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3149288
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Tested-by: Bhadram Varka <vbhadram@nvidia.com>
Tested-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-06-05 02:51:04 -07:00
Narayan Reddy
d28da6a10b xpcs: update lane programming sequence 
1) Updated the HW programming sequence of XPCS lane bring up
2) As a part of the link bringup, link partners exchange fault
sequence (local and remote faults) initially. Driver was enabling
the Link fault interrupt before the fault sequence is fully complete,
so added a condition to wait until the initial fault sequence
is complete before enabling the link fault interrupt in the MAC.

Bug 4301751

Change-Id: I369023d8ed5eef8e436105148d9f28b87aab1ca1
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3095516
(cherry picked from commit 7522e79f6d6f0b39c4ee1f3d078fbb5da45592b0)
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3133226
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-05-22 10:04:27 -07:00
Bhadram Varka
9a2f67acf6 osi: core: cleanup the code 
Removed unneeded code as a part of clean up

Bug 4284096

Change-Id: I72d2315bd641f4a46c7f78029214c23599c9b831
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3063333
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
Tested-by: Narayan Reddy <narayanr@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2024-02-21 16:32:07 +05:30
Narayan Reddy
9ec6ef675b osi: core: cleanup the code 
Clean up the code to remove unnecessary branches

Bug 4284096

Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Change-Id: I7cef09e14818016b68e0297cb8446d10880b1b13
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3058726
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2024-02-21 16:32:07 +05:30
Narayan Reddy
d68e9e1bdc osi: core: fix hsi configuration 
Enable below for the HSI configuration
  RXCRCERPIE of MMC_Receive_Interrupt_Enable
  TMOUTEN of MAC_FSM_Control
  OPE of MTL_DPP_Control
  TMOUTEN of MAC_FSM_Control
  FSM_TO_SEL of VR_XS_PCS_SFTY_TMR_CTRL

Bug 4437102

Change-Id: Iaef9bc3e8e44572fd953dbc4d846d871bb2d16a0
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3051420
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:07 +05:30
Narayan Reddy
e4c8bc9f3e osi: core: fix CG issues as per CR review 
Fixed below violations
 NETWORKING_CG_003
 NETWORKING_CG_006
 Code complexity

Jira NET-1169

Change-Id: Id985b8d8ff7e79dff929f44fb7d8fd9daff3f709
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3029471
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2024-02-21 16:32:07 +05:30
Narayan Reddy
fa049ecc89 osi: xpcs: add delays as per HW team suggestion 
Issue: Random delays were added in xpcs_start and xpcs_init
which can lead to increase in the boot time

Fix: Instead of adding random delays and retries add  the
exact delays suggested by HW team

Bug 3806700

Change-Id: If6f781d86c7de4019883e4b02dc89b2d04ecc768
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2826256
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Zuyu Liao <zuyul@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Tested-by: Zuyu Liao <zuyul@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2024-02-21 16:32:07 +05:30
Narayan Reddy
ed1fdde882 osi: core: fix MISRA rule 15.5 
JIRA NET-520
Bug 3899804

Change-Id: Ibec55a06c960aec5550cdea77dbaf89210f49b9e
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2820748
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:07 +05:30
Om Prakash Singh
858dc4815f osi: core: enable HSI_SUPPORT and fix MISRA issue 
enable HSI_SUPPORT at OSI unit level and address
misra issues.

Bug 3590939
Change-Id: Ia87bafe077553d0140219047a578100c3f5684aa
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2784224
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:07 +05:30
Om Prakash Singh
6ebced1c84 osi: core: add SW error code for XPCS write failure 
As return specific error code on PCS read-after-write fails.
And add SW error code to report for FSI on failure.

Bug 3792855

Change-Id: I51b8a088247d98621750af7bb42100a078c083c2
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2781195
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:07 +05:30
Narayan Reddy
ef38debe2e osi: core: fix misra 4.6 rule 
===== DIFF ======
Total misra violation count changed by -240
Rule: MISRA_C-2012_Directive_4.6 Diff: -240
Rule: Total Diff: -240

Bug 3695218

Change-Id: Ida2d3a775872637eda3058ea361a00346c86f7f7
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2767895
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2024-02-21 16:32:06 +05:30
Bhadram Varka
2088de15a9 osi: Pass OSD pointer for better logging 
Issue: Currently logs don't have any IP/inteface specific
name to indicate that from which IP/interface these
logs are coming.

Fix: Pass OSD pointer so that interface or device name
can be added to the logs.

Reduce XPCS logging

Bug 3719492
Bug 3722532

Change-Id: Id909b14f24f441ab40ff6497f1998aeb4ab34611
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2745731
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2024-02-21 16:32:06 +05:30
Narayan Reddy
4621665fca osi: core: Fix MISRA issues 
Fixed straight forward MISRA issues

===== DIFF ======
Total misra violation count changed by -319
Rule: MISRA_C-2012_Directive_4.4 Diff: -3
Rule: MISRA_C-2012_Directive_4.6 Diff: -32
Rule: MISRA_C-2012_Directive_4.9 Diff: 3
Rule: MISRA_C-2012_Rule_10.1 Diff: -4
Rule: MISRA_C-2012_Rule_10.3 Diff: -2
Rule: MISRA_C-2012_Rule_10.4 Diff: -21
Rule: MISRA_C-2012_Rule_11.1 Diff: -20
Rule: MISRA_C-2012_Rule_12.1 Diff: -74
Rule: MISRA_C-2012_Rule_15.5 Diff: 1
Rule: MISRA_C-2012_Rule_15.7 Diff: -2
Rule: MISRA_C-2012_Rule_16.1 Diff: -1
Rule: MISRA_C-2012_Rule_16.3 Diff: -1
Rule: MISRA_C-2012_Rule_17.7 Diff: -5
Rule: MISRA_C-2012_Rule_2.5 Diff: -157
Rule: MISRA_C-2012_Rule_8.6 Diff: -1
Rule: Total Diff: -319

JIRA NET-96
Bug 3695218

Change-Id: I221f95aaf23e9214fde21632b68425b705552752
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2735077
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Om Prakash Singh
0c754dc009 core: add pcs register readback after write support 
As per T23X-MGBE_HSIv2-14 requirement for PCS register
we need to perform readback for each write operation
to verify write operation was successful

Bug 3606649
Change-Id: I7cca6baa43feaa4207b6158f0abc796e656338dd
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2700845
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2024-02-21 16:32:06 +05:30
Om Prakash Singh
9775acba84 osi: core: fix XPCS_REG_VALUE_MASK 
Issue: PCS register read/write is failing due to wrong value of
 XPCS_REG_VALUE_MASK;

Fix: update XPCS_REG_VALUE_MASK value to 0x3FF

Bug 3591736

Change-Id: Id62aff5f8749b94810475ff79665899a10bec3e4
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2701996
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Om Prakash Singh
a7c927d757 osi: core: add support for HSI 
1) Add OSI IOCTL to enable HSI feature at runtime
2) Enable LIC interrupt for Correctable, Uncorrectable and
   Parity error
3) Program register to enable safety feature

Bug 3543410

Change-Id: I8a9f33bab72eb37e8aa64c16c610be6e5271c7f8
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2670989
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Narayan Reddy
c05156ed33 osi: core: Enable Transparent Tx LPI Mode 
In this mode, the transmit LPI state-machine
does not move to TX_QUIET state. On detecting Lower-Power Idle
on XGMII/GMII Tx interface, xpcs goes to the TX_SLEEP state and
remains in this state till MAC stops sending LPI.

Bug 200764486

Change-Id: I376ac481e880472d7a11b60931a90d6f9c7a0067
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2598380
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
8a9421a4c3 osi: xpcs: Fix Tx lane bring-up failure 
Issue:
During Tx lane bring up power up will fail if
the lane is already powered up.

Fix:
Don't bring-up Tx lane if its already powered up.

Bug 200766119
Bug 200764018

Change-Id: Idbdffdca7b9c9cccd8b8876fcfe8ea7448a7ed10
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2597604
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Narayan Reddy
baf06e1083 osi: core: xpcs: modify lane bringup sequence 
Issue: there is a PHY reset(RX_PCS_PHY_RDY) programming
in Rx sequence that was disabling the Tx path from MGBE PCS

Fix: Control entire programming sequence from SW and
by pass HW FSM

Bug 3359851
Bug 200765222

Change-Id: Iffd00d1dff00204e36eb3a14b19c07dcd3a502b8
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2584394
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:06 +05:30
Bhadram Varka
3d5aa3b5d0 osi: xpcs: support for Tx/Rx lane bring-up 
Below is per Lane bring-up sequence as per IAS

SW should trigger per lane bring up sequence as follows.
o Set PCS_WRAP_UPHY_HW_INIT_CONTROL_0_0. HW_TX_INIT_EN = 1
o Set PCS_WRAP_UPHY_HW_INIT_CONTROL_0_0. HW_RX_INIT_EN = 1
o Wait for HW_TX_INIT_EN = 0
o Wait for HW_RX_INIT_EN = 0
o Check PCS Lock status by reading the status bit
  “PCS_WRAP_INTERRUPT_STATUS_0.PCS_LINK_STS”

This change implements above sequence.

Above sequence not required for pre-silicon platforms
because NvUPHY is not available.

Bug 200740702

Change-Id: I40415e25bc6ded9a1692a381399105487a306efc
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2543048
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2024-02-21 16:32:05 +05:30
Bhadram Varka
f1c23b4adf osi: update XPCS speed based UPHY GBE mode 
Bug 3288030

Change-Id: Ic33774fce09d1d426d107a8c4bfa883e9a576f6e
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2531231
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
 2024-02-21 16:32:00 +05:30
Narayan Reddy
912cec99ca nvethernetrm: Add support for EEE LPI 
Add an API to configure the EEE LPI mode.
Tx LPI is enabled with a default entry time of 1sec.
The MAC controller has capability to automatically
enter LPI mode when all transmissions are complete.

Bug 200565917

Change-Id: I59b5eccc83770bc7dff9dadb192b733e0d01d7dd
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2274444
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:31:59 +05:30
narayanr
a41808f643 nvethernetrm: mgbe: fix doxygen comments 
Bug 200598918

Change-Id: I230c16d83070356efc8560b26a238db7927e7adf
Signed-off-by: narayanr <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2314668
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2024-02-21 16:31:59 +05:30
Bhadram Varka
41ef64576a nvethernetrm: xpcs: XPCS initialization 
Add support for XPCS initialization in USXMII mode
and start of XPCS will happen once speed set for MAC.

Bug 200552796

Change-Id: I4c98bec2e92d9b189c7d2404705e28b969592f33
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2258482
 2024-02-21 16:31:59 +05:30
Bhadram Varka
93c142ba2a delete the directories to move the history 
Change-Id: I701c1a8c6c891dc8ee2781d51c2c6ad748ed5bf3
 2024-02-21 16:31:52 +05:30
Narayan Reddy
ddd0ab4e61 osi: xpcs: add delays as per HW team suggestion 
Issue: Random delays were added in xpcs_start and xpcs_init
which can lead to increase in the boot time

Fix: Instead of adding random delays and retries add  the
exact delays suggested by HW team

Bug 3806700

Change-Id: If6f781d86c7de4019883e4b02dc89b2d04ecc768
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2826256
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Zuyu Liao <zuyul@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: svc-mobile-misra <svc-mobile-misra@nvidia.com>
Reviewed-by: svc-mobile-cert <svc-mobile-cert@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Tested-by: Zuyu Liao <zuyul@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-12-23 15:13:05 -08:00
Narayan Reddy
4d974956c0 osi: core: fix MISRA rule 15.5 
JIRA NET-520
Bug 3899804

Change-Id: Ibec55a06c960aec5550cdea77dbaf89210f49b9e
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2820748
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-12-12 15:08:52 -08:00
Om Prakash Singh
aaf12511a3 osi: core: enable HSI_SUPPORT and fix MISRA issue 
enable HSI_SUPPORT at OSI unit level and address
misra issues.

Bug 3590939
Change-Id: Ia87bafe077553d0140219047a578100c3f5684aa
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2784224
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-11-09 11:18:49 -08:00
Om Prakash Singh
b35c75e1db osi: core: add SW error code for XPCS write failure 
As return specific error code on PCS read-after-write fails.
And add SW error code to report for FSI on failure.

Bug 3792855

Change-Id: I51b8a088247d98621750af7bb42100a078c083c2
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2781195
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-11-09 11:18:39 -08:00
Narayan Reddy
f816ebf1e8 osi: core: fix misra 4.6 rule 
===== DIFF ======
Total misra violation count changed by -240
Rule: MISRA_C-2012_Directive_4.6 Diff: -240
Rule: Total Diff: -240

Bug 3695218

Change-Id: Ida2d3a775872637eda3058ea361a00346c86f7f7
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2767895
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-08-30 00:05:29 -07:00
Bhadram Varka
8592447094 osi: Pass OSD pointer for better logging 
Issue: Currently logs don't have any IP/inteface specific
name to indicate that from which IP/interface these
logs are coming.

Fix: Pass OSD pointer so that interface or device name
can be added to the logs.

Reduce XPCS logging

Bug 3719492
Bug 3722532

Change-Id: Id909b14f24f441ab40ff6497f1998aeb4ab34611
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2745731
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
 2022-08-20 23:31:07 -07:00
Narayan Reddy
21b6f6aeb9 osi: core: Fix MISRA issues 
Fixed straight forward MISRA issues

===== DIFF ======
Total misra violation count changed by -319
Rule: MISRA_C-2012_Directive_4.4 Diff: -3
Rule: MISRA_C-2012_Directive_4.6 Diff: -32
Rule: MISRA_C-2012_Directive_4.9 Diff: 3
Rule: MISRA_C-2012_Rule_10.1 Diff: -4
Rule: MISRA_C-2012_Rule_10.3 Diff: -2
Rule: MISRA_C-2012_Rule_10.4 Diff: -21
Rule: MISRA_C-2012_Rule_11.1 Diff: -20
Rule: MISRA_C-2012_Rule_12.1 Diff: -74
Rule: MISRA_C-2012_Rule_15.5 Diff: 1
Rule: MISRA_C-2012_Rule_15.7 Diff: -2
Rule: MISRA_C-2012_Rule_16.1 Diff: -1
Rule: MISRA_C-2012_Rule_16.3 Diff: -1
Rule: MISRA_C-2012_Rule_17.7 Diff: -5
Rule: MISRA_C-2012_Rule_2.5 Diff: -157
Rule: MISRA_C-2012_Rule_8.6 Diff: -1
Rule: Total Diff: -319

JIRA NET-96
Bug 3695218

Change-Id: I221f95aaf23e9214fde21632b68425b705552752
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2735077
Reviewed-by: Nagarjuna Kristam <nkristam@nvidia.com>
Reviewed-by: Sanath Kumar Gampa <sgampa@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-07-06 02:37:19 -07:00
Om Prakash Singh
f661fdd189 core: add pcs register readback after write support 
As per T23X-MGBE_HSIv2-14 requirement for PCS register
we need to perform readback for each write operation
to verify write operation was successful

Bug 3606649
Change-Id: I7cca6baa43feaa4207b6158f0abc796e656338dd
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2700845
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
 2022-05-04 23:24:27 -07:00
Om Prakash Singh
de75b86ee1 osi: core: fix XPCS_REG_VALUE_MASK 
Issue: PCS register read/write is failing due to wrong value of
 XPCS_REG_VALUE_MASK;

Fix: update XPCS_REG_VALUE_MASK value to 0x3FF

Bug 3591736

Change-Id: Id62aff5f8749b94810475ff79665899a10bec3e4
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2701996
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-25 18:37:21 -07:00
Om Prakash Singh
65f78eba09 osi: core: add support for HSI 
1) Add OSI IOCTL to enable HSI feature at runtime
2) Enable LIC interrupt for Correctable, Uncorrectable and
   Parity error
3) Program register to enable safety feature

Bug 3543410

Change-Id: I8a9f33bab72eb37e8aa64c16c610be6e5271c7f8
Signed-off-by: Om Prakash Singh <omp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2670989
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Ashutosh Jha <ajha@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2022-04-09 16:26:37 -07:00
Narayan Reddy
b9be4579b7 osi: core: Enable Transparent Tx LPI Mode 
In this mode, the transmit LPI state-machine
does not move to TX_QUIET state. On detecting Lower-Power Idle
on XGMII/GMII Tx interface, xpcs goes to the TX_SLEEP state and
remains in this state till MAC stops sending LPI.

Bug 200764486

Change-Id: I376ac481e880472d7a11b60931a90d6f9c7a0067
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2598380
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-24 12:31:56 -07:00
Bhadram Varka
dbaf1ac0ba osi: xpcs: Fix Tx lane bring-up failure 
Issue:
During Tx lane bring up power up will fail if
the lane is already powered up.

Fix:
Don't bring-up Tx lane if its already powered up.

Bug 200766119
Bug 200764018

Change-Id: Idbdffdca7b9c9cccd8b8876fcfe8ea7448a7ed10
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2597604
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-09-21 07:51:42 -07:00
Narayan Reddy
b943ccf5da osi: core: xpcs: modify lane bringup sequence 
Issue: there is a PHY reset(RX_PCS_PHY_RDY) programming
in Rx sequence that was disabling the Tx path from MGBE PCS

Fix: Control entire programming sequence from SW and
by pass HW FSM

Bug 3359851
Bug 200765222

Change-Id: Iffd00d1dff00204e36eb3a14b19c07dcd3a502b8
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2584394
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-08-28 02:47:23 -07:00
Bhadram Varka
f3a6500aa8 osi: xpcs: support for Tx/Rx lane bring-up 
Below is per Lane bring-up sequence as per IAS

SW should trigger per lane bring up sequence as follows.
o Set PCS_WRAP_UPHY_HW_INIT_CONTROL_0_0. HW_TX_INIT_EN = 1
o Set PCS_WRAP_UPHY_HW_INIT_CONTROL_0_0. HW_RX_INIT_EN = 1
o Wait for HW_TX_INIT_EN = 0
o Wait for HW_RX_INIT_EN = 0
o Check PCS Lock status by reading the status bit
  “PCS_WRAP_INTERRUPT_STATUS_0.PCS_LINK_STS”

This change implements above sequence.

Above sequence not required for pre-silicon platforms
because NvUPHY is not available.

Bug 200740702

Change-Id: I40415e25bc6ded9a1692a381399105487a306efc
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2543048
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: svc_kernel_abi <svc_kernel_abi@nvidia.com>
Reviewed-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Krishna Thota <kthota@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
 2021-06-26 20:50:53 -07:00
Bhadram Varka
cd1ab63241 osi: update XPCS speed based UPHY GBE mode 
Bug 3288030

Change-Id: Ic33774fce09d1d426d107a8c4bfa883e9a576f6e
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2531231
Reviewed-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
 2021-06-21 07:07:10 +05:30
Narayan Reddy
45ad4bb765 nvethernetrm: Add support for EEE LPI 
Add an API to configure the EEE LPI mode.
Tx LPI is enabled with a default entry time of 1sec.
The MAC controller has capability to automatically
enter LPI mode when all transmissions are complete.

Bug 200565917

Change-Id: I59b5eccc83770bc7dff9dadb192b733e0d01d7dd
Signed-off-by: Narayan Reddy <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2274444
Tested-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-by: automaticguardword <automaticguardword@nvidia.com>
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2021-04-05 16:35:54 +05:30
narayanr
17836af9ec nvethernetrm: mgbe: fix doxygen comments 
Bug 200598918

Change-Id: I230c16d83070356efc8560b26a238db7927e7adf
Signed-off-by: narayanr <narayanr@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2314668
Reviewed-by: Bhadram Varka <vbhadram@nvidia.com>
 2021-04-05 16:35:54 +05:30
Bhadram Varka
95f86be943 nvethernetrm: xpcs: XPCS initialization 
Add support for XPCS initialization in USXMII mode
and start of XPCS will happen once speed set for MAC.

Bug 200552796

Change-Id: I4c98bec2e92d9b189c7d2404705e28b969592f33
Signed-off-by: Bhadram Varka <vbhadram@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2258482
 2021-04-05 16:35:53 +05:30