HSB does not use proper seq. num currently. Every
SOF is supposed to start with seq 0 in COE header. BUt HSB
preserves last value incorrectly. This is resulting in
frame errors being reported by macsec.
Till HSB FPGA can be updated, disable seq. check for GTC.
JIRA CT26X-1895
Change-Id: I654fbe6faab187ea416b38d01c30694ce1df0ee2
Signed-off-by: Srinivas Ramachandran <srinivasra@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/3305644