Rakesh Goyal 288c525a36 nvethenetrm: core: SW WAR implementation for switching of Gates ...

Issue: switching of Gates did not happen for
intermediate cycles when CTR is
less than GCL execution time

Fix: SW WAR as per recommendation.
1) At the programming time make sure
  (CTR - total TI) should be 0 or more than
  8PTP clock time.
2) Switching to New List
   check for following
   Old BTR + n(CTR) - New GCL list's BTR >= 8PTP or
   New GCL list's BTR – (Old BTR + n(CTR)) >= 8PTP

Bug 200724911

Change-Id: I19127a134655a66bb66d025f964b85afc6c23c2e
Signed-off-by: Rakesh Goyal <rgoyal@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/kernel/nvethernetrm/+/2622942
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>

2022-02-28 10:49:29 -08:00

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