mirror of
git://nv-tegra.nvidia.com/tegra/nv-sci-src/nvsci_headers.git
synced 2025-12-22 09:23:12 +03:00
682247f4b2
d0ddab94c11685c63a68694bed69f02c951c170b - nvscievent.h e91fc7a9c1daab4c34970804792b70df556ee9f8 - nvsciipc.cfg 211f46a8c41805aff5142c3552fec95ce72c7d03 - nvscisync.h c2219e53c743c6453b1a54ffec54bfce9907b571 - nvscistream_api.h 6b8809ed1b39dcb64c4da2f34ffee2aec10bb0b1 - nvscistream.h af012d853fbe7ddf90af9cb1b8bd136948b7bb58 - nvsciipc.h 60df71827224ad5951cf42d18b8005ad6f9a0399 - nvscistream_types.h 90b2d50de948c0f2486fcfae0833370ea8a2d03f - nvscierror.h ed288ef2d308f39dc4a10efde8c5041db138a145 - nvscibuf.h Change-Id: Ic9396219e0bd9650d84660e9fa0de58c1dd29297
81 lines
3.7 KiB
INI
81 lines
3.7 KiB
INI
#
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# Copyright (c) 2019-2022, NVIDIA CORPORATION. All rights reserved.
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#
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# Format of NvSciIpc Config file
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#
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# First column should specify the backend. All possible backend types
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# are listed below:
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# INTER_THREAD, INTER_PROCESS, INTER_VM, INTER_CHIP
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#
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# For INTER_THREAD/PROCESS backend type, format will be:
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# <backend_type> <endpoint1_name> <endpoint2_name> <backend_info1> <backend_info2>
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#
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# For INTER_THREAD and INTER_PROCESS, two endpoints name should be different.
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# You can use different suffix with basename for them. <backend_info1> denotes
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# "number of frames" and <backend_info2> denotes "frame size"
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#
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# For INTER_VM/CHIP backend type, format will be:
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# <backend_type> <endpoint_name> <backend_info1>
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#
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# For INTER_CHIP optional backend info is derive with below rule:
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# <xfer_role><device_id>
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# Both should be written as two digit decimal number.
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# eg: device_id = 5, xfer_role = producer
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# backend info: 0105
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#
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# For INTER_VM backend type, BACKEND_INFO1 denotes ivc queue number
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#
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# This is NvSciIpc CFG file for x86 machine, so only 3 backends are supported
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# as of now : INTER_PROCESS, INTER_THREAD and INTER_CHIP
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INTER_PROCESS ipc_test_0 ipc_test_1 64 1536
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INTER_PROCESS ipc_test_a_0 ipc_test_a_1 64 1536
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INTER_PROCESS ipc_test_b_0 ipc_test_b_1 64 1536
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INTER_PROCESS ipc_test_c_0 ipc_test_c_1 64 1536
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INTER_THREAD itc_test_0 itc_test_1 64 1536
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INTER_PROCESS nvscistream_0 nvscistream_1 16 24576
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INTER_PROCESS nvscistream_2 nvscistream_3 16 24576
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INTER_PROCESS nvscistream_4 nvscistream_5 16 24576
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INTER_PROCESS nvscistream_6 nvscistream_7 16 24576
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INTER_PROCESS nvscisync_a_0 nvscisync_a_1 16 24576
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INTER_PROCESS nvscisync_b_0 nvscisync_b_1 16 24576
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INTER_PROCESS nvscisync_c_0 nvscisync_c_1 16 24576
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INTER_PROCESS nvscisync_d_0 nvscisync_d_1 16 24576
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INTER_PROCESS nvscibuf_ipc_A_B nvscibuf_ipc_B_A 16 24576
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INTER_PROCESS nvscibuf_ipc_B_C nvscibuf_ipc_C_B 16 24576
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INTER_PROCESS nvscibuf_ipc_A_D nvscibuf_ipc_D_A 16 24576
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INTER_PROCESS nvscibuf_ipc_B_E nvscibuf_ipc_E_B 16 24576
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INTER_PROCESS nvmap_sciipc_1 nvmap_sciipc_2 16 24576
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INTER_PROCESS nvmap_sciipc_3 nvmap_sciipc_4 16 24576
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INTER_CHIP nvscic2c_pcie_s0_c5_1 0000
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INTER_CHIP nvscic2c_pcie_s0_c5_2 0000
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INTER_CHIP nvscic2c_pcie_s0_c5_3 0000
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INTER_CHIP nvscic2c_pcie_s0_c5_4 0000
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INTER_CHIP nvscic2c_pcie_s0_c5_5 0000
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INTER_CHIP nvscic2c_pcie_s0_c5_6 0000
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INTER_CHIP nvscic2c_pcie_s0_c5_7 0000
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INTER_CHIP nvscic2c_pcie_s0_c5_8 0000
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INTER_CHIP nvscic2c_pcie_s0_c5_9 0000
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INTER_CHIP nvscic2c_pcie_s0_c5_10 0000
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INTER_CHIP nvscic2c_pcie_s0_c5_11 0000
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INTER_CHIP nvscic2c_pcie_s0_c6_1 0000
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INTER_CHIP nvscic2c_pcie_s0_c6_2 0000
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INTER_CHIP nvscic2c_pcie_s0_c6_3 0000
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INTER_CHIP nvscic2c_pcie_s0_c6_4 0000
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INTER_CHIP nvscic2c_pcie_s0_c6_5 0000
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INTER_CHIP nvscic2c_pcie_s0_c6_6 0000
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INTER_CHIP nvscic2c_pcie_s0_c6_7 0000
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INTER_CHIP nvscic2c_pcie_s0_c6_8 0000
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INTER_CHIP nvscic2c_pcie_s0_c6_9 0000
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INTER_CHIP nvscic2c_pcie_s0_c6_10 0000
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INTER_CHIP nvscic2c_pcie_s0_c6_11 0000
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INTER_CHIP egl_nvscic2c_5_prod 0105
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INTER_CHIP egl_nvscic2c_5_cons 1005
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INTER_CHIP egl_nvscic2c_6_prod 0106
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INTER_CHIP egl_nvscic2c_6_cons 1006
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INTER_CHIP egl_nvscic2c_7_prod 0107
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INTER_CHIP egl_nvscic2c_7_cons 1007
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INTER_CHIP egl_nvscic2c_8_prod 0108
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INTER_CHIP egl_nvscic2c_8_cons 1008
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INTER_CHIP egl_nvscic2c_9_prod 0109
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INTER_CHIP egl_nvscic2c_9_cons 1009
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