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[UPSTREAM v6.5]: arm64: tegra: Add Tegra234 thermal support

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Add device tree node for the BPMP thermal node on Tegra234 and add
thermal zone definitions.

Cherry picked from commit 09d990782a243b97eb566717a2155a306a2f42af

Bug 3960800
Bug 4035713
Bug 4204722

Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Yi-Wei Wang <yiweiw@nvidia.com>
Change-Id: Ifef49687ef550cbdcdf26a511a69b1e46502b376
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/2941394
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Yi-Wei Wang
2023-07-24 18:44:55 +08:00
committed by mobile promotions
parent cf3129d52e
commit 0038ca5d15
2 changed files with 72 additions and 0 deletions
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19
include/kernel/dt-bindings/thermal/tegra234-bpmp-thermal.h Normal file
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@@ -0,0 +1,19 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This header provides constants for binding nvidia,tegra234-bpmp-thermal.
*/
#ifndef _DT_BINDINGS_THERMAL_TEGRA234_BPMP_THERMAL_H
#define _DT_BINDINGS_THERMAL_TEGRA234_BPMP_THERMAL_H
#define TEGRA234_BPMP_THERMAL_ZONE_CPU 0
#define TEGRA234_BPMP_THERMAL_ZONE_GPU 1
#define TEGRA234_BPMP_THERMAL_ZONE_CV0 2
#define TEGRA234_BPMP_THERMAL_ZONE_CV1 3
#define TEGRA234_BPMP_THERMAL_ZONE_CV2 4
#define TEGRA234_BPMP_THERMAL_ZONE_SOC0 5
#define TEGRA234_BPMP_THERMAL_ZONE_SOC1 6
#define TEGRA234_BPMP_THERMAL_ZONE_SOC2 7
#define TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX 8
#endif

53
tegra234.dtsi
View File

@@ -8,6 +8,7 @@
#include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
#include <dt-bindings/power/tegra234-powergate.h>
#include <dt-bindings/reset/tegra234-reset.h>
#include <dt-bindings/thermal/tegra234-bpmp-thermal.h>
/ {
compatible = "nvidia,tegra234";
@@ -2999,6 +3000,11 @@
#address-cells = <1>;
#size-cells = <0>;
};
bpmp_thermal: thermal {
compatible = "nvidia,tegra186-bpmp-thermal";
#thermal-sensor-cells = <1>;
};
};
cpus {
@@ -3435,6 +3441,53 @@
<&bpmp TEGRA234_CLK_PLLA_OUT0>;
};
thermal-zones {
cpu-thermal {
thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CPU>;
status = "disabled";
};
gpu-thermal {
thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_GPU>;
status = "disabled";
};
cv0-thermal {
thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV0>;
status = "disabled";
};
cv1-thermal {
thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV1>;
status = "disabled";
};
cv2-thermal {
thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_CV2>;
status = "disabled";
};
soc0-thermal {
thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC0>;
status = "disabled";
};
soc1-thermal {
thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC1>;
status = "disabled";
};
soc2-thermal {
thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_SOC2>;
status = "disabled";
};
tj-thermal {
thermal-sensors = <&{/bpmp/thermal} TEGRA234_BPMP_THERMAL_ZONE_TJ_MAX>;
status = "disabled";
};
};
timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,