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dts: qspi: update parent clock and bus width

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Add assigned clock parent and rate properties
in device tree for qspi and update the p3701 bus width
for qspi to 4 instead of 1.

Bug 4739710
Bug 4535595

Change-Id: I32cdc917af9ed6c4bbeb94e27d8b007ba704ca8b
Signed-off-by: Vishwaroop A <va@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3174161
GVS: buildbot_gerritrpt <buildbot_gerritrpt@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
This commit is contained in:
Vishwaroop A
2024-10-02 16:40:28 +00:00
committed by mobile promotions
parent 332e56ee15
commit 1dd7612d8a
2 changed files with 4 additions and 10 deletions
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10
nv-platform/tegra234-p3701-0000.dtsi
View File

@@ -4,16 +4,6 @@
#include "tegra234-p3701-0000-prod-overlay.dtsi"
/ {
bus@0 {
spi@3270000 {
flash@0 {
spi-max-frequency = <51000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <1>;
};
};
};
bpmp {
i2c {
vrs@3c {

4
nv-soc/tegra234-base-overlay.dtsi
View File

@@ -440,6 +440,10 @@
dma-names = "rx", "tx";
dma-coherent;
iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>;
assigned-clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
<&bpmp TEGRA234_CLK_QSPI0_PM>;
assigned-clock-rates = <199999999 99999999>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>;
};
hardware-timestamp@3aa0000 {