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DT: nvidia: add camera dtsi and dependencies
Add camera DT overlay with camera related nodes Change-Id: I38594946027bf973b7cc787393c99a64e01e067d Signed-off-by: Matti Ryttylainen <mryttylainen@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/soc/t23x-generic-dts/+/2811146 Reviewed-by: Ankur Pawar <ankurp@nvidia.com> Reviewed-by: Frank Chen <frankc@nvidia.com> Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com> Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com> GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Ankur Pawar
committed by
Laxman Dewangan
Laxman Dewangan
parent
208e45479f
commit
562ce6ff71
258
overlay/tegra234-camera.dtsi
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258
overlay/tegra234-camera.dtsi
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// SPDX-License-Identifier: GPL-2.0
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// Copyright (c) 2022, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
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/*
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* tegra234-camera.dtsi: Camera RTCPU DTSI file.
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*/
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#include <dt-bindings/soc/nvidia,tegra186-hsp.h>
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#include <dt-bindings/interrupt/tegra234-irq.h>
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#include <dt-bindings/memory/tegra234-smmu-streamid.h>
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#include <dt-bindings/clock/tegra234-clock-oot.h>
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#include <dt-bindings/reset/tegra234-reset-oot.h>
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#include <dt-bindings/soc/tegra234-powergate.h>
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/ {
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fragment-camera@0 {
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target-path = "/";
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__overlay__ {
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aliases { /* RCE is the Camera RTCPU */
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tegra-camera-rtcpu = "/rtcpu@bc00000";
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};
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tegra_rce: rtcpu@bc00000 {
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compatible = "nvidia,tegra194-rce";
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nvidia,cpu-name = "rce";
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reg = <0 0xbc00000 0 0x1000>, /* RCE EVP (RCE_ATCM_EVP) */
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<0 0xb9f0000 0 0x40000>, /* RCE PM */
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<0 0xb840000 0 0x10000>,
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<0 0xb850000 0 0x10000>;
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reg-names = "rce-evp", "rce-pm",
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"ast-cpu", "ast-dma";
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clocks =
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<&bpmp TEGRA234_CLK_RCE_CPU_NIC>,
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<&bpmp TEGRA234_CLK_RCE_NIC>,
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<&bpmp TEGRA234_CLK_RCE_CPU>;
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clock-names = "rce-cpu-nic", "rce-nic", "rce-cpu";
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nvidia,clock-rates =
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<115200000 601600000>,
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<115200000 601600000>,
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<115200000 601600000>;
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resets = <&bpmp TEGRA234_RESET_RCE_ALL>;
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reset-names = "rce-all";
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interrupts = <GIC_SPI TEGRA234_IRQ_RCE_WDT_REMOTE IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "wdt-remote";
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iommus = <&smmu_niso0 TEGRA234_SID_RCE>;
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iommu-resv-regions = <0x0 0x0 0x0 0xA0000000 0x0 0xc0000000 0xffffffff 0xffffffff>;
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dma-coherent;
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/* Memory bandwidth in kB/s during boot */
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nvidia,test-bw = <2400000>;
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nvidia,trace = <&rtcpu_trace 4 0x70100000 0x100000>;
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nvidia,ivc-channels = <&camera_ivc_channels 2 0x90000000 0x10000>;
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nvidia,autosuspend-delay-ms = <5000>;
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status = "okay";
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hsp-vm1 {
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compatible = "nvidia,tegra-camrtc-hsp-vm";
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mboxes =
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<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(0)>,
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<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(1)>,
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<&hsp_rce TEGRA_HSP_MBOX_TYPE_SS 0>;
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mbox-names = "vm-tx", "vm-rx", "vm-ss";
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status = "okay";
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};
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hsp-vm2 {
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compatible = "nvidia,tegra-camrtc-hsp-vm";
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mboxes =
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<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_TX(2)>,
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<&hsp_rce TEGRA_HSP_MBOX_TYPE_SM TEGRA_HSP_SM_RX(3)>,
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<&hsp_rce TEGRA_HSP_MBOX_TYPE_SS 1>;
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mbox-names = "vm-tx", "vm-rx", "vm-ss";
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status = "disabled";
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};
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};
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camera_ivc_channels: camera-ivc-channels {
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echo@0 {
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compatible = "nvidia,tegra186-camera-ivc-protocol-echo";
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nvidia,service = "echo";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <16>;
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nvidia,frame-size = <64>;
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};
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dbg@1 {
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/* This is raw channel exposed as device */
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compatible = "nvidia,tegra186-camera-ivc-protocol-dbg";
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nvidia,service = "debug";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <1>;
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nvidia,frame-size = <448>;
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};
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dbg@2 {
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/* This is exposed in debugfs */
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compatible = "nvidia,tegra186-camera-ivc-protocol-debug";
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nvidia,service = "debug";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <1>;
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nvidia,frame-size = <8192>;
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nvidia,ivc-timeout = <50>;
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nvidia,test-timeout = <5000>;
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nvidia,mem-map = <&tegra_rce &vi0 &isp &vi1>;
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/* Memory bandwidth in kB/s during tests */
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nvidia,test-bw = <2400000>;
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};
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ivccontrol@3 {
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compatible = "nvidia,tegra186-camera-ivc-protocol-capture-control";
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nvidia,service = "capture-control";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <64>;
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nvidia,frame-size = <320>;
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};
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ivccapture@4 {
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compatible = "nvidia,tegra186-camera-ivc-protocol-capture";
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nvidia,service = "capture";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <512>;
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nvidia,frame-size = <64>;
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};
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diag@5 {
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compatible = "nvidia,tegra186-camera-diagnostics";
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nvidia,service = "diag";
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nvidia,version = <0>;
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nvidia,group = <1>;
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nvidia,frame-count = <1>;
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nvidia,frame-size = <64>;
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};
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};
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rtcpu_trace: tegra-rtcpu-trace {
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nvidia,enable-printk;
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nvidia,interval-ms = <50>;
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nvidia,log-prefix = "[RCE]";
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};
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capture_vi: tegra-capture-vi {
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compatible = "nvidia,tegra-camrtc-capture-vi";
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nvidia,vi-devices = <&vi0 &vi1>;
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nvidia,vi-mapping-size = <6>;
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nvidia,vi-mapping =
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<0 0>,
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<1 0>,
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<2 1>,
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<3 1>,
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<4 0>,
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<5 1>;
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nvidia,vi-mapping-names = "csi-stream-id", "vi-unit-id";
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nvidia,vi-max-channels = <72>;
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};
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reserved-memory {
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camdbg_reserved: camdbg_carveout {
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compatible = "nvidia,camdbg_carveout";
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size = <0 0x6400000>;
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alignment = <0 0x100000>;
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alloc-ranges = <0x1 0 0x1 0>;
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status = "disabled";
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};
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};
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};
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};
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fragment-camera@1 {
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target-path = "/bus@0";
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__overlay__ {
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host1x@13e00000 {
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vi0: vi0@15c00000 {
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compatible = "nvidia,tegra234-vi";
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clocks = <&bpmp TEGRA234_CLK_VI>;
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clock-names = "vi";
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nvidia,vi-falcon-device = <&vi0_thi>;
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resets = <&bpmp TEGRA234_RESET_VI>;
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reset-names = "vi0";
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iommus = <&smmu_iso TEGRA_SID_ISO_VI>;
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non-coherent;
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status = "okay";
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};
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vi0_thi: vi0-thi@15f00000 {
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compatible = "nvidia,tegra234-vi-thi";
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resets = <&bpmp TEGRA234_RESET_VI>;
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reset-names = "vi0_thi";
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status = "okay";
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};
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vi1: vi1@14c00000 {
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compatible = "nvidia,tegra234-vi";
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clocks = <&bpmp TEGRA234_CLK_VI>;
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clock-names = "vi";
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nvidia,vi-falcon-device = <&vi1_thi>;
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resets = <&bpmp TEGRA234_RESET_VI2>;
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reset-names = "vi1";
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iommus = <&smmu_iso TEGRA234_SID_ISO_VI2>;
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non-coherent;
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status = "okay";
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};
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vi1_thi: vi1-thi@14f00000 {
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compatible = "nvidia,tegra234-vi-thi";
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resets = <&bpmp TEGRA234_RESET_VI2>;
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reset-names = "vi1_thi";
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status = "okay";
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};
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isp: isp@14800000 {
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compatible = "nvidia,tegra194-isp";
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reg = <0x14800000 0x00010000>;
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resets = <&bpmp TEGRA234_RESET_ISP>;
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reset-names = "isp";
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clocks = <&bpmp TEGRA234_CLK_ISP>;
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clock-names = "isp";
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power-domains = <&bpmp TEGRA234_POWER_DOMAIN_ISPA>;
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nvidia,isp-falcon-device = <&isp_thi>;
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iommus = <&smmu_niso1 TEGRA234_SID_ISP>;
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dma-coherent;
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status = "okay";
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};
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isp_thi: isp-thi@14b00000 {
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compatible = "nvidia,tegra194-isp-thi";
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resets = <&bpmp TEGRA234_RESET_ISP>;
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iommus = <&smmu_niso1 TEGRA234_SID_ISP>;
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dma-coherent;
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status = "okay";
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};
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nvcsi: nvcsi@15a00000 {
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compatible = "nvidia,tegra194-nvcsi";
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resets = <&bpmp TEGRA234_RESET_NVCSI>;
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reset-names = "nvcsi";
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clocks = <&bpmp TEGRA234_CLK_NVCSI>;
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clock-names = "nvcsi";
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status = "okay";
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};
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};
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};
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};
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};
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