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t23x: Add Hawk & Owl overlays for P3762

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Add following overlays for Hawk+Owl
1xHAWK: tegra234-p3737-camera-p3762-a00-1Hawk-overlay.dtbo
2xHAWK: tegra234-p3737-camera-p3762-a00-2Hawk-overlay.dtbo
3xHAWK+3xOWL: tegra234-p3737-camera-p3762-a00-3Hawk-3Owl-overlay.dtbo
4xHAWK: tegra234-p3737-camera-p3762-a00-4Hawk-overlay.dtbo
4xOWL: tegra234-p3737-camera-p3762-a00-4Owl-overlay.dtbo

Bug 4583168

Change-Id: I7d03978628ead5b761668b58e05d6c35553ac52f
Signed-off-by: Ankur Pawar<ankurp@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3109502
(cherry picked from commit e979b90a55)
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3203952
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Ankur Pawar
2024-04-04 13:22:57 +00:00
committed by mobile promotions
parent a80675405f
commit 63f16420ec
9 changed files with 1299 additions and 319 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
overlay/Makefile
View File

@@ -58,6 +58,11 @@ dtbo-y += tegra234-p3737-camera-eCAM130A-overlay.dtbo
dtbo-y += tegra234-p3737-camera-dual-hawk-ar0234-e3653-overlay.dtbo dtbo-y += tegra234-p3737-camera-dual-hawk-ar0234-e3653-overlay.dtbo
dtbo-y += tegra234-p3737-camera-imx390-addr-0x21-overlay.dtbo dtbo-y += tegra234-p3737-camera-imx390-addr-0x21-overlay.dtbo
dtbo-y += tegra234-p3737-camera-imx390-overlay.dtbo dtbo-y += tegra234-p3737-camera-imx390-overlay.dtbo
dtbo-y += tegra234-p3737-camera-p3762-a00-1Hawk-overlay.dtbo
dtbo-y += tegra234-p3737-camera-p3762-a00-2Hawk-overlay.dtbo
dtbo-y += tegra234-p3737-camera-p3762-a00-3Hawk-3Owl-overlay.dtbo
dtbo-y += tegra234-p3737-camera-p3762-a00-4Hawk-overlay.dtbo
dtbo-y += tegra234-p3737-camera-p3762-a00-4Owl-overlay.dtbo
dtbo-y += tegra234-p3767-camera-p3768-imx219-C.dtbo dtbo-y += tegra234-p3767-camera-p3768-imx219-C.dtbo
dtbo-y += tegra234-p3767-camera-p3768-imx219-A.dtbo dtbo-y += tegra234-p3767-camera-p3768-imx219-A.dtbo
dtbo-y += tegra234-p3767-camera-p3768-imx219-imx477.dtbo dtbo-y += tegra234-p3767-camera-p3768-imx219-imx477.dtbo

175
overlay/tegra234-p3737-camera-p3762-a00-1Hawk-overlay.dts Normal file
View File

@@ -0,0 +1,175 @@
// SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/dts-v1/;
/plugin/;
#include "tegra234-p3737-camera-p3762-a00.dtsi"
#include "dt-bindings/gpio/tegra234-gpio.h"
#include "dt-bindings/clock/tegra234-clock.h"
#include <dt-bindings/tegra234-p3737-0000+p3701-0000.h>
/* camera control gpio definitions */
#define CAM0_RST_L TEGRA234_MAIN_GPIO(H, 3)
#define CAM0_PWDN TEGRA234_MAIN_GPIO(H, 6)
#define CAM1_RST_L TEGRA234_MAIN_GPIO(AC, 1)
#define CAM1_PWDN TEGRA234_MAIN_GPIO(AC, 0)
#define PWR_EN TEGRA234_MAIN_GPIO(AC, 7)
#define GYRO1_IRQ_GPIO TEGRA234_AON_GPIO(CC, 1)
#define ACCE1_IRQ_GPIO TEGRA234_AON_GPIO(CC, 0)
/ {
overlay-name = "Jetson Camera 1-Hawk p3762 module";
jetson-header-name = "Jetson AGX CSI Connector";
compatible = JETSON_COMPATIBLE;
fragment-camera-hawk-owl@0 {
target-path = "/";
__overlay__ {
tegra-capture-vi {
num-channels = <2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
status = "okay";
};
port@1 {
status = "okay";
};
port@2 {
status = "disabled";
};
port@3 {
status = "disabled";
};
port@4 {
status = "disabled";
};
port@5 {
status = "disabled";
};
port@6 {
status = "disabled";
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
port@9 {
status = "disabled";
};
port@10 {
status = "disabled";
};
port@11 {
status = "disabled";
};
};
};
bus@0 {
host1x@13e00000 {
nvcsi@15a00000 {
num-channels = <2>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
status = "okay";
};
channel@1 {
status = "okay";
};
channel@2 {
status = "disabled";
};
channel@3 {
status = "disabled";
};
channel@4 {
status = "disabled";
};
channel@5 {
status = "disabled";
};
channel@6 {
status = "disabled";
};
channel@7 {
status = "disabled";
};
channel@8 {
status = "disabled";
};
channel@9 {
status = "disabled";
};
channel@10 {
status = "disabled";
};
channel@11 {
status = "disabled";
};
};
};
i2c@3180000 {
max96712_b@62 {
status = "disabled";
};
ar0234_i@30 {
status = "disabled";
};
ar0234_j@32 {
status = "disabled";
};
ar0234_k@34 {
status = "disabled";
};
ar0234_l@36 {
status = "disabled";
};
};
i2c@31e0000 {
max96712_a@62 {
status = "okay";
};
virtual_i2c_mux@50 {
status = "okay";
i2c@0 {
bmi088_a@69 {
status = "okay";
};
ar0234_a@30 {
status = "okay";
};
ar0234_b@31 {
status = "okay";
};
};
i2c@1 {
ar0234_c@32 {
status = "disabled";
};
ar0234_d@33 {
status = "disabled";
};
ar0234_e@34 {
status = "disabled";
};
ar0234_f@35 {
status = "disabled";
};
ar0234_g@36 {
status = "disabled";
};
ar0234_h@37 {
status = "disabled";
};
};
};
};
};
};
};
};

175
overlay/tegra234-p3737-camera-p3762-a00-2Hawk-overlay.dts Normal file
View File

@@ -0,0 +1,175 @@
// SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/dts-v1/;
/plugin/;
#include "tegra234-p3737-camera-p3762-a00.dtsi"
#include "dt-bindings/gpio/tegra234-gpio.h"
#include "dt-bindings/clock/tegra234-clock.h"
#include <dt-bindings/tegra234-p3737-0000+p3701-0000.h>
/* camera control gpio definitions */
#define CAM0_RST_L TEGRA234_MAIN_GPIO(H, 3)
#define CAM0_PWDN TEGRA234_MAIN_GPIO(H, 6)
#define CAM1_RST_L TEGRA234_MAIN_GPIO(AC, 1)
#define CAM1_PWDN TEGRA234_MAIN_GPIO(AC, 0)
#define PWR_EN TEGRA234_MAIN_GPIO(AC, 7)
#define GYRO1_IRQ_GPIO TEGRA234_AON_GPIO(CC, 1)
#define ACCE1_IRQ_GPIO TEGRA234_AON_GPIO(CC, 0)
/ {
overlay-name = "Jetson Camera 2-Hawk p3762 module";
jetson-header-name = "Jetson AGX CSI Connector";
compatible = JETSON_COMPATIBLE;
fragment-camera-hawk-owl@0 {
target-path = "/";
__overlay__ {
tegra-capture-vi {
num-channels = <4>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
status = "okay";
};
port@1 {
status = "okay";
};
port@2 {
status = "okay";
};
port@3 {
status = "okay";
};
port@4 {
status = "disabled";
};
port@5 {
status = "disabled";
};
port@6 {
status = "disabled";
};
port@7 {
status = "disabled";
};
port@8 {
status = "disabled";
};
port@9 {
status = "disabled";
};
port@10 {
status = "disabled";
};
port@11 {
status = "disabled";
};
};
};
bus@0 {
host1x@13e00000 {
nvcsi@15a00000 {
num-channels = <4>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
status = "okay";
};
channel@1 {
status = "okay";
};
channel@2 {
status = "okay";
};
channel@3 {
status = "okay";
};
channel@4 {
status = "disabled";
};
channel@5 {
status = "disabled";
};
channel@6 {
status = "disabled";
};
channel@7 {
status = "disabled";
};
channel@8 {
status = "disabled";
};
channel@9 {
status = "disabled";
};
channel@10 {
status = "disabled";
};
channel@11 {
status = "disabled";
};
};
};
i2c@3180000 {
max96712_b@62 {
status = "disabled";
};
ar0234_i@30 {
status = "disabled";
};
ar0234_j@32 {
status = "disabled";
};
ar0234_k@34 {
status = "disabled";
};
ar0234_l@36 {
status = "disabled";
};
};
i2c@31e0000 {
max96712_a@62 {
status = "okay";
};
virtual_i2c_mux@50 {
status = "okay";
i2c@0 {
bmi088_a@69 {
status = "okay";
};
ar0234_a@30 {
status = "okay";
};
ar0234_b@31 {
status = "okay";
};
};
i2c@1 {
ar0234_c@32 {
status = "okay";
};
ar0234_d@33 {
status = "okay";
};
ar0234_e@34 {
status = "disabled";
};
ar0234_f@35 {
status = "disabled";
};
ar0234_g@36 {
status = "disabled";
};
ar0234_h@37 {
status = "disabled";
};
};
};
};
};
};
};
};

176
overlay/tegra234-p3737-camera-p3762-a00-3Hawk-3Owl-overlay.dts Normal file
View File

@@ -0,0 +1,176 @@
// SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/dts-v1/;
/plugin/;
#include "tegra234-p3737-camera-p3762-a00.dtsi"
#include "dt-bindings/gpio/tegra234-gpio.h"
#include "dt-bindings/clock/tegra234-clock.h"
#include <dt-bindings/tegra234-p3737-0000+p3701-0000.h>
/* camera control gpio definitions */
#define CAM0_RST_L TEGRA234_MAIN_GPIO(H, 3)
#define CAM0_PWDN TEGRA234_MAIN_GPIO(H, 6)
#define CAM1_RST_L TEGRA234_MAIN_GPIO(AC, 1)
#define CAM1_PWDN TEGRA234_MAIN_GPIO(AC, 0)
#define PWR_EN TEGRA234_MAIN_GPIO(AC, 7)
#define GYRO1_IRQ_GPIO TEGRA234_AON_GPIO(CC, 1)
#define ACCE1_IRQ_GPIO TEGRA234_AON_GPIO(CC, 0)
/ {
overlay-name = "Jetson Camera 3-Hawk 3-Owl p3762 module";
jetson-header-name = "Jetson AGX CSI Connector";
compatible = JETSON_COMPATIBLE;
fragment-camera-hawk-owl@0 {
target-path = "/";
__overlay__ {
tegra-capture-vi {
num-channels = <12>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
status = "okay";
};
port@1 {
status = "okay";
};
port@2 {
status = "okay";
};
port@3 {
status = "okay";
};
port@4 {
status = "okay";
};
port@5 {
status = "okay";
};
port@6 {
status = "disabled";
};
port@7 {
status = "disabled";
};
port@8 {
status = "okay";
};
port@9 {
status = "okay";
};
port@10 {
status = "okay";
};
port@11 {
status = "disabled";
};
};
};
bus@0 {
host1x@13e00000 {
nvcsi@15a00000 {
num-channels = <12>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
status = "okay";
};
channel@1 {
status = "okay";
};
channel@2 {
status = "okay";
};
channel@3 {
status = "okay";
};
channel@4 {
status = "okay";
};
channel@5 {
status = "okay";
};
channel@6 {
status = "disabled";
};
channel@7 {
status = "disabled";
};
channel@8 {
status = "okay";
};
channel@9 {
status = "okay";
};
channel@10 {
status = "okay";
};
channel@11 {
status = "disabled";
};
};
};
i2c@3180000 {
max96712_b@62 {
status = "okay";
};
ar0234_i@30 {
status = "okay";
};
ar0234_j@32 {
status = "okay";
};
ar0234_k@34 {
status = "okay";
};
ar0234_l@36 {
status = "disabled";
};
};
i2c@31e0000 {
max96712_a@62 {
status = "okay";
};
virtual_i2c_mux@50 {
status = "okay";
i2c@0 {
bmi088_a@69 {
status = "okay";
};
ar0234_a@30 {
status = "okay";
};
ar0234_b@31 {
status = "okay";
};
};
i2c@1 {
ar0234_c@32 {
status = "okay";
};
ar0234_d@33 {
status = "okay";
};
ar0234_e@34 {
status = "okay";
};
ar0234_f@35 {
status = "okay";
};
ar0234_g@36 {
status = "disabled";
};
ar0234_h@37 {
status = "disabled";
};
};
};
};
};
};
};
};

175
overlay/tegra234-p3737-camera-p3762-a00-4Hawk-overlay.dts Normal file
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@@ -0,0 +1,175 @@
// SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/dts-v1/;
/plugin/;
#include "tegra234-p3737-camera-p3762-a00.dtsi"
#include "dt-bindings/gpio/tegra234-gpio.h"
#include "dt-bindings/clock/tegra234-clock.h"
#include <dt-bindings/tegra234-p3737-0000+p3701-0000.h>
#define CAM0_RST_L TEGRA234_MAIN_GPIO(H, 3)
#define CAM0_PWDN TEGRA234_MAIN_GPIO(H, 6)
#define CAM1_RST_L TEGRA234_MAIN_GPIO(AC, 1)
#define CAM1_PWDN TEGRA234_MAIN_GPIO(AC, 0)
#define PWR_EN TEGRA234_MAIN_GPIO(AC, 7)
#define GYRO1_IRQ_GPIO TEGRA234_AON_GPIO(CC, 1)
#define ACCE1_IRQ_GPIO TEGRA234_AON_GPIO(CC, 0)
/* camera control gpio definitions */
/ {
overlay-name = "Jetson Camera 4-Hawk p3762 module";
jetson-header-name = "Jetson AGX CSI Connector";
compatible = JETSON_COMPATIBLE;
fragment-camera-hawk-owl@0 {
target-path = "/";
__overlay__ {
tegra-capture-vi {
num-channels = <8>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
status = "okay";
};
port@1 {
status = "okay";
};
port@2 {
status = "okay";
};
port@3 {
status = "okay";
};
port@4 {
status = "okay";
};
port@5 {
status = "okay";
};
port@6 {
status = "okay";
};
port@7 {
status = "okay";
};
port@8 {
status = "disabled";
};
port@9 {
status = "disabled";
};
port@10 {
status = "disabled";
};
port@11 {
status = "disabled";
};
};
};
bus@0 {
host1x@13e00000 {
nvcsi@15a00000 {
num-channels = <8>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
status = "okay";
};
channel@1 {
status = "okay";
};
channel@2 {
status = "okay";
};
channel@3 {
status = "okay";
};
channel@4 {
status = "okay";
};
channel@5 {
status = "okay";
};
channel@6 {
status = "okay";
};
channel@7 {
status = "okay";
};
channel@8 {
status = "disabled";
};
channel@9 {
status = "disabled";
};
channel@10 {
status = "disabled";
};
channel@11 {
status = "disabled";
};
};
};
i2c@3180000 {
max96712_b@62 {
status = "disabled";
};
ar0234_i@30 {
status = "disabled";
};
ar0234_j@32 {
status = "disabled";
};
ar0234_k@34 {
status = "disabled";
};
ar0234_l@36 {
status = "disabled";
};
};
i2c@31e0000 {
max96712_a@62 {
status = "okay";
};
virtual_i2c_mux@50 {
status = "okay";
i2c@0 {
bmi088_a@69 {
status = "okay";
};
ar0234_a@30 {
status = "okay";
};
ar0234_b@31 {
status = "okay";
};
};
i2c@1 {
ar0234_c@32 {
status = "okay";
};
ar0234_d@33 {
status = "okay";
};
ar0234_e@34 {
status = "okay";
};
ar0234_f@35 {
status = "okay";
};
ar0234_g@36 {
status = "okay";
};
ar0234_h@37 {
status = "okay";
};
};
};
};
};
};
};
};

176
overlay/tegra234-p3737-camera-p3762-a00-4Owl-overlay.dts Normal file
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@@ -0,0 +1,176 @@
// SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
/dts-v1/;
/plugin/;
#include "tegra234-p3737-camera-p3762-a00.dtsi"
#include "dt-bindings/gpio/tegra234-gpio.h"
#include "dt-bindings/clock/tegra234-clock.h"
#include <dt-bindings/tegra234-p3737-0000+p3701-0000.h>
/* camera control gpio definitions */
#define CAM0_RST_L TEGRA234_MAIN_GPIO(H, 3)
#define CAM0_PWDN TEGRA234_MAIN_GPIO(H, 6)
#define CAM1_RST_L TEGRA234_MAIN_GPIO(AC, 1)
#define CAM1_PWDN TEGRA234_MAIN_GPIO(AC, 0)
#define PWR_EN TEGRA234_MAIN_GPIO(AC, 7)
#define GYRO1_IRQ_GPIO TEGRA234_AON_GPIO(CC, 1)
#define ACCE1_IRQ_GPIO TEGRA234_AON_GPIO(CC, 0)
/ {
overlay-name = "Jetson Camera 4-Owl p3762 module";
jetson-header-name = "Jetson AGX CSI Connector";
compatible = JETSON_COMPATIBLE;
fragment-camera-hawk-owl@0 {
target-path = "/";
__overlay__ {
tegra-capture-vi {
num-channels = <12>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
status = "disabled";
};
port@1 {
status = "disabled";
};
port@2 {
status = "disabled";
};
port@3 {
status = "disabled";
};
port@4 {
status = "disabled";
};
port@5 {
status = "disabled";
};
port@6 {
status = "disabled";
};
port@7 {
status = "disabled";
};
port@8 {
status = "okay";
};
port@9 {
status = "okay";
};
port@10 {
status = "okay";
};
port@11 {
status = "okay";
};
};
};
bus@0 {
host1x@13e00000 {
nvcsi@15a00000 {
num-channels = <12>;
#address-cells = <1>;
#size-cells = <0>;
channel@0 {
status = "disabled";
};
channel@1 {
status = "disabled";
};
channel@2 {
status = "disabled";
};
channel@3 {
status = "disabled";
};
channel@4 {
status = "disabled";
};
channel@5 {
status = "disabled";
};
channel@6 {
status = "disabled";
};
channel@7 {
status = "disabled";
};
channel@8 {
status = "okay";
};
channel@9 {
status = "okay";
};
channel@10 {
status = "okay";
};
channel@11 {
status = "okay";
};
};
};
i2c@3180000 {
max96712_b@62 {
status = "okay";
};
ar0234_i@30 {
status = "okay";
};
ar0234_j@32 {
status = "okay";
};
ar0234_k@34 {
status = "okay";
};
ar0234_l@36 {
status = "okay";
};
};
i2c@31e0000 {
max96712_a@62 {
status = "disabled";
};
virtual_i2c_mux@50 {
status = "disabled";
i2c@0 {
bmi088_a@69 {
status = "disabled";
};
ar0234_a@30 {
status = "disabled";
};
ar0234_b@31 {
status = "disabled";
};
};
i2c@1 {
ar0234_c@32 {
status = "disabled";
};
ar0234_d@33 {
status = "disabled";
};
ar0234_e@34 {
status = "disabled";
};
ar0234_f@35 {
status = "disabled";
};
ar0234_g@36 {
status = "disabled";
};
ar0234_h@37 {
status = "disabled";
};
};
};
};
};
};
};
};

203
overlay/tegra234-p3737-camera-p3762-a00-overlay.dts
View File

@@ -4,7 +4,7 @@
/dts-v1/; /dts-v1/;
/plugin/; /plugin/;
#include "tegra234-camera-p3762-a00.dtsi" #include "tegra234-p3737-camera-p3762-a00.dtsi"
#include "dt-bindings/gpio/tegra234-gpio.h" #include "dt-bindings/gpio/tegra234-gpio.h"
#include "dt-bindings/clock/tegra234-clock.h" #include "dt-bindings/clock/tegra234-clock.h"
#include <dt-bindings/tegra234-p3737-0000+p3701-0000.h> #include <dt-bindings/tegra234-p3737-0000+p3701-0000.h>
@@ -27,112 +27,30 @@
target-path = "/"; target-path = "/";
__overlay__ { __overlay__ {
bus@0 { bus@0 {
/* set camera gpio direction to output */
gpio@2200000 {
camera-control-output-low {
gpio-hog;
output-low;
gpios = <CAM0_RST_L 0 CAM0_PWDN 0
CAM1_RST_L 0 CAM1_PWDN 0>;
label = "cam0-rst", "cam0-pwdn",
"cam1-rst", "cam1-pwdn";
};
};
i2c@3180000 { i2c@3180000 {
max96712_b@62 { max96712_b@62 {
compatible = "nvidia,max96712";
reg = <0x62>;
channel = "b";
pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
}; };
ar0234_i@30 { ar0234_i@30 {
status = "okay"; status = "okay";
def-addr = <0x18>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "b";
has-eeprom;
eeprom-addr = <0x38>;
reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
}; };
ar0234_j@32 { ar0234_j@32 {
status = "okay"; status = "okay";
def-addr = <0x18>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "b";
has-eeprom;
eeprom-addr = <0x3a>;
reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
}; };
ar0234_k@34 { ar0234_k@34 {
status = "okay"; status = "okay";
def-addr = <0x18>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "b";
has-eeprom;
eeprom-addr = <0x3c>;
reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
}; };
ar0234_l@36 { ar0234_l@36 {
status = "okay"; status = "okay";
def-addr = <0x18>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "b";
has-eeprom;
eeprom-addr = <0x3e>;
reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
}; };
}; };
i2c@31e0000 { i2c@31e0000 {
max96712_a@62 { max96712_a@62 {
compatible = "nvidia,max96712";
reg = <0x62>;
channel = "a";
pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
status = "okay"; status = "okay";
}; };
virtual_i2c_mux@50 { virtual_i2c_mux@50 {
reg = <0x50>;
compatible = "nvidia,virtual-i2c-mux";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&dp_aux_ch3_i2c>;
status = "okay"; status = "okay";
i2c@0 { i2c@0 {
reg = <0>;
i2c-mux,deselect-on-exit;
#address-cells = <1>;
#size-cells = <0>;
bmi088_a@69 { bmi088_a@69 {
compatible = "bmi,bmi088"; compatible = "bmi,bmi088";
reg = <0x69>; reg = <0x69>;
@@ -148,137 +66,29 @@
}; };
ar0234_a@30 { ar0234_a@30 {
status = "okay"; status = "okay";
def-addr = <0x10>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "a";
has-eeprom;
eeprom-addr = <0x40>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
}; };
ar0234_b@31 { ar0234_b@31 {
status = "okay"; status = "okay";
def-addr = <0x18>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "a";
has-eeprom;
eeprom-addr = <0x40>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
}; };
}; };
i2c@1 { i2c@1 {
reg = <1>;
i2c-mux,deselect-on-exit;
#address-cells = <1>;
#size-cells = <0>;
ar0234_c@32 { ar0234_c@32 {
status = "okay"; status = "okay";
def-addr = <0x10>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "a";
has-eeprom;
eeprom-addr = <0x15>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
}; };
ar0234_d@33 { ar0234_d@33 {
status = "okay"; status = "okay";
def-addr = <0x18>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "a";
has-eeprom;
eeprom-addr = <0x15>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
}; };
ar0234_e@34 { ar0234_e@34 {
status = "okay"; status = "okay";
def-addr = <0x10>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "a";
has-eeprom;
eeprom-addr = <0x44>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
}; };
ar0234_f@35 { ar0234_f@35 {
status = "okay"; status = "okay";
def-addr = <0x18>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "a";
has-eeprom;
eeprom-addr = <0x44>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
}; };
ar0234_g@36 { ar0234_g@36 {
status = "okay"; status = "okay";
def-addr = <0x10>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "a";
has-eeprom;
eeprom-addr = <0x46>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
}; };
ar0234_h@37 { ar0234_h@37 {
status = "okay"; status = "okay";
def-addr = <0x18>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "a";
has-eeprom;
eeprom-addr = <0x46>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
}; };
}; };
}; };
@@ -286,15 +96,4 @@
}; };
}; };
}; };
fragment-cam-cdi-tsc@0 {
target-path = "/";
__overlay__ {
tsc_sig_gen@c6a0000 {
status = "okay";
generator@380 {
status = "okay";
};
};
};
};
}; };

299
overlay/tegra234-p3737-camera-p3762-a00.dtsi Normal file
View File

@@ -0,0 +1,299 @@
// SPDX-License-Identifier: GPL-2.0-only
// SPDX-FileCopyrightText: Copyright (c) 2024, NVIDIA CORPORATION & AFFILIATES. All rights reserved.
#include "tegra234-camera-p3762-a00.dtsi"
#include "dt-bindings/gpio/tegra234-gpio.h"
#include "dt-bindings/clock/tegra234-clock.h"
#include <dt-bindings/tegra234-p3737-0000+p3701-0000.h>
/* camera control gpio definitions */
#define CAM0_RST_L TEGRA234_MAIN_GPIO(H, 3)
#define CAM0_PWDN TEGRA234_MAIN_GPIO(H, 6)
#define CAM1_RST_L TEGRA234_MAIN_GPIO(AC, 1)
#define CAM1_PWDN TEGRA234_MAIN_GPIO(AC, 0)
#define PWR_EN TEGRA234_MAIN_GPIO(AC, 7)
#define GYRO1_IRQ_GPIO TEGRA234_AON_GPIO(CC, 1)
#define ACCE1_IRQ_GPIO TEGRA234_AON_GPIO(CC, 0)
/ {
fragment-camera-hawk-owl@0 {
target-path = "/";
__overlay__ {
bus@0 {
/* set camera gpio direction to output */
gpio@2200000 {
camera-control-output-low {
gpio-hog;
output-low;
gpios = <CAM0_RST_L 0 CAM0_PWDN 0
CAM1_RST_L 0 CAM1_PWDN 0>;
label = "cam0-rst", "cam0-pwdn",
"cam1-rst", "cam1-pwdn";
};
};
i2c@3180000 {
max96712_b@62 {
compatible = "nvidia,max96712";
reg = <0x62>;
channel = "b";
pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
status = "disabled";
};
ar0234_i@30 {
status = "disabled";
def-addr = <0x18>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "b";
has-eeprom;
eeprom-addr = <0x38>;
reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
};
ar0234_j@32 {
status = "disabled";
def-addr = <0x18>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "b";
has-eeprom;
eeprom-addr = <0x3a>;
reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
};
ar0234_k@34 {
status = "disabled";
def-addr = <0x18>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "b";
has-eeprom;
eeprom-addr = <0x3c>;
reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
};
ar0234_l@36 {
status = "disabled";
def-addr = <0x18>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "b";
has-eeprom;
eeprom-addr = <0x3e>;
reset-gpios = <&gpio CAM1_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM1_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
};
};
i2c@31e0000 {
max96712_a@62 {
compatible = "nvidia,max96712";
reg = <0x62>;
channel = "a";
pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
status = "disabled";
};
virtual_i2c_mux@50 {
reg = <0x50>;
compatible = "nvidia,virtual-i2c-mux";
#address-cells = <1>;
#size-cells = <0>;
i2c-parent = <&dp_aux_ch3_i2c>;
status = "disabled";
i2c@0 {
reg = <0>;
i2c-mux,deselect-on-exit;
#address-cells = <1>;
#size-cells = <0>;
bmi088_a@69 {
compatible = "bmi,bmi088";
reg = <0x69>;
accel_i2c_addr = <0x19>;
/* Old BMI088 driver uses *_gpio property and the latest
* BMI088 driver uses *-gpios property. Have both versions
* to maintain backward compatibility.
*/
accel_irq_gpio = <&gpio_aon ACCE1_IRQ_GPIO GPIO_ACTIVE_HIGH>;
gyro_irq_gpio = <&gpio_aon GYRO1_IRQ_GPIO GPIO_ACTIVE_HIGH>;
accel_irq-gpios = <&gpio_aon ACCE1_IRQ_GPIO GPIO_ACTIVE_HIGH>;
gyro_irq-gpios = <&gpio_aon GYRO1_IRQ_GPIO GPIO_ACTIVE_HIGH>;
accel_matrix = [01 00 00 00 01 00 00 00 01];
gyro_matrix = [01 00 00 00 01 00 00 00 01];
gyro_reg_0x18 = <0x81>;
timestamps = <&hte_aon ACCE1_IRQ_GPIO>, <&hte_aon GYRO1_IRQ_GPIO>;
timestamp-names = "accelerometer", "gyroscope";
status = "disabled";
};
ar0234_a@30 {
status = "disabled";
def-addr = <0x10>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "a";
has-eeprom;
eeprom-addr = <0x40>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
};
ar0234_b@31 {
status = "disabled";
def-addr = <0x18>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "a";
has-eeprom;
eeprom-addr = <0x40>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
};
};
i2c@1 {
reg = <1>;
i2c-mux,deselect-on-exit;
#address-cells = <1>;
#size-cells = <0>;
ar0234_c@32 {
status = "disabled";
def-addr = <0x10>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "a";
has-eeprom;
eeprom-addr = <0x15>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
};
ar0234_d@33 {
status = "disabled";
def-addr = <0x18>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "a";
has-eeprom;
eeprom-addr = <0x15>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
};
ar0234_e@34 {
status = "disabled";
def-addr = <0x10>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "a";
has-eeprom;
eeprom-addr = <0x44>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
};
ar0234_f@35 {
status = "disabled";
def-addr = <0x18>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "a";
has-eeprom;
eeprom-addr = <0x44>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
};
ar0234_g@36 {
status = "disabled";
def-addr = <0x10>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "a";
has-eeprom;
eeprom-addr = <0x46>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
};
ar0234_h@37 {
status = "disabled";
def-addr = <0x18>;
/* Define any required hw resources needed by driver */
/* ie. clocks, io pins, power sources */
clocks = <&bpmp TEGRA234_CLK_EXTPERIPH1>,
<&bpmp TEGRA234_CLK_EXTPERIPH1>;
clock-names = "extperiph1", "pllp_grtba";
mclk = "extperiph1";
channel = "a";
has-eeprom;
eeprom-addr = <0x46>;
reset-gpios = <&gpio CAM0_RST_L GPIO_ACTIVE_HIGH>;
pwdn-gpios = <&gpio CAM0_PWDN GPIO_ACTIVE_HIGH>;
pwr-gpios = <&gpio PWR_EN GPIO_ACTIVE_HIGH>;
};
};
};
};
};
};
};
fragment-cam-cdi-tsc@0 {
target-path = "/";
__overlay__ {
tsc_sig_gen@c6a0000 {
status = "okay";
generator@380 {
status = "okay";
};
};
};
};
};