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nv-soc: qspi: set qspi parent and frequency

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Configure the QSPI controller parent clock
to PLLC and set the required frequency.

Bug 4509953
Bug 4474594

Signed-off-by: Vishwaroop A <va@nvidia.com>
Change-Id: I9d258778e8ee7932d2bcbd5b3c8b648d9b339624
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3089397
Reviewed-by: Bibek Basu <bbasu@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
Reviewed-by: svcacv <svcacv@nvidia.com>
This commit is contained in:
Vishwaroop A
2024-03-05 05:16:31 +00:00
committed by mobile promotions
parent 4d11ffa2b4
commit 7577f8b531
1 changed files with 5 additions and 0 deletions
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5
nv-soc/tegra234-base-overlay.dtsi
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@@ -423,6 +423,11 @@
dma-names = "rx", "tx"; dma-names = "rx", "tx";
dma-coherent; dma-coherent;
iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>; iommus = <&smmu_niso1 TEGRA234_SID_QSPI0>;
assigned-clocks = <&bpmp TEGRA234_CLK_QSPI0_2X_PM>,
<&bpmp TEGRA234_CLK_QSPI0_PM>;
assigned-clock-parents = <&bpmp TEGRA234_CLK_PLLC>,
<&bpmp TEGRA234_CLK_QSPI0_2X_PM>;
assigned-clock-rates = <199999998 99999999>;
}; };
hardware-timestamp@3aa0000 { hardware-timestamp@3aa0000 {