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t23x: overlay: Add uphy lane number and intr in p2u nodes

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UPHY lane number is required to exchange lane margin data between P2U
and UPHY. Add uphy lane number in p2u device tree nodes.

Bug 3868928
Bug 3970434

Change-Id: Ia0880f33a6818cd673de491ca151686632664dcb
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/linux-stable/+/2815718
(cherry picked from commit 4525ffc4d523786008ac443f906f53d18e55f8bd)
Signed-off-by: Petlozu Pravareshwar <petlozup@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/soc/t23x-generic-dts/+/2859928
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
This commit is contained in:
Petlozu Pravareshwar
2023-02-21 11:14:33 +00:00
committed by Laxman Dewangan
parent d59eb27c88
commit 8c8ae3b243
1 changed files with 175 additions and 0 deletions
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175
overlay/tegra234-soc-overlay.dtsi
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@@ -11,7 +11,9 @@
#include <dt-bindings/memory/tegra234-smmu-streamid.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt/tegra234-irq.h>
#include <dt-bindings/gpio/tegra234-gpio.h>
#include <dt-bindings/p2u/tegra234-p2u.h>
#include <dt-bindings/power/tegra234-powergate.h>
#include "tegra234-soc-display-overlay.dtsi"
@@ -1231,4 +1233,177 @@
};
};
};
fragment-t234@10 {
target-path = "/bus@0";
__overlay__ {
p2u_hsio_0: phy@3e00000 {
interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L0_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID0>;
};
p2u_hsio_1: phy@3e10000 {
interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L1_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID1>;
};
p2u_hsio_2: phy@3e20000 {
interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L2_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID2>;
};
p2u_hsio_3: phy@3e30000 {
interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L3_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID3>;
};
p2u_hsio_4: phy@3e40000 {
interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L4_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID4>;
};
p2u_hsio_5: phy@3e50000 {
interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L5_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID5>;
};
p2u_hsio_6: phy@3e60000 {
interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L6_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID6>;
};
p2u_hsio_7: phy@3e70000 {
interrupts = <GIC_SPI TEGRA234_IRQ_HSIO_L7_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID7>;
};
p2u_nvhs_0: phy@3e90000 {
interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L0_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID8>;
};
p2u_nvhs_1: phy@3ea0000 {
interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L1_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID9>;
};
p2u_nvhs_2: phy@3eb0000 {
interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L2_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID10>;
};
p2u_nvhs_3: phy@3ec0000 {
interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L3_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID11>;
};
p2u_nvhs_4: phy@3ed0000 {
interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L4_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID12>;
};
p2u_nvhs_5: phy@3ee0000 {
interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L5_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID13>;
};
p2u_nvhs_6: phy@3ef0000 {
interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L6_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID14>;
};
p2u_nvhs_7: phy@3f00000 {
interrupts = <GIC_SPI TEGRA234_IRQ_NVHS_L7_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID15>;
};
p2u_gbe_0: phy@3f20000 {
interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L0_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID16>;
};
p2u_gbe_1: phy@3f30000 {
interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L1_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID17>;
};
p2u_gbe_2: phy@3f40000 {
interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L2_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID18>;
};
p2u_gbe_3: phy@3f50000 {
interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L3_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID19>;
};
p2u_gbe_4: phy@3f60000 {
interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L4_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID20>;
};
p2u_gbe_5: phy@3f70000 {
interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L5_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID21>;
};
p2u_gbe_6: phy@3f80000 {
interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L6_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID22>;
};
p2u_gbe_7: phy@3f90000 {
interrupts = <GIC_SPI TEGRA234_IRQ_GBE_L7_P2U IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "intr";
nvidia,bpmp = <&bpmp TEGRA234_P2U_LANE_ID23>;
};
};
};
};