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nv-public: fix indentation for nv-dtb includes

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As a final step in changing overlay fragments to includes
for nv dtb files, fix the indentation.

Bug 4290389

Change-Id: Ib7be8c925a33b5d30b93a8a8491ea8fe6419f2a4
Signed-off-by: Brad Griffis <bgriffis@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/c/device/hardware/nvidia/t23x-public-dts/+/3005704
Reviewed-by: svcacv <svcacv@nvidia.com>
Reviewed-by: Jonathan Hunter <jonathanh@nvidia.com>
GVS: Gerrit_Virtual_Submit <buildbot_gerritrpt@nvidia.com>
This commit is contained in:
Brad Griffis
2023-10-28 13:29:51 +00:00
committed by mobile promotions
parent ef304f6995
commit 955b31bed3
24 changed files with 8975 additions and 8975 deletions
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4
nv-soc/tegra234-base-overlay.dtsi
View File

@@ -300,11 +300,11 @@
"eqos_rx_m", "eqos_rx_input", "eqos_rx_m", "eqos_rx_input",
"eqos_macsec_tx", "eqos_tx_divider", "eqos_macsec_tx", "eqos_tx_divider",
"eqos_macsec_rx"; "eqos_macsec_rx";
#if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2 #if TEGRA_IOMMU_DT_VERSION >= DT_VERSION_2
interconnects = <&mc TEGRA234_MEMORY_CLIENT_EQOSR>, interconnects = <&mc TEGRA234_MEMORY_CLIENT_EQOSR>,
<&mc TEGRA234_MEMORY_CLIENT_EQOSW>; <&mc TEGRA234_MEMORY_CLIENT_EQOSW>;
interconnect-names = "dma-mem", "write"; interconnect-names = "dma-mem", "write";
#endif #endif
iommus = <&smmu_niso1 TEGRA234_SID_EQOS>; iommus = <&smmu_niso1 TEGRA234_SID_EQOS>;
nvidia,num-dma-chans = <8>; nvidia,num-dma-chans = <8>;
nvidia,num-mtl-queues = <8>; nvidia,num-mtl-queues = <8>;

24
nv-soc/tegra234-soc-safetyservice-fsicom.dtsi
View File

@@ -5,7 +5,7 @@
#include <dt-bindings/memory/tegra234-mc.h> #include <dt-bindings/memory/tegra234-mc.h>
/ { / {
reserved-memory { reserved-memory {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
ranges; ranges;
@@ -18,9 +18,9 @@
iommu-addresses = <&fsicom_client_inst1 0x0 0x0 0x0 0xf0000000>, iommu-addresses = <&fsicom_client_inst1 0x0 0x0 0x0 0xf0000000>,
<&fsicom_client_inst1 0x0 0xf1000000 0xffffffff 0x0effffff>; <&fsicom_client_inst1 0x0 0xf1000000 0xffffffff 0x0effffff>;
}; };
}; };
fsicom_client: fsicom_client { fsicom_client: fsicom_client {
compatible = "nvidia,tegra234-fsicom-client"; compatible = "nvidia,tegra234-fsicom-client";
#if TEGRA_HSP_DT_VERSION >= DT_VERSION_2 #if TEGRA_HSP_DT_VERSION >= DT_VERSION_2
mboxes = mboxes =
@@ -45,16 +45,16 @@
smmu_inst = <0>; smmu_inst = <0>;
max_fsi_core=<1>; /*Value 1 <-> core 0, value 2 <-> core0,1*/ max_fsi_core=<1>; /*Value 1 <-> core 0, value 2 <-> core0,1*/
status = "disabled"; status = "disabled";
}; };
fsicom_client_inst1: fsicom_client_inst1 { fsicom_client_inst1: fsicom_client_inst1 {
compatible = "nvidia,tegra234-fsicom-client"; compatible = "nvidia,tegra234-fsicom-client";
iommus = <&smmu_niso1 TEGRA234_SID_NISO1_FSI_CPU1>; iommus = <&smmu_niso1 TEGRA234_SID_NISO1_FSI_CPU1>;
memory-region = <&fsicom_resv_inst1>; memory-region = <&fsicom_resv_inst1>;
dma-coherent; dma-coherent;
smmu_inst = <1>; smmu_inst = <1>;
status = "okay"; status = "okay";
}; };
safetyservices_epl_client@110000 { safetyservices_epl_client@110000 {
compatible = "nvidia,tegra234-epl-client"; compatible = "nvidia,tegra234-epl-client";
#if TEGRA_HSP_DT_VERSION >= DT_VERSION_2 #if TEGRA_HSP_DT_VERSION >= DT_VERSION_2
mboxes = mboxes =
@@ -91,8 +91,8 @@
#endif #endif
status = "disabled"; status = "disabled";
}; };
FsiComIvc { FsiComIvc {
compatible = "nvidia,tegra-fsicom-channels"; compatible = "nvidia,tegra-fsicom-channels";
status = "disabled"; status = "disabled";
nChannel=<7>; nChannel=<7>;
@@ -137,11 +137,11 @@
frame-size = <10240>; frame-size = <10240>;
core-id = <0>; core-id = <0>;
}; };
}; };
FsiComClientChConfigEpd{ FsiComClientChConfigEpd{
compatible = "nvidia,tegra-fsicom-EPD"; compatible = "nvidia,tegra-fsicom-EPD";
status = "disabled"; status = "disabled";
channelid_list = <0>; channelid_list = <0>;
}; };
}; };